2 * OMAP DMA handling defines and function
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #ifndef __ASM_ARCH_DMA_H
22 #define __ASM_ARCH_DMA_H
24 #include <linux/platform_device.h>
26 #define INT_DMA_LCD 25
28 #define OMAP1_DMA_TOUT_IRQ (1 << 0)
29 #define OMAP_DMA_DROP_IRQ (1 << 1)
30 #define OMAP_DMA_HALF_IRQ (1 << 2)
31 #define OMAP_DMA_FRAME_IRQ (1 << 3)
32 #define OMAP_DMA_LAST_IRQ (1 << 4)
33 #define OMAP_DMA_BLOCK_IRQ (1 << 5)
34 #define OMAP1_DMA_SYNC_IRQ (1 << 6)
35 #define OMAP2_DMA_PKT_IRQ (1 << 7)
36 #define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
37 #define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
38 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
39 #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
41 #define OMAP_DMA_CCR_EN (1 << 7)
42 #define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
43 #define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
44 #define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
45 #define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
47 #define OMAP_DMA_DATA_TYPE_S8 0x00
48 #define OMAP_DMA_DATA_TYPE_S16 0x01
49 #define OMAP_DMA_DATA_TYPE_S32 0x02
51 #define OMAP_DMA_SYNC_ELEMENT 0x00
52 #define OMAP_DMA_SYNC_FRAME 0x01
53 #define OMAP_DMA_SYNC_BLOCK 0x02
54 #define OMAP_DMA_SYNC_PACKET 0x03
56 #define OMAP_DMA_DST_SYNC_PREFETCH 0x02
57 #define OMAP_DMA_SRC_SYNC 0x01
58 #define OMAP_DMA_DST_SYNC 0x00
60 #define OMAP_DMA_PORT_EMIFF 0x00
61 #define OMAP_DMA_PORT_EMIFS 0x01
62 #define OMAP_DMA_PORT_OCP_T1 0x02
63 #define OMAP_DMA_PORT_TIPB 0x03
64 #define OMAP_DMA_PORT_OCP_T2 0x04
65 #define OMAP_DMA_PORT_MPUI 0x05
67 #define OMAP_DMA_AMODE_CONSTANT 0x00
68 #define OMAP_DMA_AMODE_POST_INC 0x01
69 #define OMAP_DMA_AMODE_SINGLE_IDX 0x02
70 #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
72 #define DMA_DEFAULT_FIFO_DEPTH 0x10
73 #define DMA_DEFAULT_ARB_RATE 0x01
74 /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
75 #define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
76 #define DMA_THREAD_RESERVE_ONET (0x01 << 12)
77 #define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
78 #define DMA_THREAD_RESERVE_THREET (0x03 << 12)
79 #define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
80 #define DMA_THREAD_FIFO_75 (0x01 << 14)
81 #define DMA_THREAD_FIFO_25 (0x02 << 14)
82 #define DMA_THREAD_FIFO_50 (0x03 << 14)
84 /* DMA4_OCP_SYSCONFIG bits */
85 #define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
86 #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
87 #define DMA_SYSCONFIG_EMUFREE (1 << 5)
88 #define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
89 #define DMA_SYSCONFIG_SOFTRESET (1 << 2)
90 #define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
92 #define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
93 #define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
95 #define DMA_IDLEMODE_SMARTIDLE 0x2
96 #define DMA_IDLEMODE_NO_IDLE 0x1
97 #define DMA_IDLEMODE_FORCE_IDLE 0x0
100 #ifndef CONFIG_ARCH_OMAP1
101 #define OMAP_DMA_STATIC_CHAIN 0x1
102 #define OMAP_DMA_DYNAMIC_CHAIN 0x2
103 #define OMAP_DMA_CHAIN_ACTIVE 0x1
104 #define OMAP_DMA_CHAIN_INACTIVE 0x0
107 #define DMA_CH_PRIO_HIGH 0x1
108 #define DMA_CH_PRIO_LOW 0x0 /* Def */
110 /* Errata handling */
111 #define IS_DMA_ERRATA(id) (errata & (id))
112 #define SET_DMA_ERRATA(id) (errata |= (id))
114 #define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
115 #define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
116 #define DMA_ERRATA_i378 BIT(0x2)
117 #define DMA_ERRATA_i541 BIT(0x3)
118 #define DMA_ERRATA_i88 BIT(0x4)
119 #define DMA_ERRATA_3_3 BIT(0x5)
120 #define DMA_ROMCODE_BUG BIT(0x6)
122 /* Attributes for OMAP DMA Contrller */
123 #define DMA_LINKED_LCH BIT(0x0)
124 #define GLOBAL_PRIORITY BIT(0x1)
125 #define RESERVE_CHANNEL BIT(0x2)
126 #define IS_CSSA_32 BIT(0x3)
127 #define IS_CDSA_32 BIT(0x4)
128 #define IS_RW_PRIORITY BIT(0x5)
129 #define ENABLE_1510_MODE BIT(0x6)
130 #define SRC_PORT BIT(0x7)
131 #define DST_PORT BIT(0x8)
132 #define SRC_INDEX BIT(0x9)
133 #define DST_INDEX BIT(0xA)
134 #define IS_BURST_ONLY4 BIT(0xB)
135 #define CLEAR_CSR_ON_READ BIT(0xC)
136 #define IS_WORD_16 BIT(0xD)
138 /* Defines for DMA Capabilities */
139 #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
140 #define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
141 #define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
143 enum omap_reg_offsets {
145 GCR, GSCR, GRST1, HW_ID,
146 PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
147 PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
148 CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
149 PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
150 IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
151 IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
154 /* omap1+ specific */
157 /* Common registers for all omap's */
158 CSDP, CCR, CICR, CSR,
159 CEN, CFN, CSFI, CSEI,
163 /* Channel specific registers */
167 /* omap3630 and omap4 specific */
172 enum omap_dma_burst_mode {
173 OMAP_DMA_DATA_BURST_DIS = 0,
174 OMAP_DMA_DATA_BURST_4,
175 OMAP_DMA_DATA_BURST_8,
176 OMAP_DMA_DATA_BURST_16,
180 OMAP_DMA_LITTLE_ENDIAN = 0,
184 enum omap_dma_color_mode {
185 OMAP_DMA_COLOR_DIS = 0,
186 OMAP_DMA_CONSTANT_FILL,
187 OMAP_DMA_TRANSPARENT_COPY
190 enum omap_dma_write_mode {
191 OMAP_DMA_WRITE_NON_POSTED = 0,
192 OMAP_DMA_WRITE_POSTED,
193 OMAP_DMA_WRITE_LAST_NON_POSTED
196 enum omap_dma_channel_mode {
203 struct omap_dma_channel_params {
204 int data_type; /* data type 8,16,32 */
205 int elem_count; /* number of elements in a frame */
206 int frame_count; /* number of frames in a element */
208 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
209 int src_amode; /* constant, post increment, indexed,
211 unsigned long src_start; /* source address : physical */
212 int src_ei; /* source element index */
213 int src_fi; /* source frame index */
215 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
216 int dst_amode; /* constant, post increment, indexed,
218 unsigned long dst_start; /* source address : physical */
219 int dst_ei; /* source element index */
220 int dst_fi; /* source frame index */
222 int trigger; /* trigger attached if the channel is
224 int sync_mode; /* sycn on element, frame , block or packet */
225 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
227 int ie; /* interrupt enabled */
229 unsigned char read_prio;/* read priority */
230 unsigned char write_prio;/* write priority */
232 #ifndef CONFIG_ARCH_OMAP1
233 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
237 struct omap_dma_lch {
242 const char *dev_name;
243 void (*callback)(int lch, u16 ch_status, void *data);
246 /* required for Dynamic chaining */
254 struct omap_dma_dev_attr {
258 struct omap_dma_lch *chan;
261 /* System DMA platform data structure */
262 struct omap_system_dma_plat_info {
263 struct omap_dma_dev_attr *dma_attr;
265 void (*disable_irq_lch)(int lch);
266 void (*show_dma_caps)(void);
267 void (*clear_lch_regs)(int lch);
268 void (*clear_dma)(int lch);
269 void (*dma_write)(u32 val, int reg, int lch);
270 u32 (*dma_read)(int reg, int lch);
273 extern void __init omap_init_consistent_dma_size(void);
274 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
275 extern int omap_request_dma(int dev_id, const char *dev_name,
276 void (*callback)(int lch, u16 ch_status, void *data),
277 void *data, int *dma_ch);
278 extern void omap_enable_dma_irq(int ch, u16 irq_bits);
279 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
280 extern void omap_free_dma(int ch);
281 extern void omap_start_dma(int lch);
282 extern void omap_stop_dma(int lch);
283 extern void omap_set_dma_transfer_params(int lch, int data_type,
284 int elem_count, int frame_count,
286 int dma_trigger, int src_or_dst_synch);
287 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
289 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
290 extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
292 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
293 unsigned long src_start,
294 int src_ei, int src_fi);
295 extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
296 extern void omap_set_dma_src_data_pack(int lch, int enable);
297 extern void omap_set_dma_src_burst_mode(int lch,
298 enum omap_dma_burst_mode burst_mode);
300 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
301 unsigned long dest_start,
302 int dst_ei, int dst_fi);
303 extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
304 extern void omap_set_dma_dest_data_pack(int lch, int enable);
305 extern void omap_set_dma_dest_burst_mode(int lch,
306 enum omap_dma_burst_mode burst_mode);
308 extern void omap_set_dma_params(int lch,
309 struct omap_dma_channel_params *params);
311 extern void omap_dma_link_lch(int lch_head, int lch_queue);
312 extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
314 extern int omap_set_dma_callback(int lch,
315 void (*callback)(int lch, u16 ch_status, void *data),
317 extern dma_addr_t omap_get_dma_src_pos(int lch);
318 extern dma_addr_t omap_get_dma_dst_pos(int lch);
319 extern void omap_clear_dma(int lch);
320 extern int omap_get_dma_active_status(int lch);
321 extern int omap_dma_running(void);
322 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
324 extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
325 unsigned char write_prio);
326 extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
327 extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
328 extern int omap_get_dma_index(int lch, int *ei, int *fi);
330 void omap_dma_global_context_save(void);
331 void omap_dma_global_context_restore(void);
333 extern void omap_dma_disable_irq(int lch);
336 #ifndef CONFIG_ARCH_OMAP1
337 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
338 void (*callback) (int lch, u16 ch_status,
340 int *chain_id, int no_of_chans,
342 struct omap_dma_channel_params params);
343 extern int omap_free_dma_chain(int chain_id);
344 extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
345 int dest_start, int elem_count,
346 int frame_count, void *callbk_data);
347 extern int omap_start_dma_chain_transfers(int chain_id);
348 extern int omap_stop_dma_chain_transfers(int chain_id);
349 extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
350 extern int omap_get_dma_chain_dst_pos(int chain_id);
351 extern int omap_get_dma_chain_src_pos(int chain_id);
353 extern int omap_modify_dma_chain_params(int chain_id,
354 struct omap_dma_channel_params params);
355 extern int omap_dma_chain_status(int chain_id);
358 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
359 #include <mach/lcd_dma.h>
361 static inline int omap_lcd_dma_running(void)
367 #endif /* __ASM_ARCH_DMA_H */