arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-2012 Texas Instruments
  10  * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <plat/sram.h>
  29 #include <plat/board.h>
  30 #include <plat/cpu.h>
  31
  32 #include "sram.h"
  33
  34 /* XXX These "sideways" includes will disappear when sram.c becomes a driver */
  35 #include "../mach-omap2/iomap.h"
  36 #include "../mach-omap2/prm2xxx_3xxx.h"
  37 #include "../mach-omap2/sdrc.h"
  38
  39 #define OMAP1_SRAM_PA           0x20000000
  40 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
  41 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
  42 #ifdef CONFIG_OMAP4_ERRATA_I688
  43 #define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
  44 #else
  45 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  46 #endif
  47 #define OMAP5_SRAM_PA           0x40300000
  48
  49 #if defined(CONFIG_ARCH_OMAP2PLUS)
  50 #define SRAM_BOOTLOADER_SZ      0x00
  51 #else
  52 #define SRAM_BOOTLOADER_SZ      0x80
  53 #endif
  54
  55 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  56 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  57 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  58
  59 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  60 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  61 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  62 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  63 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  64
  65 #define GP_DEVICE               0x300
  66
  67 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  68
  69 static unsigned long omap_sram_start;
  70 static void __iomem *omap_sram_base;
  71 static unsigned long omap_sram_size;
  72 static void __iomem *omap_sram_ceil;
  73
  74 /*
  75  * Depending on the target RAMFS firewall setup, the public usable amount of
  76  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  77  * device allows ARM11 but not other initiators for full size. This
  78  * functionality seems ok until some nice security API happens.
  79  */
  80 static int is_sram_locked(void)
  81 {
  82         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  83                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  84                 if (cpu_is_omap242x()) {
  85                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  86                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  87                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  88                 }
  89                 if (cpu_is_omap34xx()) {
  90                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  91                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
  92                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  93                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
  94                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  95                 }
  96                 return 0;
  97         } else
  98                 return 1; /* assume locked with no PPA or security driver */
  99 }
 100
 101 /*
 102  * The amount of SRAM depends on the core type.
 103  * Note that we cannot try to test for SRAM here because writes
 104  * to secure SRAM will hang the system. Also the SRAM is not
 105  * yet mapped at this point.
 106  */
 107 static void __init omap_detect_sram(void)
 108 {
 109         if (cpu_class_is_omap2()) {
 110                 if (is_sram_locked()) {
 111                         if (cpu_is_omap34xx()) {
 112                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 113                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 114                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 115                                         omap_sram_size = 0x7000; /* 28K */
 116                                 } else {
 117                                         omap_sram_size = 0x8000; /* 32K */
 118                                 }
 119                         } else if (cpu_is_omap44xx()) {
 120                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 121                                 omap_sram_size = 0xa000; /* 40K */
 122                         } else if (soc_is_omap54xx()) {
 123                                 omap_sram_start = OMAP5_SRAM_PA;
 124                                 omap_sram_size = SZ_128K; /* 128KB */
 125                         } else {
 126                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 127                                 omap_sram_size = 0x800; /* 2K */
 128                         }
 129                 } else {
 130                         if (soc_is_am33xx()) {
 131                                 omap_sram_start = AM33XX_SRAM_PA;
 132                                 omap_sram_size = 0x10000; /* 64K */
 133                         } else if (cpu_is_omap34xx()) {
 134                                 omap_sram_start = OMAP3_SRAM_PA;
 135                                 omap_sram_size = 0x10000; /* 64K */
 136                         } else if (cpu_is_omap44xx()) {
 137                                 omap_sram_start = OMAP4_SRAM_PA;
 138                                 omap_sram_size = 0xe000; /* 56K */
 139                         } else if (soc_is_omap54xx()) {
 140                                 omap_sram_start = OMAP5_SRAM_PA;
 141                                 omap_sram_size = SZ_128K; /* 128KB */
 142                         } else {
 143                                 omap_sram_start = OMAP2_SRAM_PA;
 144                                 if (cpu_is_omap242x())
 145                                         omap_sram_size = 0xa0000; /* 640K */
 146                                 else if (cpu_is_omap243x())
 147                                         omap_sram_size = 0x10000; /* 64K */
 148                         }
 149                 }
 150         } else {
 151                 omap_sram_start = OMAP1_SRAM_PA;
 152
 153                 if (cpu_is_omap7xx())
 154                         omap_sram_size = 0x32000;       /* 200K */
 155                 else if (cpu_is_omap15xx())
 156                         omap_sram_size = 0x30000;       /* 192K */
 157                 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
 158                                 cpu_is_omap1621() || cpu_is_omap1710())
 159                         omap_sram_size = 0x4000;        /* 16K */
 160                 else {
 161                         pr_err("Could not detect SRAM size\n");
 162                         omap_sram_size = 0x4000;
 163                 }
 164         }
 165 }
 166
 167 /*
 168  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 169  */
 170 static void __init omap_map_sram(void)
 171 {
 172         int cached = 1;
 173
 174         if (omap_sram_size == 0)
 175                 return;
 176
 177 #ifdef CONFIG_OMAP4_ERRATA_I688
 178                 omap_sram_start += PAGE_SIZE;
 179                 omap_sram_size -= SZ_16K;
 180 #endif
 181         if (cpu_is_omap34xx()) {
 182                 /*
 183                  * SRAM must be marked as non-cached on OMAP3 since the
 184                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 185                  * SDRAM controller disabled, and if it is marked cached,
 186                  * the ARM may attempt to write cache lines back to SDRAM
 187                  * which will cause the system to hang.
 188                  */
 189                 cached = 0;
 190         }
 191
 192         omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
 193         omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
 194                                                 cached);
 195         if (!omap_sram_base) {
 196                 pr_err("SRAM: Could not map\n");
 197                 return;
 198         }
 199
 200         omap_sram_ceil = omap_sram_base + omap_sram_size;
 201
 202         /*
 203          * Looks like we need to preserve some bootloader code at the
 204          * beginning of SRAM for jumping to flash for reboot to work...
 205          */
 206         memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 207                   omap_sram_size - SRAM_BOOTLOADER_SZ);
 208 }
 209
 210 /*
 211  * Memory allocator for SRAM: calculates the new ceiling address
 212  * for pushing a function using the fncpy API.
 213  *
 214  * Note that fncpy requires the returned address to be aligned
 215  * to an 8-byte boundary.
 216  */
 217 void *omap_sram_push_address(unsigned long size)
 218 {
 219         unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
 220
 221         available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
 222
 223         if (size > available) {
 224                 pr_err("Not enough space in SRAM\n");
 225                 return NULL;
 226         }
 227
 228         new_ceil -= size;
 229         new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
 230         omap_sram_ceil = IOMEM(new_ceil);
 231
 232         return (void *)omap_sram_ceil;
 233 }
 234
 235 #ifdef CONFIG_ARCH_OMAP1
 236
 237 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 238
 239 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 240 {
 241         BUG_ON(!_omap_sram_reprogram_clock);
 242         /* On 730, bit 13 must always be 1 */
 243         if (cpu_is_omap7xx())
 244                 ckctl |= 0x2000;
 245         _omap_sram_reprogram_clock(dpllctl, ckctl);
 246 }
 247
 248 static int __init omap1_sram_init(void)
 249 {
 250         _omap_sram_reprogram_clock =
 251                         omap_sram_push(omap1_sram_reprogram_clock,
 252                                         omap1_sram_reprogram_clock_sz);
 253
 254         return 0;
 255 }
 256
 257 #else
 258 #define omap1_sram_init()       do {} while (0)
 259 #endif
 260
 261 #if defined(CONFIG_ARCH_OMAP2)
 262
 263 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 264                               u32 base_cs, u32 force_unlock);
 265
 266 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 267                    u32 base_cs, u32 force_unlock)
 268 {
 269         BUG_ON(!_omap2_sram_ddr_init);
 270         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 271                              base_cs, force_unlock);
 272 }
 273
 274 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 275                                           u32 mem_type);
 276
 277 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 278 {
 279         BUG_ON(!_omap2_sram_reprogram_sdrc);
 280         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 281 }
 282
 283 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 284
 285 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 286 {
 287         BUG_ON(!_omap2_set_prcm);
 288         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 289 }
 290 #endif
 291
 292 #ifdef CONFIG_SOC_OMAP2420
 293 static int __init omap242x_sram_init(void)
 294 {
 295         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 296                                         omap242x_sram_ddr_init_sz);
 297
 298         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 299                                             omap242x_sram_reprogram_sdrc_sz);
 300
 301         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 302                                          omap242x_sram_set_prcm_sz);
 303
 304         return 0;
 305 }
 306 #else
 307 static inline int omap242x_sram_init(void)
 308 {
 309         return 0;
 310 }
 311 #endif
 312
 313 #ifdef CONFIG_SOC_OMAP2430
 314 static int __init omap243x_sram_init(void)
 315 {
 316         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 317                                         omap243x_sram_ddr_init_sz);
 318
 319         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 320                                             omap243x_sram_reprogram_sdrc_sz);
 321
 322         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 323                                          omap243x_sram_set_prcm_sz);
 324
 325         return 0;
 326 }
 327 #else
 328 static inline int omap243x_sram_init(void)
 329 {
 330         return 0;
 331 }
 332 #endif
 333
 334 #ifdef CONFIG_ARCH_OMAP3
 335
 336 static u32 (*_omap3_sram_configure_core_dpll)(
 337                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 338                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 339                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 340                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 341                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 342
 343 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 344                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 345                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 346                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 347                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 348 {
 349         BUG_ON(!_omap3_sram_configure_core_dpll);
 350         return _omap3_sram_configure_core_dpll(
 351                         m2, unlock_dll, f, inc,
 352                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 353                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 354                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 355                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 356 }
 357
 358 void omap3_sram_restore_context(void)
 359 {
 360         omap_sram_ceil = omap_sram_base + omap_sram_size;
 361
 362         _omap3_sram_configure_core_dpll =
 363                 omap_sram_push(omap3_sram_configure_core_dpll,
 364                                omap3_sram_configure_core_dpll_sz);
 365         omap_push_sram_idle();
 366 }
 367
 368 static inline int omap34xx_sram_init(void)
 369 {
 370         omap3_sram_restore_context();
 371         return 0;
 372 }
 373 #else
 374 static inline int omap34xx_sram_init(void)
 375 {
 376         return 0;
 377 }
 378 #endif /* CONFIG_ARCH_OMAP3 */
 379
 380 static inline int am33xx_sram_init(void)
 381 {
 382         return 0;
 383 }
 384
 385 int __init omap_sram_init(void)
 386 {
 387         omap_detect_sram();
 388         omap_map_sram();
 389
 390         if (!(cpu_class_is_omap2()))
 391                 omap1_sram_init();
 392         else if (cpu_is_omap242x())
 393                 omap242x_sram_init();
 394         else if (cpu_is_omap2430())
 395                 omap243x_sram_init();
 396         else if (soc_is_am33xx())
 397                 am33xx_sram_init();
 398         else if (cpu_is_omap34xx())
 399                 omap34xx_sram_init();
 400
 401         return 0;
 402 }