3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_GCOV_PROFILE_ALL
6 select ARCH_HAS_SG_CHAIN
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_WANT_OPTIONAL_GPIOLIB
11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
12 select ARCH_WANT_FRAME_POINTERS
16 select AUDIT_ARCH_COMPAT_GENERIC
17 select ARM_GIC_V2M if PCI_MSI
19 select ARM_GIC_V3_ITS if PCI_MSI
20 select BUILDTIME_EXTABLE_SORT
21 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS
25 select GENERIC_ALLOCATOR
26 select GENERIC_CLOCKEVENTS
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_CPU_AUTOPROBE
29 select GENERIC_EARLY_IOREMAP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_PCI_IOMAP
33 select GENERIC_SCHED_CLOCK
34 select GENERIC_SMP_IDLE_THREAD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
37 select GENERIC_TIME_VSYSCALL
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_JUMP_LABEL
44 select HAVE_ARCH_SECCOMP_FILTER
45 select HAVE_ARCH_TRACEHOOK
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_CC_STACKPROTECTOR
49 select HAVE_CMPXCHG_DOUBLE
50 select HAVE_DEBUG_BUGVERBOSE
51 select HAVE_DEBUG_KMEMLEAK
52 select HAVE_DMA_API_DEBUG
54 select HAVE_DMA_CONTIGUOUS
55 select HAVE_DYNAMIC_FTRACE
56 select HAVE_EFFICIENT_UNALIGNED_ACCESS
57 select HAVE_FTRACE_MCOUNT_RECORD
58 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
60 select HAVE_GENERIC_DMA_COHERENT
61 select HAVE_HW_BREAKPOINT if PERF_EVENTS
63 select HAVE_PATA_PLATFORM
64 select HAVE_PERF_EVENTS
66 select HAVE_PERF_USER_STACK_DUMP
67 select HAVE_RCU_TABLE_FREE
68 select HAVE_SYSCALL_TRACEPOINTS
70 select MODULES_USE_ELF_RELA
73 select OF_EARLY_FLATTREE
74 select OF_RESERVED_MEM
75 select PERF_USE_VMALLOC
80 select SYSCTL_EXCEPTION_TRACE
81 select HAVE_CONTEXT_TRACKING
83 ARM 64-bit (AArch64) Linux support.
88 config ARCH_PHYS_ADDR_T_64BIT
97 config STACKTRACE_SUPPORT
100 config LOCKDEP_SUPPORT
103 config TRACE_IRQFLAGS_SUPPORT
106 config RWSEM_XCHGADD_ALGORITHM
109 config GENERIC_HWEIGHT
115 config GENERIC_CALIBRATE_DELAY
121 config HAVE_GENERIC_RCU_GUP
124 config ARCH_DMA_ADDR_T_64BIT
127 config NEED_DMA_MAP_STATE
130 config NEED_SG_DMA_LENGTH
139 config KERNEL_MODE_NEON
142 config FIX_EARLYCON_MEM
145 source "init/Kconfig"
147 source "kernel/Kconfig.freezer"
149 menu "Platform selection"
154 This enables support for Samsung Exynos SoC family
157 bool "ARMv8 based Samsung Exynos7"
159 select COMMON_CLK_SAMSUNG
160 select HAVE_S3C2410_WATCHDOG if WATCHDOG
161 select HAVE_S3C_RTC if RTC_CLASS
163 select PINCTRL_EXYNOS
166 This enables support for Samsung Exynos7 SoC family
169 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
172 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
175 bool "AMD Seattle SoC Family"
177 This enables support for AMD Seattle SOC Family
180 bool "NVIDIA Tegra SoC Family"
181 select ARCH_HAS_RESET_CONTROLLER
182 select ARCH_REQUIRE_GPIOLIB
186 select GENERIC_CLOCKEVENTS
190 select RESET_CONTROLLER
192 This enables support for the NVIDIA Tegra SoC family.
194 config ARCH_TEGRA_132_SOC
195 bool "NVIDIA Tegra132 SoC"
196 depends on ARCH_TEGRA
197 select PINCTRL_TEGRA124
198 select USB_ARCH_HAS_EHCI if USB_SUPPORT
199 select USB_ULPI if USB_PHY
200 select USB_ULPI_VIEWPORT if USB_PHY
202 Enable support for NVIDIA Tegra132 SoC, based on the Denver
203 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
204 but contains an NVIDIA Denver CPU complex in place of
205 Tegra124's "4+1" Cortex-A15 CPU complex.
207 config ARCH_FSL_LS2085A
208 bool "Freescale LS2085A SOC"
210 This enables support for Freescale LS2085A SOC.
213 bool "Cavium Inc. Thunder SoC Family"
215 This enables support for Cavium's Thunder Family of SoCs.
218 bool "ARMv8 software model (Versatile Express)"
219 select ARCH_REQUIRE_GPIOLIB
220 select COMMON_CLK_VERSATILE
221 select POWER_RESET_VEXPRESS
222 select VEXPRESS_CONFIG
224 This enables support for the ARMv8 software model (Versatile
228 bool "AppliedMicro X-Gene SOC Family"
230 This enables support for AppliedMicro X-Gene SOC Family
239 This feature enables support for PCI bus system. If you say Y
240 here, the kernel will include drivers and infrastructure code
241 to support PCI bus devices.
246 config PCI_DOMAINS_GENERIC
252 source "drivers/pci/Kconfig"
253 source "drivers/pci/pcie/Kconfig"
254 source "drivers/pci/hotplug/Kconfig"
258 menu "Kernel Features"
260 menu "ARM errata workarounds via the alternatives framework"
262 config ARM64_ERRATUM_826319
263 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
266 This option adds an alternative code sequence to work around ARM
267 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
268 AXI master interface and an L2 cache.
270 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
271 and is unable to accept a certain write via this interface, it will
272 not progress on read data presented on the read data channel and the
275 The workaround promotes data cache clean instructions to
276 data cache clean-and-invalidate.
277 Please note that this does not necessarily enable the workaround,
278 as it depends on the alternative framework, which will only patch
279 the kernel if an affected CPU is detected.
283 config ARM64_ERRATUM_827319
284 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
287 This option adds an alternative code sequence to work around ARM
288 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
289 master interface and an L2 cache.
291 Under certain conditions this erratum can cause a clean line eviction
292 to occur at the same time as another transaction to the same address
293 on the AMBA 5 CHI interface, which can cause data corruption if the
294 interconnect reorders the two transactions.
296 The workaround promotes data cache clean instructions to
297 data cache clean-and-invalidate.
298 Please note that this does not necessarily enable the workaround,
299 as it depends on the alternative framework, which will only patch
300 the kernel if an affected CPU is detected.
304 config ARM64_ERRATUM_824069
305 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
308 This option adds an alternative code sequence to work around ARM
309 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
310 to a coherent interconnect.
312 If a Cortex-A53 processor is executing a store or prefetch for
313 write instruction at the same time as a processor in another
314 cluster is executing a cache maintenance operation to the same
315 address, then this erratum might cause a clean cache line to be
316 incorrectly marked as dirty.
318 The workaround promotes data cache clean instructions to
319 data cache clean-and-invalidate.
320 Please note that this option does not necessarily enable the
321 workaround, as it depends on the alternative framework, which will
322 only patch the kernel if an affected CPU is detected.
326 config ARM64_ERRATUM_819472
327 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
330 This option adds an alternative code sequence to work around ARM
331 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
332 present when it is connected to a coherent interconnect.
334 If the processor is executing a load and store exclusive sequence at
335 the same time as a processor in another cluster is executing a cache
336 maintenance operation to the same address, then this erratum might
337 cause data corruption.
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_832075
348 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
351 This option adds an alternative code sequence to work around ARM
352 erratum 832075 on Cortex-A57 parts up to r1p2.
354 Affected Cortex-A57 parts might deadlock when exclusive load/store
355 instructions to Write-Back memory are mixed with Device loads.
357 The workaround is to promote device loads to use Load-Acquire
359 Please note that this does not necessarily enable the workaround,
360 as it depends on the alternative framework, which will only patch
361 the kernel if an affected CPU is detected.
370 default ARM64_4K_PAGES
372 Page size (translation granule) configuration.
374 config ARM64_4K_PAGES
377 This feature enables 4KB pages support.
379 config ARM64_64K_PAGES
382 This feature enables 64KB pages support (4KB by default)
383 allowing only two levels of page tables and faster TLB
384 look-up. AArch32 emulation is not available when this feature
390 prompt "Virtual address space size"
391 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
392 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
394 Allows choosing one of multiple possible virtual address
395 space sizes. The level of translation table is determined by
396 a combination of page size and virtual address space size.
398 config ARM64_VA_BITS_39
400 depends on ARM64_4K_PAGES
402 config ARM64_VA_BITS_42
404 depends on ARM64_64K_PAGES
406 config ARM64_VA_BITS_48
414 default 39 if ARM64_VA_BITS_39
415 default 42 if ARM64_VA_BITS_42
416 default 48 if ARM64_VA_BITS_48
418 config ARM64_PGTABLE_LEVELS
420 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
421 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
422 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
423 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
425 config CPU_BIG_ENDIAN
426 bool "Build big-endian kernel"
428 Say Y if you plan on running a kernel in big-endian mode.
431 bool "Symmetric Multi-Processing"
433 This enables support for systems with more than one CPU. If
434 you say N here, the kernel will run on single and
435 multiprocessor machines, but will use only one CPU of a
436 multiprocessor machine. If you say Y here, the kernel will run
437 on many, but not all, single processor machines. On a single
438 processor machine, the kernel will run faster if you say N
441 If you don't know what to do here, say N.
444 bool "Multi-core scheduler support"
447 Multi-core scheduler support improves the CPU scheduler's decision
448 making when dealing with multi-core CPU chips at a cost of slightly
449 increased overhead in some places. If unsure say N here.
452 bool "SMT scheduler support"
455 Improves the CPU scheduler's decision making when dealing with
456 MultiThreading at a cost of slightly increased overhead in some
457 places. If unsure say N here.
460 int "Maximum number of CPUs (2-64)"
463 # These have to remain sorted largest to smallest
467 bool "Support for hot-pluggable CPUs"
470 Say Y here to experiment with turning CPUs off and on. CPUs
471 can be controlled through /sys/devices/system/cpu.
473 source kernel/Kconfig.preempt
479 config ARCH_HAS_HOLES_MEMORYMODEL
480 def_bool y if SPARSEMEM
482 config ARCH_SPARSEMEM_ENABLE
484 select SPARSEMEM_VMEMMAP_ENABLE
486 config ARCH_SPARSEMEM_DEFAULT
487 def_bool ARCH_SPARSEMEM_ENABLE
489 config ARCH_SELECT_MEMORY_MODEL
490 def_bool ARCH_SPARSEMEM_ENABLE
492 config HAVE_ARCH_PFN_VALID
493 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
495 config HW_PERF_EVENTS
496 bool "Enable hardware performance counter support for perf events"
497 depends on PERF_EVENTS
500 Enable hardware performance counter support for perf events. If
501 disabled, perf events will use software events only.
503 config SYS_SUPPORTS_HUGETLBFS
506 config ARCH_WANT_GENERAL_HUGETLB
509 config ARCH_WANT_HUGE_PMD_SHARE
510 def_bool y if !ARM64_64K_PAGES
512 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
515 config ARCH_HAS_CACHE_LINE_SIZE
521 bool "Enable seccomp to safely compute untrusted bytecode"
523 This kernel feature is useful for number crunching applications
524 that may need to compute untrusted bytecode during their
525 execution. By using pipes or other transports made available to
526 the process as file descriptors supporting the read/write
527 syscalls, it's possible to isolate those applications in
528 their own address space using seccomp. Once seccomp is
529 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
530 and the task is only allowed to execute a few safe syscalls
531 defined by each seccomp mode.
538 bool "Xen guest support on ARM64"
539 depends on ARM64 && OF
542 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
544 config FORCE_MAX_ZONEORDER
546 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
549 menuconfig ARMV8_DEPRECATED
550 bool "Emulate deprecated/obsolete ARMv8 instructions"
553 Legacy software support may require certain instructions
554 that have been deprecated or obsoleted in the architecture.
556 Enable this config to enable selective emulation of these
564 bool "Emulate SWP/SWPB instructions"
566 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
567 they are always undefined. Say Y here to enable software
568 emulation of these instructions for userspace using LDXR/STXR.
570 In some older versions of glibc [<=2.8] SWP is used during futex
571 trylock() operations with the assumption that the code will not
572 be preempted. This invalid assumption may be more likely to fail
573 with SWP emulation enabled, leading to deadlock of the user
576 NOTE: when accessing uncached shared regions, LDXR/STXR rely
577 on an external transaction monitoring block called a global
578 monitor to maintain update atomicity. If your system does not
579 implement a global monitor, this option can cause programs that
580 perform SWP operations to uncached memory to deadlock.
584 config CP15_BARRIER_EMULATION
585 bool "Emulate CP15 Barrier instructions"
587 The CP15 barrier instructions - CP15ISB, CP15DSB, and
588 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
589 strongly recommended to use the ISB, DSB, and DMB
590 instructions instead.
592 Say Y here to enable software emulation of these
593 instructions for AArch32 userspace code. When this option is
594 enabled, CP15 barrier usage is traced which can help
595 identify software that needs updating.
606 string "Default kernel command string"
609 Provide a set of default command-line options at build time by
610 entering them here. As a minimum, you should specify the the
611 root device (e.g. root=/dev/nfs).
614 bool "Always use the default kernel command string"
616 Always use the default kernel command string, even if the boot
617 loader passes other arguments to the kernel.
618 This is useful if you cannot or don't want to change the
619 command-line options your boot loader passes to the kernel.
625 bool "UEFI runtime support"
626 depends on OF && !CPU_BIG_ENDIAN
629 select EFI_PARAMS_FROM_FDT
630 select EFI_RUNTIME_WRAPPERS
635 This option provides support for runtime services provided
636 by UEFI firmware (such as non-volatile variables, realtime
637 clock, and platform reset). A UEFI stub is also provided to
638 allow the kernel to be booted as an EFI application. This
639 is only useful on systems that have UEFI firmware.
642 bool "Enable support for SMBIOS (DMI) tables"
646 This enables SMBIOS/DMI feature for systems.
648 This option is only useful on systems that have UEFI firmware.
649 However, even with this option, the resultant kernel should
650 continue to boot on existing non-UEFI platforms.
654 menu "Userspace binary formats"
656 source "fs/Kconfig.binfmt"
659 bool "Kernel support for 32-bit EL0"
660 depends on !ARM64_64K_PAGES
661 select COMPAT_BINFMT_ELF
663 select OLD_SIGSUSPEND3
664 select COMPAT_OLD_SIGACTION
666 This option enables support for a 32-bit EL0 running under a 64-bit
667 kernel at EL1. AArch32-specific components such as system calls,
668 the user helper functions, VFP support and the ptrace interface are
669 handled appropriately by the kernel.
671 If you want to execute 32-bit userspace applications, say Y.
673 config SYSVIPC_COMPAT
675 depends on COMPAT && SYSVIPC
679 menu "Power management options"
681 source "kernel/power/Kconfig"
683 config ARCH_SUSPEND_POSSIBLE
686 config ARM64_CPU_SUSPEND
691 menu "CPU Power Management"
693 source "drivers/cpuidle/Kconfig"
695 source "drivers/cpufreq/Kconfig"
701 source "drivers/Kconfig"
703 source "drivers/firmware/Kconfig"
707 source "arch/arm64/kvm/Kconfig"
709 source "arch/arm64/Kconfig.debug"
711 source "security/Kconfig"
713 source "crypto/Kconfig"
715 source "arch/arm64/crypto/Kconfig"