3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ACPI_MCFG if ACPI
7 select ARCH_HAS_DEVMEM_IS_ALLOWED
8 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_GCOV_PROFILE_ALL
11 select ARCH_HAS_SG_CHAIN
12 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_SUPPORTS_ATOMIC_RMW
15 select ARCH_SUPPORTS_NUMA_BALANCING
16 select ARCH_WANT_OPTIONAL_GPIOLIB
17 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
18 select ARCH_WANT_FRAME_POINTERS
19 select ARCH_HAS_UBSAN_SANITIZE_ALL
23 select AUDIT_ARCH_COMPAT_GENERIC
24 select ARM_GIC_V2M if PCI
26 select ARM_GIC_V3_ITS if PCI
28 select BUILDTIME_EXTABLE_SORT
29 select CLONE_BACKWARDS
31 select CPU_PM if (SUSPEND || CPU_IDLE)
32 select DCACHE_WORD_ACCESS
35 select GENERIC_ALLOCATOR
36 select GENERIC_CLOCKEVENTS
37 select GENERIC_CLOCKEVENTS_BROADCAST
38 select GENERIC_CPU_AUTOPROBE
39 select GENERIC_EARLY_IOREMAP
40 select GENERIC_IDLE_POLL_SETUP
41 select GENERIC_IRQ_PROBE
42 select GENERIC_IRQ_SHOW
43 select GENERIC_IRQ_SHOW_LEVEL
44 select GENERIC_PCI_IOMAP
45 select GENERIC_SCHED_CLOCK
46 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_STRNCPY_FROM_USER
48 select GENERIC_STRNLEN_USER
49 select GENERIC_TIME_VSYSCALL
50 select HANDLE_DOMAIN_IRQ
51 select HARDIRQS_SW_RESEND
52 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
53 select HAVE_ARCH_AUDITSYSCALL
54 select HAVE_ARCH_BITREVERSE
55 select HAVE_ARCH_HUGE_VMAP
56 select HAVE_ARCH_JUMP_LABEL
57 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
59 select HAVE_ARCH_MMAP_RND_BITS
60 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
61 select HAVE_ARCH_SECCOMP_FILTER
62 select HAVE_ARCH_TRACEHOOK
63 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
66 select HAVE_C_RECORDMCOUNT
67 select HAVE_CC_STACKPROTECTOR
68 select HAVE_CMPXCHG_DOUBLE
69 select HAVE_CMPXCHG_LOCAL
70 select HAVE_CONTEXT_TRACKING
71 select HAVE_DEBUG_BUGVERBOSE
72 select HAVE_DEBUG_KMEMLEAK
73 select HAVE_DMA_API_DEBUG
74 select HAVE_DMA_CONTIGUOUS
75 select HAVE_DYNAMIC_FTRACE
76 select HAVE_EFFICIENT_UNALIGNED_ACCESS
77 select HAVE_FTRACE_MCOUNT_RECORD
78 select HAVE_FUNCTION_TRACER
79 select HAVE_FUNCTION_GRAPH_TRACER
80 select HAVE_GENERIC_DMA_COHERENT
81 select HAVE_HW_BREAKPOINT if PERF_EVENTS
82 select HAVE_IRQ_TIME_ACCOUNTING
84 select HAVE_MEMBLOCK_NODE_MAP if NUMA
85 select HAVE_PATA_PLATFORM
86 select HAVE_PERF_EVENTS
88 select HAVE_PERF_USER_STACK_DUMP
89 select HAVE_RCU_TABLE_FREE
90 select HAVE_SYSCALL_TRACEPOINTS
91 select IOMMU_DMA if IOMMU_SUPPORT
93 select IRQ_FORCED_THREADING
94 select MODULES_USE_ELF_RELA
97 select OF_EARLY_FLATTREE
98 select OF_NUMA if NUMA && OF
99 select OF_RESERVED_MEM
100 select PCI_ECAM if ACPI
101 select PERF_USE_VMALLOC
105 select SYSCTL_EXCEPTION_TRACE
107 ARM 64-bit (AArch64) Linux support.
112 config ARCH_PHYS_ADDR_T_64BIT
118 config ARM64_PAGE_SHIFT
120 default 16 if ARM64_64K_PAGES
121 default 14 if ARM64_16K_PAGES
124 config ARM64_CONT_SHIFT
126 default 5 if ARM64_64K_PAGES
127 default 7 if ARM64_16K_PAGES
130 config ARCH_MMAP_RND_BITS_MIN
131 default 14 if ARM64_64K_PAGES
132 default 16 if ARM64_16K_PAGES
135 # max bits determined by the following formula:
136 # VA_BITS - PAGE_SHIFT - 3
137 config ARCH_MMAP_RND_BITS_MAX
138 default 19 if ARM64_VA_BITS=36
139 default 24 if ARM64_VA_BITS=39
140 default 27 if ARM64_VA_BITS=42
141 default 30 if ARM64_VA_BITS=47
142 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
143 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
144 default 33 if ARM64_VA_BITS=48
145 default 14 if ARM64_64K_PAGES
146 default 16 if ARM64_16K_PAGES
149 config ARCH_MMAP_RND_COMPAT_BITS_MIN
150 default 7 if ARM64_64K_PAGES
151 default 9 if ARM64_16K_PAGES
154 config ARCH_MMAP_RND_COMPAT_BITS_MAX
160 config STACKTRACE_SUPPORT
163 config ILLEGAL_POINTER_VALUE
165 default 0xdead000000000000
167 config LOCKDEP_SUPPORT
170 config TRACE_IRQFLAGS_SUPPORT
173 config RWSEM_XCHGADD_ALGORITHM
180 config GENERIC_BUG_RELATIVE_POINTERS
182 depends on GENERIC_BUG
184 config GENERIC_HWEIGHT
190 config GENERIC_CALIBRATE_DELAY
196 config HAVE_GENERIC_RCU_GUP
199 config ARCH_DMA_ADDR_T_64BIT
202 config NEED_DMA_MAP_STATE
205 config NEED_SG_DMA_LENGTH
217 config KERNEL_MODE_NEON
220 config FIX_EARLYCON_MEM
223 config PGTABLE_LEVELS
225 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
226 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
227 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
228 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
229 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
230 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
236 source "arch/arm64/Kconfig.platforms"
243 This feature enables support for PCI bus system. If you say Y
244 here, the kernel will include drivers and infrastructure code
245 to support PCI bus devices.
250 config PCI_DOMAINS_GENERIC
256 source "drivers/pci/Kconfig"
260 menu "Kernel Features"
262 menu "ARM errata workarounds via the alternatives framework"
264 config ARM64_ERRATUM_826319
265 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
268 This option adds an alternative code sequence to work around ARM
269 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
270 AXI master interface and an L2 cache.
272 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
273 and is unable to accept a certain write via this interface, it will
274 not progress on read data presented on the read data channel and the
277 The workaround promotes data cache clean instructions to
278 data cache clean-and-invalidate.
279 Please note that this does not necessarily enable the workaround,
280 as it depends on the alternative framework, which will only patch
281 the kernel if an affected CPU is detected.
285 config ARM64_ERRATUM_827319
286 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
289 This option adds an alternative code sequence to work around ARM
290 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
291 master interface and an L2 cache.
293 Under certain conditions this erratum can cause a clean line eviction
294 to occur at the same time as another transaction to the same address
295 on the AMBA 5 CHI interface, which can cause data corruption if the
296 interconnect reorders the two transactions.
298 The workaround promotes data cache clean instructions to
299 data cache clean-and-invalidate.
300 Please note that this does not necessarily enable the workaround,
301 as it depends on the alternative framework, which will only patch
302 the kernel if an affected CPU is detected.
306 config ARM64_ERRATUM_824069
307 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
310 This option adds an alternative code sequence to work around ARM
311 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
312 to a coherent interconnect.
314 If a Cortex-A53 processor is executing a store or prefetch for
315 write instruction at the same time as a processor in another
316 cluster is executing a cache maintenance operation to the same
317 address, then this erratum might cause a clean cache line to be
318 incorrectly marked as dirty.
320 The workaround promotes data cache clean instructions to
321 data cache clean-and-invalidate.
322 Please note that this option does not necessarily enable the
323 workaround, as it depends on the alternative framework, which will
324 only patch the kernel if an affected CPU is detected.
328 config ARM64_ERRATUM_819472
329 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
332 This option adds an alternative code sequence to work around ARM
333 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
334 present when it is connected to a coherent interconnect.
336 If the processor is executing a load and store exclusive sequence at
337 the same time as a processor in another cluster is executing a cache
338 maintenance operation to the same address, then this erratum might
339 cause data corruption.
341 The workaround promotes data cache clean instructions to
342 data cache clean-and-invalidate.
343 Please note that this does not necessarily enable the workaround,
344 as it depends on the alternative framework, which will only patch
345 the kernel if an affected CPU is detected.
349 config ARM64_ERRATUM_832075
350 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
353 This option adds an alternative code sequence to work around ARM
354 erratum 832075 on Cortex-A57 parts up to r1p2.
356 Affected Cortex-A57 parts might deadlock when exclusive load/store
357 instructions to Write-Back memory are mixed with Device loads.
359 The workaround is to promote device loads to use Load-Acquire
361 Please note that this does not necessarily enable the workaround,
362 as it depends on the alternative framework, which will only patch
363 the kernel if an affected CPU is detected.
367 config ARM64_ERRATUM_834220
368 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
372 This option adds an alternative code sequence to work around ARM
373 erratum 834220 on Cortex-A57 parts up to r1p2.
375 Affected Cortex-A57 parts might report a Stage 2 translation
376 fault as the result of a Stage 1 fault for load crossing a
377 page boundary when there is a permission or device memory
378 alignment fault at Stage 1 and a translation fault at Stage 2.
380 The workaround is to verify that the Stage 1 translation
381 doesn't generate a fault before handling the Stage 2 fault.
382 Please note that this does not necessarily enable the workaround,
383 as it depends on the alternative framework, which will only patch
384 the kernel if an affected CPU is detected.
388 config ARM64_ERRATUM_845719
389 bool "Cortex-A53: 845719: a load might read incorrect data"
393 This option adds an alternative code sequence to work around ARM
394 erratum 845719 on Cortex-A53 parts up to r0p4.
396 When running a compat (AArch32) userspace on an affected Cortex-A53
397 part, a load at EL0 from a virtual address that matches the bottom 32
398 bits of the virtual address used by a recent load at (AArch64) EL1
399 might return incorrect data.
401 The workaround is to write the contextidr_el1 register on exception
402 return to a 32-bit task.
403 Please note that this does not necessarily enable the workaround,
404 as it depends on the alternative framework, which will only patch
405 the kernel if an affected CPU is detected.
409 config ARM64_ERRATUM_843419
410 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
413 select ARM64_MODULE_CMODEL_LARGE
415 This option builds kernel modules using the large memory model in
416 order to avoid the use of the ADRP instruction, which can cause
417 a subsequent memory access to use an incorrect address on Cortex-A53
420 Note that the kernel itself must be linked with a version of ld
421 which fixes potentially affected ADRP instructions through the
426 config CAVIUM_ERRATUM_22375
427 bool "Cavium erratum 22375, 24313"
430 Enable workaround for erratum 22375, 24313.
432 This implements two gicv3-its errata workarounds for ThunderX. Both
433 with small impact affecting only ITS table allocation.
435 erratum 22375: only alloc 8MB table size
436 erratum 24313: ignore memory access type
438 The fixes are in ITS initialization and basically ignore memory access
439 type and table size provided by the TYPER and BASER registers.
443 config CAVIUM_ERRATUM_23144
444 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
448 ITS SYNC command hang for cross node io and collections/cpu mapping.
452 config CAVIUM_ERRATUM_23154
453 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
456 The gicv3 of ThunderX requires a modified version for
457 reading the IAR status to ensure data synchronization
458 (access to icc_iar1_el1 is not sync'ed before and after).
462 config CAVIUM_ERRATUM_27456
463 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
466 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
467 instructions may cause the icache to become corrupted if it
468 contains data for a non-current ASID. The fix is to
469 invalidate the icache when changing the mm context.
478 default ARM64_4K_PAGES
480 Page size (translation granule) configuration.
482 config ARM64_4K_PAGES
485 This feature enables 4KB pages support.
487 config ARM64_16K_PAGES
490 The system will use 16KB pages support. AArch32 emulation
491 requires applications compiled with 16K (or a multiple of 16K)
494 config ARM64_64K_PAGES
497 This feature enables 64KB pages support (4KB by default)
498 allowing only two levels of page tables and faster TLB
499 look-up. AArch32 emulation requires applications compiled
500 with 64K aligned segments.
505 prompt "Virtual address space size"
506 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
507 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
508 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
510 Allows choosing one of multiple possible virtual address
511 space sizes. The level of translation table is determined by
512 a combination of page size and virtual address space size.
514 config ARM64_VA_BITS_36
515 bool "36-bit" if EXPERT
516 depends on ARM64_16K_PAGES
518 config ARM64_VA_BITS_39
520 depends on ARM64_4K_PAGES
522 config ARM64_VA_BITS_42
524 depends on ARM64_64K_PAGES
526 config ARM64_VA_BITS_47
528 depends on ARM64_16K_PAGES
530 config ARM64_VA_BITS_48
537 default 36 if ARM64_VA_BITS_36
538 default 39 if ARM64_VA_BITS_39
539 default 42 if ARM64_VA_BITS_42
540 default 47 if ARM64_VA_BITS_47
541 default 48 if ARM64_VA_BITS_48
543 config CPU_BIG_ENDIAN
544 bool "Build big-endian kernel"
546 Say Y if you plan on running a kernel in big-endian mode.
549 bool "Multi-core scheduler support"
551 Multi-core scheduler support improves the CPU scheduler's decision
552 making when dealing with multi-core CPU chips at a cost of slightly
553 increased overhead in some places. If unsure say N here.
556 bool "SMT scheduler support"
558 Improves the CPU scheduler's decision making when dealing with
559 MultiThreading at a cost of slightly increased overhead in some
560 places. If unsure say N here.
563 int "Maximum number of CPUs (2-4096)"
565 # These have to remain sorted largest to smallest
569 bool "Support for hot-pluggable CPUs"
570 select GENERIC_IRQ_MIGRATION
572 Say Y here to experiment with turning CPUs off and on. CPUs
573 can be controlled through /sys/devices/system/cpu.
575 # Common NUMA Features
577 bool "Numa Memory Allocation and Scheduler Support"
580 Enable NUMA (Non Uniform Memory Access) support.
582 The kernel will try to allocate memory used by a CPU on the
583 local memory of the CPU and add some more
584 NUMA awareness to the kernel.
587 int "Maximum NUMA Nodes (as a power of 2)"
590 depends on NEED_MULTIPLE_NODES
592 Specify the maximum number of NUMA Nodes available on the target
593 system. Increases memory reserved to accommodate various tables.
595 config USE_PERCPU_NUMA_NODE_ID
599 source kernel/Kconfig.preempt
600 source kernel/Kconfig.hz
602 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
603 depends on !HIBERNATION
606 config ARCH_HAS_HOLES_MEMORYMODEL
607 def_bool y if SPARSEMEM
609 config ARCH_SPARSEMEM_ENABLE
611 select SPARSEMEM_VMEMMAP_ENABLE
613 config ARCH_SPARSEMEM_DEFAULT
614 def_bool ARCH_SPARSEMEM_ENABLE
616 config ARCH_SELECT_MEMORY_MODEL
617 def_bool ARCH_SPARSEMEM_ENABLE
619 config HAVE_ARCH_PFN_VALID
620 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
622 config HW_PERF_EVENTS
626 config SYS_SUPPORTS_HUGETLBFS
629 config ARCH_WANT_HUGE_PMD_SHARE
630 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
632 config ARCH_HAS_CACHE_LINE_SIZE
638 bool "Enable seccomp to safely compute untrusted bytecode"
640 This kernel feature is useful for number crunching applications
641 that may need to compute untrusted bytecode during their
642 execution. By using pipes or other transports made available to
643 the process as file descriptors supporting the read/write
644 syscalls, it's possible to isolate those applications in
645 their own address space using seccomp. Once seccomp is
646 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
647 and the task is only allowed to execute a few safe syscalls
648 defined by each seccomp mode.
651 bool "Enable paravirtualization code"
653 This changes the kernel so it can modify itself when it is run
654 under a hypervisor, potentially improving performance significantly
655 over full virtualization.
657 config PARAVIRT_TIME_ACCOUNTING
658 bool "Paravirtual steal time accounting"
662 Select this option to enable fine granularity task steal time
663 accounting. Time spent executing other tasks in parallel with
664 the current vCPU is discounted from the vCPU power. To account for
665 that, there can be a small performance impact.
667 If in doubt, say N here.
674 bool "Xen guest support on ARM64"
675 depends on ARM64 && OF
679 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
681 config FORCE_MAX_ZONEORDER
683 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
684 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
687 The kernel memory allocator divides physically contiguous memory
688 blocks into "zones", where each zone is a power of two number of
689 pages. This option selects the largest power of two that the kernel
690 keeps in the memory allocator. If you need to allocate very large
691 blocks of physically contiguous memory, then you may need to
694 This config option is actually maximum order plus one. For example,
695 a value of 11 means that the largest free memory block is 2^10 pages.
697 We make sure that we can allocate upto a HugePage size for each configuration.
699 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
701 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
702 4M allocations matching the default size used by generic code.
704 menuconfig ARMV8_DEPRECATED
705 bool "Emulate deprecated/obsolete ARMv8 instructions"
708 Legacy software support may require certain instructions
709 that have been deprecated or obsoleted in the architecture.
711 Enable this config to enable selective emulation of these
719 bool "Emulate SWP/SWPB instructions"
721 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
722 they are always undefined. Say Y here to enable software
723 emulation of these instructions for userspace using LDXR/STXR.
725 In some older versions of glibc [<=2.8] SWP is used during futex
726 trylock() operations with the assumption that the code will not
727 be preempted. This invalid assumption may be more likely to fail
728 with SWP emulation enabled, leading to deadlock of the user
731 NOTE: when accessing uncached shared regions, LDXR/STXR rely
732 on an external transaction monitoring block called a global
733 monitor to maintain update atomicity. If your system does not
734 implement a global monitor, this option can cause programs that
735 perform SWP operations to uncached memory to deadlock.
739 config CP15_BARRIER_EMULATION
740 bool "Emulate CP15 Barrier instructions"
742 The CP15 barrier instructions - CP15ISB, CP15DSB, and
743 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
744 strongly recommended to use the ISB, DSB, and DMB
745 instructions instead.
747 Say Y here to enable software emulation of these
748 instructions for AArch32 userspace code. When this option is
749 enabled, CP15 barrier usage is traced which can help
750 identify software that needs updating.
754 config SETEND_EMULATION
755 bool "Emulate SETEND instruction"
757 The SETEND instruction alters the data-endianness of the
758 AArch32 EL0, and is deprecated in ARMv8.
760 Say Y here to enable software emulation of the instruction
761 for AArch32 userspace code.
763 Note: All the cpus on the system must have mixed endian support at EL0
764 for this feature to be enabled. If a new CPU - which doesn't support mixed
765 endian - is hotplugged in after this feature has been enabled, there could
766 be unexpected results in the applications.
771 menu "ARMv8.1 architectural features"
773 config ARM64_HW_AFDBM
774 bool "Support for hardware updates of the Access and Dirty page flags"
777 The ARMv8.1 architecture extensions introduce support for
778 hardware updates of the access and dirty information in page
779 table entries. When enabled in TCR_EL1 (HA and HD bits) on
780 capable processors, accesses to pages with PTE_AF cleared will
781 set this bit instead of raising an access flag fault.
782 Similarly, writes to read-only pages with the DBM bit set will
783 clear the read-only bit (AP[2]) instead of raising a
786 Kernels built with this configuration option enabled continue
787 to work on pre-ARMv8.1 hardware and the performance impact is
788 minimal. If unsure, say Y.
791 bool "Enable support for Privileged Access Never (PAN)"
794 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
795 prevents the kernel or hypervisor from accessing user-space (EL0)
798 Choosing this option will cause any unprotected (not using
799 copy_to_user et al) memory access to fail with a permission fault.
801 The feature is detected at runtime, and will remain as a 'nop'
802 instruction if the cpu does not implement the feature.
804 config ARM64_LSE_ATOMICS
805 bool "Atomic instructions"
807 As part of the Large System Extensions, ARMv8.1 introduces new
808 atomic instructions that are designed specifically to scale in
811 Say Y here to make use of these instructions for the in-kernel
812 atomic routines. This incurs a small overhead on CPUs that do
813 not support these instructions and requires the kernel to be
814 built with binutils >= 2.25.
817 bool "Enable support for Virtualization Host Extensions (VHE)"
820 Virtualization Host Extensions (VHE) allow the kernel to run
821 directly at EL2 (instead of EL1) on processors that support
822 it. This leads to better performance for KVM, as they reduce
823 the cost of the world switch.
825 Selecting this option allows the VHE feature to be detected
826 at runtime, and does not affect processors that do not
827 implement this feature.
831 menu "ARMv8.2 architectural features"
834 bool "Enable support for User Access Override (UAO)"
837 User Access Override (UAO; part of the ARMv8.2 Extensions)
838 causes the 'unprivileged' variant of the load/store instructions to
839 be overriden to be privileged.
841 This option changes get_user() and friends to use the 'unprivileged'
842 variant of the load/store instructions. This ensures that user-space
843 really did have access to the supplied memory. When addr_limit is
844 set to kernel memory the UAO bit will be set, allowing privileged
845 access to kernel memory.
847 Choosing this option will cause copy_to_user() et al to use user-space
850 The feature is detected at runtime, the kernel will use the
851 regular load/store instructions if the cpu does not implement the
856 config ARM64_MODULE_CMODEL_LARGE
859 config ARM64_MODULE_PLTS
861 select ARM64_MODULE_CMODEL_LARGE
862 select HAVE_MOD_ARCH_SPECIFIC
867 This builds the kernel as a Position Independent Executable (PIE),
868 which retains all relocation metadata required to relocate the
869 kernel binary at runtime to a different virtual address than the
870 address it was linked at.
871 Since AArch64 uses the RELA relocation format, this requires a
872 relocation pass at runtime even if the kernel is loaded at the
873 same address it was linked at.
875 config RANDOMIZE_BASE
876 bool "Randomize the address of the kernel image"
877 select ARM64_MODULE_PLTS
880 Randomizes the virtual address at which the kernel image is
881 loaded, as a security feature that deters exploit attempts
882 relying on knowledge of the location of kernel internals.
884 It is the bootloader's job to provide entropy, by passing a
885 random u64 value in /chosen/kaslr-seed at kernel entry.
887 When booting via the UEFI stub, it will invoke the firmware's
888 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
889 to the kernel proper. In addition, it will randomise the physical
890 location of the kernel Image as well.
894 config RANDOMIZE_MODULE_REGION_FULL
895 bool "Randomize the module region independently from the core kernel"
896 depends on RANDOMIZE_BASE
899 Randomizes the location of the module region without considering the
900 location of the core kernel. This way, it is impossible for modules
901 to leak information about the location of core kernel data structures
902 but it does imply that function calls between modules and the core
903 kernel will need to be resolved via veneers in the module PLT.
905 When this option is not set, the module region will be randomized over
906 a limited range that contains the [_stext, _etext] interval of the
907 core kernel, so branch relocations are always in range.
913 config ARM64_ACPI_PARKING_PROTOCOL
914 bool "Enable support for the ARM64 ACPI parking protocol"
917 Enable support for the ARM64 ACPI parking protocol. If disabled
918 the kernel will not allow booting through the ARM64 ACPI parking
919 protocol even if the corresponding data is present in the ACPI
923 string "Default kernel command string"
926 Provide a set of default command-line options at build time by
927 entering them here. As a minimum, you should specify the the
928 root device (e.g. root=/dev/nfs).
931 bool "Always use the default kernel command string"
933 Always use the default kernel command string, even if the boot
934 loader passes other arguments to the kernel.
935 This is useful if you cannot or don't want to change the
936 command-line options your boot loader passes to the kernel.
942 bool "UEFI runtime support"
943 depends on OF && !CPU_BIG_ENDIAN
946 select EFI_PARAMS_FROM_FDT
947 select EFI_RUNTIME_WRAPPERS
952 This option provides support for runtime services provided
953 by UEFI firmware (such as non-volatile variables, realtime
954 clock, and platform reset). A UEFI stub is also provided to
955 allow the kernel to be booted as an EFI application. This
956 is only useful on systems that have UEFI firmware.
959 bool "Enable support for SMBIOS (DMI) tables"
963 This enables SMBIOS/DMI feature for systems.
965 This option is only useful on systems that have UEFI firmware.
966 However, even with this option, the resultant kernel should
967 continue to boot on existing non-UEFI platforms.
971 menu "Userspace binary formats"
973 source "fs/Kconfig.binfmt"
976 bool "Kernel support for 32-bit EL0"
977 depends on ARM64_4K_PAGES || EXPERT
978 select COMPAT_BINFMT_ELF
980 select OLD_SIGSUSPEND3
981 select COMPAT_OLD_SIGACTION
983 This option enables support for a 32-bit EL0 running under a 64-bit
984 kernel at EL1. AArch32-specific components such as system calls,
985 the user helper functions, VFP support and the ptrace interface are
986 handled appropriately by the kernel.
988 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
989 that you will only be able to execute AArch32 binaries that were compiled
990 with page size aligned segments.
992 If you want to execute 32-bit userspace applications, say Y.
994 config SYSVIPC_COMPAT
996 depends on COMPAT && SYSVIPC
1000 menu "Power management options"
1002 source "kernel/power/Kconfig"
1004 config ARCH_HIBERNATION_POSSIBLE
1008 config ARCH_HIBERNATION_HEADER
1010 depends on HIBERNATION
1012 config ARCH_SUSPEND_POSSIBLE
1017 menu "CPU Power Management"
1019 source "drivers/cpuidle/Kconfig"
1021 source "drivers/cpufreq/Kconfig"
1025 source "net/Kconfig"
1027 source "drivers/Kconfig"
1029 source "drivers/firmware/Kconfig"
1031 source "drivers/acpi/Kconfig"
1035 source "arch/arm64/kvm/Kconfig"
1037 source "arch/arm64/Kconfig.debug"
1039 source "security/Kconfig"
1041 source "crypto/Kconfig"
1043 source "arch/arm64/crypto/Kconfig"
1046 source "lib/Kconfig"