3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
23 select BUILDTIME_EXTABLE_SORT
24 select CLONE_BACKWARDS
26 select CPU_PM if (SUSPEND || CPU_IDLE)
27 select DCACHE_WORD_ACCESS
28 select GENERIC_ALLOCATOR
29 select GENERIC_CLOCKEVENTS
30 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
31 select GENERIC_CPU_AUTOPROBE
32 select GENERIC_EARLY_IOREMAP
33 select GENERIC_IRQ_PROBE
34 select GENERIC_IRQ_SHOW
35 select GENERIC_IRQ_SHOW_LEVEL
36 select GENERIC_PCI_IOMAP
37 select GENERIC_SCHED_CLOCK
38 select GENERIC_SMP_IDLE_THREAD
39 select GENERIC_STRNCPY_FROM_USER
40 select GENERIC_STRNLEN_USER
41 select GENERIC_TIME_VSYSCALL
42 select HANDLE_DOMAIN_IRQ
43 select HARDIRQS_SW_RESEND
44 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
45 select HAVE_ARCH_AUDITSYSCALL
46 select HAVE_ARCH_BITREVERSE
47 select HAVE_ARCH_JUMP_LABEL
49 select HAVE_ARCH_SECCOMP_FILTER
50 select HAVE_ARCH_TRACEHOOK
52 select HAVE_C_RECORDMCOUNT
53 select HAVE_CC_STACKPROTECTOR
54 select HAVE_CMPXCHG_DOUBLE
55 select HAVE_DEBUG_BUGVERBOSE
56 select HAVE_DEBUG_KMEMLEAK
57 select HAVE_DMA_API_DEBUG
59 select HAVE_DMA_CONTIGUOUS
60 select HAVE_DYNAMIC_FTRACE
61 select HAVE_EFFICIENT_UNALIGNED_ACCESS
62 select HAVE_FTRACE_MCOUNT_RECORD
63 select HAVE_FUNCTION_TRACER
64 select HAVE_FUNCTION_GRAPH_TRACER
65 select HAVE_GENERIC_DMA_COHERENT
66 select HAVE_HW_BREAKPOINT if PERF_EVENTS
68 select HAVE_PATA_PLATFORM
69 select HAVE_PERF_EVENTS
71 select HAVE_PERF_USER_STACK_DUMP
72 select HAVE_RCU_TABLE_FREE
73 select HAVE_SYSCALL_TRACEPOINTS
75 select IRQ_FORCED_THREADING
76 select MODULES_USE_ELF_RELA
79 select OF_EARLY_FLATTREE
80 select OF_RESERVED_MEM
81 select PERF_USE_VMALLOC
86 select SYSCTL_EXCEPTION_TRACE
87 select HAVE_CONTEXT_TRACKING
89 ARM 64-bit (AArch64) Linux support.
94 config ARCH_PHYS_ADDR_T_64BIT
103 config STACKTRACE_SUPPORT
106 config LOCKDEP_SUPPORT
109 config TRACE_IRQFLAGS_SUPPORT
112 config RWSEM_XCHGADD_ALGORITHM
115 config GENERIC_HWEIGHT
121 config GENERIC_CALIBRATE_DELAY
127 config HAVE_GENERIC_RCU_GUP
130 config ARCH_DMA_ADDR_T_64BIT
133 config NEED_DMA_MAP_STATE
136 config NEED_SG_DMA_LENGTH
145 config KERNEL_MODE_NEON
148 config FIX_EARLYCON_MEM
151 config PGTABLE_LEVELS
153 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
154 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
155 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
156 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
158 source "init/Kconfig"
160 source "kernel/Kconfig.freezer"
162 menu "Platform selection"
167 This enables support for Samsung Exynos SoC family
170 bool "ARMv8 based Samsung Exynos7"
172 select COMMON_CLK_SAMSUNG
173 select HAVE_S3C2410_WATCHDOG if WATCHDOG
174 select HAVE_S3C_RTC if RTC_CLASS
176 select PINCTRL_EXYNOS
179 This enables support for Samsung Exynos7 SoC family
181 config ARCH_FSL_LS2085A
182 bool "Freescale LS2085A SOC"
184 This enables support for Freescale LS2085A SOC.
187 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
191 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
194 bool "Qualcomm Platforms"
197 This enables support for the ARMv8 based Qualcomm chipsets.
200 bool "AMD Seattle SoC Family"
202 This enables support for AMD Seattle SOC Family
205 bool "NVIDIA Tegra SoC Family"
206 select ARCH_HAS_RESET_CONTROLLER
207 select ARCH_REQUIRE_GPIOLIB
211 select GENERIC_CLOCKEVENTS
214 select RESET_CONTROLLER
216 This enables support for the NVIDIA Tegra SoC family.
218 config ARCH_TEGRA_132_SOC
219 bool "NVIDIA Tegra132 SoC"
220 depends on ARCH_TEGRA
221 select PINCTRL_TEGRA124
222 select USB_ULPI if USB_PHY
223 select USB_ULPI_VIEWPORT if USB_PHY
225 Enable support for NVIDIA Tegra132 SoC, based on the Denver
226 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
227 but contains an NVIDIA Denver CPU complex in place of
228 Tegra124's "4+1" Cortex-A15 CPU complex.
231 bool "Spreadtrum SoC platform"
233 Support for Spreadtrum ARM based SoCs
236 bool "Cavium Inc. Thunder SoC Family"
238 This enables support for Cavium's Thunder Family of SoCs.
241 bool "ARMv8 software model (Versatile Express)"
242 select ARCH_REQUIRE_GPIOLIB
243 select COMMON_CLK_VERSATILE
244 select POWER_RESET_VEXPRESS
245 select VEXPRESS_CONFIG
247 This enables support for the ARMv8 software model (Versatile
251 bool "AppliedMicro X-Gene SOC Family"
253 This enables support for AppliedMicro X-Gene SOC Family
256 bool "Xilinx ZynqMP Family"
258 This enables support for Xilinx ZynqMP Family
267 This feature enables support for PCI bus system. If you say Y
268 here, the kernel will include drivers and infrastructure code
269 to support PCI bus devices.
274 config PCI_DOMAINS_GENERIC
280 source "drivers/pci/Kconfig"
281 source "drivers/pci/pcie/Kconfig"
282 source "drivers/pci/hotplug/Kconfig"
286 menu "Kernel Features"
288 menu "ARM errata workarounds via the alternatives framework"
290 config ARM64_ERRATUM_826319
291 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
294 This option adds an alternative code sequence to work around ARM
295 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
296 AXI master interface and an L2 cache.
298 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
299 and is unable to accept a certain write via this interface, it will
300 not progress on read data presented on the read data channel and the
303 The workaround promotes data cache clean instructions to
304 data cache clean-and-invalidate.
305 Please note that this does not necessarily enable the workaround,
306 as it depends on the alternative framework, which will only patch
307 the kernel if an affected CPU is detected.
311 config ARM64_ERRATUM_827319
312 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
315 This option adds an alternative code sequence to work around ARM
316 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
317 master interface and an L2 cache.
319 Under certain conditions this erratum can cause a clean line eviction
320 to occur at the same time as another transaction to the same address
321 on the AMBA 5 CHI interface, which can cause data corruption if the
322 interconnect reorders the two transactions.
324 The workaround promotes data cache clean instructions to
325 data cache clean-and-invalidate.
326 Please note that this does not necessarily enable the workaround,
327 as it depends on the alternative framework, which will only patch
328 the kernel if an affected CPU is detected.
332 config ARM64_ERRATUM_824069
333 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
336 This option adds an alternative code sequence to work around ARM
337 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
338 to a coherent interconnect.
340 If a Cortex-A53 processor is executing a store or prefetch for
341 write instruction at the same time as a processor in another
342 cluster is executing a cache maintenance operation to the same
343 address, then this erratum might cause a clean cache line to be
344 incorrectly marked as dirty.
346 The workaround promotes data cache clean instructions to
347 data cache clean-and-invalidate.
348 Please note that this option does not necessarily enable the
349 workaround, as it depends on the alternative framework, which will
350 only patch the kernel if an affected CPU is detected.
354 config ARM64_ERRATUM_819472
355 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
358 This option adds an alternative code sequence to work around ARM
359 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
360 present when it is connected to a coherent interconnect.
362 If the processor is executing a load and store exclusive sequence at
363 the same time as a processor in another cluster is executing a cache
364 maintenance operation to the same address, then this erratum might
365 cause data corruption.
367 The workaround promotes data cache clean instructions to
368 data cache clean-and-invalidate.
369 Please note that this does not necessarily enable the workaround,
370 as it depends on the alternative framework, which will only patch
371 the kernel if an affected CPU is detected.
375 config ARM64_ERRATUM_832075
376 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
379 This option adds an alternative code sequence to work around ARM
380 erratum 832075 on Cortex-A57 parts up to r1p2.
382 Affected Cortex-A57 parts might deadlock when exclusive load/store
383 instructions to Write-Back memory are mixed with Device loads.
385 The workaround is to promote device loads to use Load-Acquire
387 Please note that this does not necessarily enable the workaround,
388 as it depends on the alternative framework, which will only patch
389 the kernel if an affected CPU is detected.
393 config ARM64_ERRATUM_845719
394 bool "Cortex-A53: 845719: a load might read incorrect data"
398 This option adds an alternative code sequence to work around ARM
399 erratum 845719 on Cortex-A53 parts up to r0p4.
401 When running a compat (AArch32) userspace on an affected Cortex-A53
402 part, a load at EL0 from a virtual address that matches the bottom 32
403 bits of the virtual address used by a recent load at (AArch64) EL1
404 might return incorrect data.
406 The workaround is to write the contextidr_el1 register on exception
407 return to a 32-bit task.
408 Please note that this does not necessarily enable the workaround,
409 as it depends on the alternative framework, which will only patch
410 the kernel if an affected CPU is detected.
419 default ARM64_4K_PAGES
421 Page size (translation granule) configuration.
423 config ARM64_4K_PAGES
426 This feature enables 4KB pages support.
428 config ARM64_64K_PAGES
431 This feature enables 64KB pages support (4KB by default)
432 allowing only two levels of page tables and faster TLB
433 look-up. AArch32 emulation is not available when this feature
439 prompt "Virtual address space size"
440 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
441 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
443 Allows choosing one of multiple possible virtual address
444 space sizes. The level of translation table is determined by
445 a combination of page size and virtual address space size.
447 config ARM64_VA_BITS_39
449 depends on ARM64_4K_PAGES
451 config ARM64_VA_BITS_42
453 depends on ARM64_64K_PAGES
455 config ARM64_VA_BITS_48
462 default 39 if ARM64_VA_BITS_39
463 default 42 if ARM64_VA_BITS_42
464 default 48 if ARM64_VA_BITS_48
466 config CPU_BIG_ENDIAN
467 bool "Build big-endian kernel"
469 Say Y if you plan on running a kernel in big-endian mode.
472 bool "Symmetric Multi-Processing"
474 This enables support for systems with more than one CPU. If
475 you say N here, the kernel will run on single and
476 multiprocessor machines, but will use only one CPU of a
477 multiprocessor machine. If you say Y here, the kernel will run
478 on many, but not all, single processor machines. On a single
479 processor machine, the kernel will run faster if you say N
482 If you don't know what to do here, say N.
485 bool "Multi-core scheduler support"
488 Multi-core scheduler support improves the CPU scheduler's decision
489 making when dealing with multi-core CPU chips at a cost of slightly
490 increased overhead in some places. If unsure say N here.
493 bool "SMT scheduler support"
496 Improves the CPU scheduler's decision making when dealing with
497 MultiThreading at a cost of slightly increased overhead in some
498 places. If unsure say N here.
501 int "Maximum number of CPUs (2-4096)"
504 # These have to remain sorted largest to smallest
508 bool "Support for hot-pluggable CPUs"
511 Say Y here to experiment with turning CPUs off and on. CPUs
512 can be controlled through /sys/devices/system/cpu.
514 source kernel/Kconfig.preempt
524 config ARCH_HAS_HOLES_MEMORYMODEL
525 def_bool y if SPARSEMEM
527 config ARCH_SPARSEMEM_ENABLE
529 select SPARSEMEM_VMEMMAP_ENABLE
531 config ARCH_SPARSEMEM_DEFAULT
532 def_bool ARCH_SPARSEMEM_ENABLE
534 config ARCH_SELECT_MEMORY_MODEL
535 def_bool ARCH_SPARSEMEM_ENABLE
537 config HAVE_ARCH_PFN_VALID
538 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
540 config HW_PERF_EVENTS
541 bool "Enable hardware performance counter support for perf events"
542 depends on PERF_EVENTS
545 Enable hardware performance counter support for perf events. If
546 disabled, perf events will use software events only.
548 config SYS_SUPPORTS_HUGETLBFS
551 config ARCH_WANT_GENERAL_HUGETLB
554 config ARCH_WANT_HUGE_PMD_SHARE
555 def_bool y if !ARM64_64K_PAGES
557 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
560 config ARCH_HAS_CACHE_LINE_SIZE
566 bool "Enable seccomp to safely compute untrusted bytecode"
568 This kernel feature is useful for number crunching applications
569 that may need to compute untrusted bytecode during their
570 execution. By using pipes or other transports made available to
571 the process as file descriptors supporting the read/write
572 syscalls, it's possible to isolate those applications in
573 their own address space using seccomp. Once seccomp is
574 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
575 and the task is only allowed to execute a few safe syscalls
576 defined by each seccomp mode.
583 bool "Xen guest support on ARM64"
584 depends on ARM64 && OF
587 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
589 config FORCE_MAX_ZONEORDER
591 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
594 menuconfig ARMV8_DEPRECATED
595 bool "Emulate deprecated/obsolete ARMv8 instructions"
598 Legacy software support may require certain instructions
599 that have been deprecated or obsoleted in the architecture.
601 Enable this config to enable selective emulation of these
609 bool "Emulate SWP/SWPB instructions"
611 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
612 they are always undefined. Say Y here to enable software
613 emulation of these instructions for userspace using LDXR/STXR.
615 In some older versions of glibc [<=2.8] SWP is used during futex
616 trylock() operations with the assumption that the code will not
617 be preempted. This invalid assumption may be more likely to fail
618 with SWP emulation enabled, leading to deadlock of the user
621 NOTE: when accessing uncached shared regions, LDXR/STXR rely
622 on an external transaction monitoring block called a global
623 monitor to maintain update atomicity. If your system does not
624 implement a global monitor, this option can cause programs that
625 perform SWP operations to uncached memory to deadlock.
629 config CP15_BARRIER_EMULATION
630 bool "Emulate CP15 Barrier instructions"
632 The CP15 barrier instructions - CP15ISB, CP15DSB, and
633 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
634 strongly recommended to use the ISB, DSB, and DMB
635 instructions instead.
637 Say Y here to enable software emulation of these
638 instructions for AArch32 userspace code. When this option is
639 enabled, CP15 barrier usage is traced which can help
640 identify software that needs updating.
644 config SETEND_EMULATION
645 bool "Emulate SETEND instruction"
647 The SETEND instruction alters the data-endianness of the
648 AArch32 EL0, and is deprecated in ARMv8.
650 Say Y here to enable software emulation of the instruction
651 for AArch32 userspace code.
653 Note: All the cpus on the system must have mixed endian support at EL0
654 for this feature to be enabled. If a new CPU - which doesn't support mixed
655 endian - is hotplugged in after this feature has been enabled, there could
656 be unexpected results in the applications.
666 string "Default kernel command string"
669 Provide a set of default command-line options at build time by
670 entering them here. As a minimum, you should specify the the
671 root device (e.g. root=/dev/nfs).
674 bool "Always use the default kernel command string"
676 Always use the default kernel command string, even if the boot
677 loader passes other arguments to the kernel.
678 This is useful if you cannot or don't want to change the
679 command-line options your boot loader passes to the kernel.
685 bool "UEFI runtime support"
686 depends on OF && !CPU_BIG_ENDIAN
689 select EFI_PARAMS_FROM_FDT
690 select EFI_RUNTIME_WRAPPERS
695 This option provides support for runtime services provided
696 by UEFI firmware (such as non-volatile variables, realtime
697 clock, and platform reset). A UEFI stub is also provided to
698 allow the kernel to be booted as an EFI application. This
699 is only useful on systems that have UEFI firmware.
702 bool "Enable support for SMBIOS (DMI) tables"
706 This enables SMBIOS/DMI feature for systems.
708 This option is only useful on systems that have UEFI firmware.
709 However, even with this option, the resultant kernel should
710 continue to boot on existing non-UEFI platforms.
714 menu "Userspace binary formats"
716 source "fs/Kconfig.binfmt"
719 bool "Kernel support for 32-bit EL0"
720 depends on !ARM64_64K_PAGES || EXPERT
721 select COMPAT_BINFMT_ELF
723 select OLD_SIGSUSPEND3
724 select COMPAT_OLD_SIGACTION
726 This option enables support for a 32-bit EL0 running under a 64-bit
727 kernel at EL1. AArch32-specific components such as system calls,
728 the user helper functions, VFP support and the ptrace interface are
729 handled appropriately by the kernel.
731 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
732 will only be able to execute AArch32 binaries that were compiled with
733 64k aligned segments.
735 If you want to execute 32-bit userspace applications, say Y.
737 config SYSVIPC_COMPAT
739 depends on COMPAT && SYSVIPC
743 menu "Power management options"
745 source "kernel/power/Kconfig"
747 config ARCH_SUSPEND_POSSIBLE
752 menu "CPU Power Management"
754 source "drivers/cpuidle/Kconfig"
756 source "drivers/cpufreq/Kconfig"
762 source "drivers/Kconfig"
764 source "drivers/firmware/Kconfig"
766 source "drivers/acpi/Kconfig"
770 source "arch/arm64/kvm/Kconfig"
772 source "arch/arm64/Kconfig.debug"
774 source "security/Kconfig"
776 source "crypto/Kconfig"
778 source "arch/arm64/crypto/Kconfig"