3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
30 select GENERIC_ALLOCATOR
31 select GENERIC_CLOCKEVENTS
32 select GENERIC_CLOCKEVENTS_BROADCAST
33 select GENERIC_CPU_AUTOPROBE
34 select GENERIC_EARLY_IOREMAP
35 select GENERIC_IDLE_POLL_SETUP
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select GENERIC_IRQ_SHOW_LEVEL
39 select GENERIC_PCI_IOMAP
40 select GENERIC_SCHED_CLOCK
41 select GENERIC_SMP_IDLE_THREAD
42 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
44 select GENERIC_TIME_VSYSCALL
45 select HANDLE_DOMAIN_IRQ
46 select HARDIRQS_SW_RESEND
47 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
48 select HAVE_ARCH_AUDITSYSCALL
49 select HAVE_ARCH_BITREVERSE
50 select HAVE_ARCH_JUMP_LABEL
51 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP
53 select HAVE_ARCH_SECCOMP_FILTER
54 select HAVE_ARCH_TRACEHOOK
56 select HAVE_C_RECORDMCOUNT
57 select HAVE_CC_STACKPROTECTOR
58 select HAVE_CMPXCHG_DOUBLE
59 select HAVE_CMPXCHG_LOCAL
60 select HAVE_DEBUG_BUGVERBOSE
61 select HAVE_DEBUG_KMEMLEAK
62 select HAVE_DMA_API_DEBUG
64 select HAVE_DMA_CONTIGUOUS
65 select HAVE_DYNAMIC_FTRACE
66 select HAVE_EFFICIENT_UNALIGNED_ACCESS
67 select HAVE_FTRACE_MCOUNT_RECORD
68 select HAVE_FUNCTION_TRACER
69 select HAVE_FUNCTION_GRAPH_TRACER
70 select HAVE_GENERIC_DMA_COHERENT
71 select HAVE_HW_BREAKPOINT if PERF_EVENTS
73 select HAVE_PATA_PLATFORM
74 select HAVE_PERF_EVENTS
76 select HAVE_PERF_USER_STACK_DUMP
77 select HAVE_RCU_TABLE_FREE
78 select HAVE_SYSCALL_TRACEPOINTS
79 select IOMMU_DMA if IOMMU_SUPPORT
81 select IRQ_FORCED_THREADING
82 select MODULES_USE_ELF_RELA
85 select OF_EARLY_FLATTREE
86 select OF_RESERVED_MEM
87 select PERF_USE_VMALLOC
92 select SYSCTL_EXCEPTION_TRACE
93 select HAVE_CONTEXT_TRACKING
95 ARM 64-bit (AArch64) Linux support.
100 config ARCH_PHYS_ADDR_T_64BIT
109 config STACKTRACE_SUPPORT
112 config ILLEGAL_POINTER_VALUE
114 default 0xdead000000000000
116 config LOCKDEP_SUPPORT
119 config TRACE_IRQFLAGS_SUPPORT
122 config RWSEM_XCHGADD_ALGORITHM
129 config GENERIC_BUG_RELATIVE_POINTERS
131 depends on GENERIC_BUG
133 config GENERIC_HWEIGHT
139 config GENERIC_CALIBRATE_DELAY
145 config HAVE_GENERIC_RCU_GUP
148 config ARCH_DMA_ADDR_T_64BIT
151 config NEED_DMA_MAP_STATE
154 config NEED_SG_DMA_LENGTH
166 config KERNEL_MODE_NEON
169 config FIX_EARLYCON_MEM
172 config PGTABLE_LEVELS
174 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
175 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
176 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
177 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
178 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
179 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
181 source "init/Kconfig"
183 source "kernel/Kconfig.freezer"
185 source "arch/arm64/Kconfig.platforms"
192 This feature enables support for PCI bus system. If you say Y
193 here, the kernel will include drivers and infrastructure code
194 to support PCI bus devices.
199 config PCI_DOMAINS_GENERIC
205 source "drivers/pci/Kconfig"
206 source "drivers/pci/pcie/Kconfig"
207 source "drivers/pci/hotplug/Kconfig"
211 menu "Kernel Features"
213 menu "ARM errata workarounds via the alternatives framework"
215 config ARM64_ERRATUM_826319
216 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
219 This option adds an alternative code sequence to work around ARM
220 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
221 AXI master interface and an L2 cache.
223 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
224 and is unable to accept a certain write via this interface, it will
225 not progress on read data presented on the read data channel and the
228 The workaround promotes data cache clean instructions to
229 data cache clean-and-invalidate.
230 Please note that this does not necessarily enable the workaround,
231 as it depends on the alternative framework, which will only patch
232 the kernel if an affected CPU is detected.
236 config ARM64_ERRATUM_827319
237 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
240 This option adds an alternative code sequence to work around ARM
241 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
242 master interface and an L2 cache.
244 Under certain conditions this erratum can cause a clean line eviction
245 to occur at the same time as another transaction to the same address
246 on the AMBA 5 CHI interface, which can cause data corruption if the
247 interconnect reorders the two transactions.
249 The workaround promotes data cache clean instructions to
250 data cache clean-and-invalidate.
251 Please note that this does not necessarily enable the workaround,
252 as it depends on the alternative framework, which will only patch
253 the kernel if an affected CPU is detected.
257 config ARM64_ERRATUM_824069
258 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
261 This option adds an alternative code sequence to work around ARM
262 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
263 to a coherent interconnect.
265 If a Cortex-A53 processor is executing a store or prefetch for
266 write instruction at the same time as a processor in another
267 cluster is executing a cache maintenance operation to the same
268 address, then this erratum might cause a clean cache line to be
269 incorrectly marked as dirty.
271 The workaround promotes data cache clean instructions to
272 data cache clean-and-invalidate.
273 Please note that this option does not necessarily enable the
274 workaround, as it depends on the alternative framework, which will
275 only patch the kernel if an affected CPU is detected.
279 config ARM64_ERRATUM_819472
280 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
283 This option adds an alternative code sequence to work around ARM
284 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
285 present when it is connected to a coherent interconnect.
287 If the processor is executing a load and store exclusive sequence at
288 the same time as a processor in another cluster is executing a cache
289 maintenance operation to the same address, then this erratum might
290 cause data corruption.
292 The workaround promotes data cache clean instructions to
293 data cache clean-and-invalidate.
294 Please note that this does not necessarily enable the workaround,
295 as it depends on the alternative framework, which will only patch
296 the kernel if an affected CPU is detected.
300 config ARM64_ERRATUM_832075
301 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
304 This option adds an alternative code sequence to work around ARM
305 erratum 832075 on Cortex-A57 parts up to r1p2.
307 Affected Cortex-A57 parts might deadlock when exclusive load/store
308 instructions to Write-Back memory are mixed with Device loads.
310 The workaround is to promote device loads to use Load-Acquire
312 Please note that this does not necessarily enable the workaround,
313 as it depends on the alternative framework, which will only patch
314 the kernel if an affected CPU is detected.
318 config ARM64_ERRATUM_845719
319 bool "Cortex-A53: 845719: a load might read incorrect data"
323 This option adds an alternative code sequence to work around ARM
324 erratum 845719 on Cortex-A53 parts up to r0p4.
326 When running a compat (AArch32) userspace on an affected Cortex-A53
327 part, a load at EL0 from a virtual address that matches the bottom 32
328 bits of the virtual address used by a recent load at (AArch64) EL1
329 might return incorrect data.
331 The workaround is to write the contextidr_el1 register on exception
332 return to a 32-bit task.
333 Please note that this does not necessarily enable the workaround,
334 as it depends on the alternative framework, which will only patch
335 the kernel if an affected CPU is detected.
339 config ARM64_ERRATUM_843419
340 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
344 This option builds kernel modules using the large memory model in
345 order to avoid the use of the ADRP instruction, which can cause
346 a subsequent memory access to use an incorrect address on Cortex-A53
349 Note that the kernel itself must be linked with a version of ld
350 which fixes potentially affected ADRP instructions through the
355 config CAVIUM_ERRATUM_22375
356 bool "Cavium erratum 22375, 24313"
359 Enable workaround for erratum 22375, 24313.
361 This implements two gicv3-its errata workarounds for ThunderX. Both
362 with small impact affecting only ITS table allocation.
364 erratum 22375: only alloc 8MB table size
365 erratum 24313: ignore memory access type
367 The fixes are in ITS initialization and basically ignore memory access
368 type and table size provided by the TYPER and BASER registers.
372 config CAVIUM_ERRATUM_23154
373 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
376 The gicv3 of ThunderX requires a modified version for
377 reading the IAR status to ensure data synchronization
378 (access to icc_iar1_el1 is not sync'ed before and after).
387 default ARM64_4K_PAGES
389 Page size (translation granule) configuration.
391 config ARM64_4K_PAGES
394 This feature enables 4KB pages support.
396 config ARM64_16K_PAGES
399 The system will use 16KB pages support. AArch32 emulation
400 requires applications compiled with 16K (or a multiple of 16K)
403 config ARM64_64K_PAGES
406 This feature enables 64KB pages support (4KB by default)
407 allowing only two levels of page tables and faster TLB
408 look-up. AArch32 emulation requires applications compiled
409 with 64K aligned segments.
414 prompt "Virtual address space size"
415 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
416 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
417 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
419 Allows choosing one of multiple possible virtual address
420 space sizes. The level of translation table is determined by
421 a combination of page size and virtual address space size.
423 config ARM64_VA_BITS_36
424 bool "36-bit" if EXPERT
425 depends on ARM64_16K_PAGES
427 config ARM64_VA_BITS_39
429 depends on ARM64_4K_PAGES
431 config ARM64_VA_BITS_42
433 depends on ARM64_64K_PAGES
435 config ARM64_VA_BITS_47
437 depends on ARM64_16K_PAGES
439 config ARM64_VA_BITS_48
446 default 36 if ARM64_VA_BITS_36
447 default 39 if ARM64_VA_BITS_39
448 default 42 if ARM64_VA_BITS_42
449 default 47 if ARM64_VA_BITS_47
450 default 48 if ARM64_VA_BITS_48
452 config CPU_BIG_ENDIAN
453 bool "Build big-endian kernel"
455 Say Y if you plan on running a kernel in big-endian mode.
458 bool "Multi-core scheduler support"
460 Multi-core scheduler support improves the CPU scheduler's decision
461 making when dealing with multi-core CPU chips at a cost of slightly
462 increased overhead in some places. If unsure say N here.
465 bool "SMT scheduler support"
467 Improves the CPU scheduler's decision making when dealing with
468 MultiThreading at a cost of slightly increased overhead in some
469 places. If unsure say N here.
472 int "Maximum number of CPUs (2-4096)"
474 # These have to remain sorted largest to smallest
478 bool "Support for hot-pluggable CPUs"
479 select GENERIC_IRQ_MIGRATION
481 Say Y here to experiment with turning CPUs off and on. CPUs
482 can be controlled through /sys/devices/system/cpu.
484 source kernel/Kconfig.preempt
485 source kernel/Kconfig.hz
487 config ARCH_HAS_HOLES_MEMORYMODEL
488 def_bool y if SPARSEMEM
490 config ARCH_SPARSEMEM_ENABLE
492 select SPARSEMEM_VMEMMAP_ENABLE
494 config ARCH_SPARSEMEM_DEFAULT
495 def_bool ARCH_SPARSEMEM_ENABLE
497 config ARCH_SELECT_MEMORY_MODEL
498 def_bool ARCH_SPARSEMEM_ENABLE
500 config HAVE_ARCH_PFN_VALID
501 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
503 config HW_PERF_EVENTS
507 config SYS_SUPPORTS_HUGETLBFS
510 config ARCH_WANT_GENERAL_HUGETLB
513 config ARCH_WANT_HUGE_PMD_SHARE
514 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
516 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
519 config ARCH_HAS_CACHE_LINE_SIZE
525 bool "Enable seccomp to safely compute untrusted bytecode"
527 This kernel feature is useful for number crunching applications
528 that may need to compute untrusted bytecode during their
529 execution. By using pipes or other transports made available to
530 the process as file descriptors supporting the read/write
531 syscalls, it's possible to isolate those applications in
532 their own address space using seccomp. Once seccomp is
533 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
534 and the task is only allowed to execute a few safe syscalls
535 defined by each seccomp mode.
542 bool "Xen guest support on ARM64"
543 depends on ARM64 && OF
546 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
548 config FORCE_MAX_ZONEORDER
550 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
551 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
554 The kernel memory allocator divides physically contiguous memory
555 blocks into "zones", where each zone is a power of two number of
556 pages. This option selects the largest power of two that the kernel
557 keeps in the memory allocator. If you need to allocate very large
558 blocks of physically contiguous memory, then you may need to
561 This config option is actually maximum order plus one. For example,
562 a value of 11 means that the largest free memory block is 2^10 pages.
564 We make sure that we can allocate upto a HugePage size for each configuration.
566 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
568 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
569 4M allocations matching the default size used by generic code.
571 menuconfig ARMV8_DEPRECATED
572 bool "Emulate deprecated/obsolete ARMv8 instructions"
575 Legacy software support may require certain instructions
576 that have been deprecated or obsoleted in the architecture.
578 Enable this config to enable selective emulation of these
586 bool "Emulate SWP/SWPB instructions"
588 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
589 they are always undefined. Say Y here to enable software
590 emulation of these instructions for userspace using LDXR/STXR.
592 In some older versions of glibc [<=2.8] SWP is used during futex
593 trylock() operations with the assumption that the code will not
594 be preempted. This invalid assumption may be more likely to fail
595 with SWP emulation enabled, leading to deadlock of the user
598 NOTE: when accessing uncached shared regions, LDXR/STXR rely
599 on an external transaction monitoring block called a global
600 monitor to maintain update atomicity. If your system does not
601 implement a global monitor, this option can cause programs that
602 perform SWP operations to uncached memory to deadlock.
606 config CP15_BARRIER_EMULATION
607 bool "Emulate CP15 Barrier instructions"
609 The CP15 barrier instructions - CP15ISB, CP15DSB, and
610 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
611 strongly recommended to use the ISB, DSB, and DMB
612 instructions instead.
614 Say Y here to enable software emulation of these
615 instructions for AArch32 userspace code. When this option is
616 enabled, CP15 barrier usage is traced which can help
617 identify software that needs updating.
621 config SETEND_EMULATION
622 bool "Emulate SETEND instruction"
624 The SETEND instruction alters the data-endianness of the
625 AArch32 EL0, and is deprecated in ARMv8.
627 Say Y here to enable software emulation of the instruction
628 for AArch32 userspace code.
630 Note: All the cpus on the system must have mixed endian support at EL0
631 for this feature to be enabled. If a new CPU - which doesn't support mixed
632 endian - is hotplugged in after this feature has been enabled, there could
633 be unexpected results in the applications.
638 menu "ARMv8.1 architectural features"
640 config ARM64_HW_AFDBM
641 bool "Support for hardware updates of the Access and Dirty page flags"
644 The ARMv8.1 architecture extensions introduce support for
645 hardware updates of the access and dirty information in page
646 table entries. When enabled in TCR_EL1 (HA and HD bits) on
647 capable processors, accesses to pages with PTE_AF cleared will
648 set this bit instead of raising an access flag fault.
649 Similarly, writes to read-only pages with the DBM bit set will
650 clear the read-only bit (AP[2]) instead of raising a
653 Kernels built with this configuration option enabled continue
654 to work on pre-ARMv8.1 hardware and the performance impact is
655 minimal. If unsure, say Y.
658 bool "Enable support for Privileged Access Never (PAN)"
661 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
662 prevents the kernel or hypervisor from accessing user-space (EL0)
665 Choosing this option will cause any unprotected (not using
666 copy_to_user et al) memory access to fail with a permission fault.
668 The feature is detected at runtime, and will remain as a 'nop'
669 instruction if the cpu does not implement the feature.
671 config ARM64_LSE_ATOMICS
672 bool "Atomic instructions"
674 As part of the Large System Extensions, ARMv8.1 introduces new
675 atomic instructions that are designed specifically to scale in
678 Say Y here to make use of these instructions for the in-kernel
679 atomic routines. This incurs a small overhead on CPUs that do
680 not support these instructions and requires the kernel to be
681 built with binutils >= 2.25.
690 string "Default kernel command string"
693 Provide a set of default command-line options at build time by
694 entering them here. As a minimum, you should specify the the
695 root device (e.g. root=/dev/nfs).
698 bool "Always use the default kernel command string"
700 Always use the default kernel command string, even if the boot
701 loader passes other arguments to the kernel.
702 This is useful if you cannot or don't want to change the
703 command-line options your boot loader passes to the kernel.
709 bool "UEFI runtime support"
710 depends on OF && !CPU_BIG_ENDIAN
713 select EFI_PARAMS_FROM_FDT
714 select EFI_RUNTIME_WRAPPERS
719 This option provides support for runtime services provided
720 by UEFI firmware (such as non-volatile variables, realtime
721 clock, and platform reset). A UEFI stub is also provided to
722 allow the kernel to be booted as an EFI application. This
723 is only useful on systems that have UEFI firmware.
726 bool "Enable support for SMBIOS (DMI) tables"
730 This enables SMBIOS/DMI feature for systems.
732 This option is only useful on systems that have UEFI firmware.
733 However, even with this option, the resultant kernel should
734 continue to boot on existing non-UEFI platforms.
738 menu "Userspace binary formats"
740 source "fs/Kconfig.binfmt"
743 bool "Kernel support for 32-bit EL0"
744 depends on ARM64_4K_PAGES || EXPERT
745 select COMPAT_BINFMT_ELF
747 select OLD_SIGSUSPEND3
748 select COMPAT_OLD_SIGACTION
750 This option enables support for a 32-bit EL0 running under a 64-bit
751 kernel at EL1. AArch32-specific components such as system calls,
752 the user helper functions, VFP support and the ptrace interface are
753 handled appropriately by the kernel.
755 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
756 that you will only be able to execute AArch32 binaries that were compiled
757 with page size aligned segments.
759 If you want to execute 32-bit userspace applications, say Y.
761 config SYSVIPC_COMPAT
763 depends on COMPAT && SYSVIPC
767 menu "Power management options"
769 source "kernel/power/Kconfig"
771 config ARCH_SUSPEND_POSSIBLE
776 menu "CPU Power Management"
778 source "drivers/cpuidle/Kconfig"
780 source "drivers/cpufreq/Kconfig"
786 source "drivers/Kconfig"
788 source "drivers/firmware/Kconfig"
790 source "drivers/acpi/Kconfig"
794 source "arch/arm64/kvm/Kconfig"
796 source "arch/arm64/Kconfig.debug"
798 source "security/Kconfig"
800 source "crypto/Kconfig"
802 source "arch/arm64/crypto/Kconfig"