arch/arm64/boot/dts/apm/apm-storm.dtsi

   1 /*
   2  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   3  *
   4  * Copyright (C) 2013, Applied Micro Circuits Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 / {
  13         compatible = "apm,xgene-storm";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu@000 {
  23                         device_type = "cpu";
  24                         compatible = "apm,potenza", "arm,armv8";
  25                         reg = <0x0 0x000>;
  26                         enable-method = "spin-table";
  27                         cpu-release-addr = <0x1 0x0000fff8>;
  28                 };
  29                 cpu@001 {
  30                         device_type = "cpu";
  31                         compatible = "apm,potenza", "arm,armv8";
  32                         reg = <0x0 0x001>;
  33                         enable-method = "spin-table";
  34                         cpu-release-addr = <0x1 0x0000fff8>;
  35                 };
  36                 cpu@100 {
  37                         device_type = "cpu";
  38                         compatible = "apm,potenza", "arm,armv8";
  39                         reg = <0x0 0x100>;
  40                         enable-method = "spin-table";
  41                         cpu-release-addr = <0x1 0x0000fff8>;
  42                 };
  43                 cpu@101 {
  44                         device_type = "cpu";
  45                         compatible = "apm,potenza", "arm,armv8";
  46                         reg = <0x0 0x101>;
  47                         enable-method = "spin-table";
  48                         cpu-release-addr = <0x1 0x0000fff8>;
  49                 };
  50                 cpu@200 {
  51                         device_type = "cpu";
  52                         compatible = "apm,potenza", "arm,armv8";
  53                         reg = <0x0 0x200>;
  54                         enable-method = "spin-table";
  55                         cpu-release-addr = <0x1 0x0000fff8>;
  56                 };
  57                 cpu@201 {
  58                         device_type = "cpu";
  59                         compatible = "apm,potenza", "arm,armv8";
  60                         reg = <0x0 0x201>;
  61                         enable-method = "spin-table";
  62                         cpu-release-addr = <0x1 0x0000fff8>;
  63                 };
  64                 cpu@300 {
  65                         device_type = "cpu";
  66                         compatible = "apm,potenza", "arm,armv8";
  67                         reg = <0x0 0x300>;
  68                         enable-method = "spin-table";
  69                         cpu-release-addr = <0x1 0x0000fff8>;
  70                 };
  71                 cpu@301 {
  72                         device_type = "cpu";
  73                         compatible = "apm,potenza", "arm,armv8";
  74                         reg = <0x0 0x301>;
  75                         enable-method = "spin-table";
  76                         cpu-release-addr = <0x1 0x0000fff8>;
  77                 };
  78         };
  79
  80         gic: interrupt-controller@78010000 {
  81                 compatible = "arm,cortex-a15-gic";
  82                 #interrupt-cells = <3>;
  83                 interrupt-controller;
  84                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
  85                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
  86                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
  87                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
  88                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
  89         };
  90
  91         timer {
  92                 compatible = "arm,armv8-timer";
  93                 interrupts = <1 0 0xff01>,      /* Secure Phys IRQ */
  94                              <1 13 0xff01>,     /* Non-secure Phys IRQ */
  95                              <1 14 0xff01>,     /* Virt IRQ */
  96                              <1 15 0xff01>;     /* Hyp IRQ */
  97                 clock-frequency = <50000000>;
  98         };
  99
 100         pmu {
 101                 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
 102                 interrupts = <1 12 0xff04>;
 103         };
 104
 105         soc {
 106                 compatible = "simple-bus";
 107                 #address-cells = <2>;
 108                 #size-cells = <2>;
 109                 ranges;
 110                 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
 111
 112                 clocks {
 113                         #address-cells = <2>;
 114                         #size-cells = <2>;
 115                         ranges;
 116                         refclk: refclk {
 117                                 compatible = "fixed-clock";
 118                                 #clock-cells = <1>;
 119                                 clock-frequency = <100000000>;
 120                                 clock-output-names = "refclk";
 121                         };
 122
 123                         pcppll: pcppll@17000100 {
 124                                 compatible = "apm,xgene-pcppll-clock";
 125                                 #clock-cells = <1>;
 126                                 clocks = <&refclk 0>;
 127                                 clock-names = "pcppll";
 128                                 reg = <0x0 0x17000100 0x0 0x1000>;
 129                                 clock-output-names = "pcppll";
 130                                 type = <0>;
 131                         };
 132
 133                         socpll: socpll@17000120 {
 134                                 compatible = "apm,xgene-socpll-clock";
 135                                 #clock-cells = <1>;
 136                                 clocks = <&refclk 0>;
 137                                 clock-names = "socpll";
 138                                 reg = <0x0 0x17000120 0x0 0x1000>;
 139                                 clock-output-names = "socpll";
 140                                 type = <1>;
 141                         };
 142
 143                         socplldiv2: socplldiv2  {
 144                                 compatible = "fixed-factor-clock";
 145                                 #clock-cells = <1>;
 146                                 clocks = <&socpll 0>;
 147                                 clock-names = "socplldiv2";
 148                                 clock-mult = <1>;
 149                                 clock-div = <2>;
 150                                 clock-output-names = "socplldiv2";
 151                         };
 152
 153                         qmlclk: qmlclk {
 154                                 compatible = "apm,xgene-device-clock";
 155                                 #clock-cells = <1>;
 156                                 clocks = <&socplldiv2 0>;
 157                                 clock-names = "qmlclk";
 158                                 reg = <0x0 0x1703C000 0x0 0x1000>;
 159                                 reg-names = "csr-reg";
 160                                 clock-output-names = "qmlclk";
 161                         };
 162
 163                         ethclk: ethclk {
 164                                 compatible = "apm,xgene-device-clock";
 165                                 #clock-cells = <1>;
 166                                 clocks = <&socplldiv2 0>;
 167                                 clock-names = "ethclk";
 168                                 reg = <0x0 0x17000000 0x0 0x1000>;
 169                                 reg-names = "div-reg";
 170                                 divider-offset = <0x238>;
 171                                 divider-width = <0x9>;
 172                                 divider-shift = <0x0>;
 173                                 clock-output-names = "ethclk";
 174                         };
 175
 176                         menetclk: menetclk {
 177                                 compatible = "apm,xgene-device-clock";
 178                                 #clock-cells = <1>;
 179                                 clocks = <&ethclk 0>;
 180                                 reg = <0x0 0x1702C000 0x0 0x1000>;
 181                                 reg-names = "csr-reg";
 182                                 clock-output-names = "menetclk";
 183                         };
 184
 185                         sge0clk: sge0clk@1f21c000 {
 186                                 compatible = "apm,xgene-device-clock";
 187                                 #clock-cells = <1>;
 188                                 clocks = <&socplldiv2 0>;
 189                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 190                                 reg-names = "csr-reg";
 191                                 csr-mask = <0x3>;
 192                                 clock-output-names = "sge0clk";
 193                         };
 194
 195                         sge1clk: sge1clk@1f21c000 {
 196                                 compatible = "apm,xgene-device-clock";
 197                                 #clock-cells = <1>;
 198                                 clocks = <&socplldiv2 0>;
 199                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 200                                 reg-names = "csr-reg";
 201                                 csr-mask = <0xc>;
 202                                 clock-output-names = "sge1clk";
 203                         };
 204
 205                         xge0clk: xge0clk@1f61c000 {
 206                                 compatible = "apm,xgene-device-clock";
 207                                 #clock-cells = <1>;
 208                                 clocks = <&socplldiv2 0>;
 209                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 210                                 reg-names = "csr-reg";
 211                                 csr-mask = <0x3>;
 212                                 clock-output-names = "xge0clk";
 213                         };
 214
 215                         sataphy1clk: sataphy1clk@1f21c000 {
 216                                 compatible = "apm,xgene-device-clock";
 217                                 #clock-cells = <1>;
 218                                 clocks = <&socplldiv2 0>;
 219                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 220                                 reg-names = "csr-reg";
 221                                 clock-output-names = "sataphy1clk";
 222                                 status = "disabled";
 223                                 csr-offset = <0x4>;
 224                                 csr-mask = <0x00>;
 225                                 enable-offset = <0x0>;
 226                                 enable-mask = <0x06>;
 227                         };
 228
 229                         sataphy2clk: sataphy1clk@1f22c000 {
 230                                 compatible = "apm,xgene-device-clock";
 231                                 #clock-cells = <1>;
 232                                 clocks = <&socplldiv2 0>;
 233                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 234                                 reg-names = "csr-reg";
 235                                 clock-output-names = "sataphy2clk";
 236                                 status = "ok";
 237                                 csr-offset = <0x4>;
 238                                 csr-mask = <0x3a>;
 239                                 enable-offset = <0x0>;
 240                                 enable-mask = <0x06>;
 241                         };
 242
 243                         sataphy3clk: sataphy1clk@1f23c000 {
 244                                 compatible = "apm,xgene-device-clock";
 245                                 #clock-cells = <1>;
 246                                 clocks = <&socplldiv2 0>;
 247                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 248                                 reg-names = "csr-reg";
 249                                 clock-output-names = "sataphy3clk";
 250                                 status = "ok";
 251                                 csr-offset = <0x4>;
 252                                 csr-mask = <0x3a>;
 253                                 enable-offset = <0x0>;
 254                                 enable-mask = <0x06>;
 255                         };
 256
 257                         sata01clk: sata01clk@1f21c000 {
 258                                 compatible = "apm,xgene-device-clock";
 259                                 #clock-cells = <1>;
 260                                 clocks = <&socplldiv2 0>;
 261                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 262                                 reg-names = "csr-reg";
 263                                 clock-output-names = "sata01clk";
 264                                 csr-offset = <0x4>;
 265                                 csr-mask = <0x05>;
 266                                 enable-offset = <0x0>;
 267                                 enable-mask = <0x39>;
 268                         };
 269
 270                         sata23clk: sata23clk@1f22c000 {
 271                                 compatible = "apm,xgene-device-clock";
 272                                 #clock-cells = <1>;
 273                                 clocks = <&socplldiv2 0>;
 274                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 275                                 reg-names = "csr-reg";
 276                                 clock-output-names = "sata23clk";
 277                                 csr-offset = <0x4>;
 278                                 csr-mask = <0x05>;
 279                                 enable-offset = <0x0>;
 280                                 enable-mask = <0x39>;
 281                         };
 282
 283                         sata45clk: sata45clk@1f23c000 {
 284                                 compatible = "apm,xgene-device-clock";
 285                                 #clock-cells = <1>;
 286                                 clocks = <&socplldiv2 0>;
 287                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 288                                 reg-names = "csr-reg";
 289                                 clock-output-names = "sata45clk";
 290                                 csr-offset = <0x4>;
 291                                 csr-mask = <0x05>;
 292                                 enable-offset = <0x0>;
 293                                 enable-mask = <0x39>;
 294                         };
 295
 296                         rtcclk: rtcclk@17000000 {
 297                                 compatible = "apm,xgene-device-clock";
 298                                 #clock-cells = <1>;
 299                                 clocks = <&socplldiv2 0>;
 300                                 reg = <0x0 0x17000000 0x0 0x2000>;
 301                                 reg-names = "csr-reg";
 302                                 csr-offset = <0xc>;
 303                                 csr-mask = <0x2>;
 304                                 enable-offset = <0x10>;
 305                                 enable-mask = <0x2>;
 306                                 clock-output-names = "rtcclk";
 307                         };
 308
 309                         rngpkaclk: rngpkaclk@17000000 {
 310                                 compatible = "apm,xgene-device-clock";
 311                                 #clock-cells = <1>;
 312                                 clocks = <&socplldiv2 0>;
 313                                 reg = <0x0 0x17000000 0x0 0x2000>;
 314                                 reg-names = "csr-reg";
 315                                 csr-offset = <0xc>;
 316                                 csr-mask = <0x10>;
 317                                 enable-offset = <0x10>;
 318                                 enable-mask = <0x10>;
 319                                 clock-output-names = "rngpkaclk";
 320                         };
 321
 322                         pcie0clk: pcie0clk@1f2bc000 {
 323                                 status = "disabled";
 324                                 compatible = "apm,xgene-device-clock";
 325                                 #clock-cells = <1>;
 326                                 clocks = <&socplldiv2 0>;
 327                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 328                                 reg-names = "csr-reg";
 329                                 clock-output-names = "pcie0clk";
 330                         };
 331
 332                         pcie1clk: pcie1clk@1f2cc000 {
 333                                 status = "disabled";
 334                                 compatible = "apm,xgene-device-clock";
 335                                 #clock-cells = <1>;
 336                                 clocks = <&socplldiv2 0>;
 337                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 338                                 reg-names = "csr-reg";
 339                                 clock-output-names = "pcie1clk";
 340                         };
 341
 342                         pcie2clk: pcie2clk@1f2dc000 {
 343                                 status = "disabled";
 344                                 compatible = "apm,xgene-device-clock";
 345                                 #clock-cells = <1>;
 346                                 clocks = <&socplldiv2 0>;
 347                                 reg = <0x0 0x1f2dc000 0x0 0x1000>;
 348                                 reg-names = "csr-reg";
 349                                 clock-output-names = "pcie2clk";
 350                         };
 351
 352                         pcie3clk: pcie3clk@1f50c000 {
 353                                 status = "disabled";
 354                                 compatible = "apm,xgene-device-clock";
 355                                 #clock-cells = <1>;
 356                                 clocks = <&socplldiv2 0>;
 357                                 reg = <0x0 0x1f50c000 0x0 0x1000>;
 358                                 reg-names = "csr-reg";
 359                                 clock-output-names = "pcie3clk";
 360                         };
 361
 362                         pcie4clk: pcie4clk@1f51c000 {
 363                                 status = "disabled";
 364                                 compatible = "apm,xgene-device-clock";
 365                                 #clock-cells = <1>;
 366                                 clocks = <&socplldiv2 0>;
 367                                 reg = <0x0 0x1f51c000 0x0 0x1000>;
 368                                 reg-names = "csr-reg";
 369                                 clock-output-names = "pcie4clk";
 370                         };
 371
 372                         dmaclk: dmaclk@1f27c000 {
 373                                 compatible = "apm,xgene-device-clock";
 374                                 #clock-cells = <1>;
 375                                 clocks = <&socplldiv2 0>;
 376                                 reg = <0x0 0x1f27c000 0x0 0x1000>;
 377                                 reg-names = "csr-reg";
 378                                 clock-output-names = "dmaclk";
 379                         };
 380                 };
 381
 382                 msi: msi@79000000 {
 383                         compatible = "apm,xgene1-msi";
 384                         msi-controller;
 385                         reg = <0x00 0x79000000 0x0 0x900000>;
 386                         interrupts = <  0x0 0x10 0x4
 387                                         0x0 0x11 0x4
 388                                         0x0 0x12 0x4
 389                                         0x0 0x13 0x4
 390                                         0x0 0x14 0x4
 391                                         0x0 0x15 0x4
 392                                         0x0 0x16 0x4
 393                                         0x0 0x17 0x4
 394                                         0x0 0x18 0x4
 395                                         0x0 0x19 0x4
 396                                         0x0 0x1a 0x4
 397                                         0x0 0x1b 0x4
 398                                         0x0 0x1c 0x4
 399                                         0x0 0x1d 0x4
 400                                         0x0 0x1e 0x4
 401                                         0x0 0x1f 0x4>;
 402                 };
 403
 404                 scu: system-clk-controller@17000000 {
 405                         compatible = "apm,xgene-scu","syscon";
 406                         reg = <0x0 0x17000000 0x0 0x400>;
 407                 };
 408
 409                 reboot: reboot@17000014 {
 410                         compatible = "syscon-reboot";
 411                         regmap = <&scu>;
 412                         offset = <0x14>;
 413                         mask = <0x1>;
 414                 };
 415
 416                 csw: csw@7e200000 {
 417                         compatible = "apm,xgene-csw", "syscon";
 418                         reg = <0x0 0x7e200000 0x0 0x1000>;
 419                 };
 420
 421                 mcba: mcba@7e700000 {
 422                         compatible = "apm,xgene-mcb", "syscon";
 423                         reg = <0x0 0x7e700000 0x0 0x1000>;
 424                 };
 425
 426                 mcbb: mcbb@7e720000 {
 427                         compatible = "apm,xgene-mcb", "syscon";
 428                         reg = <0x0 0x7e720000 0x0 0x1000>;
 429                 };
 430
 431                 efuse: efuse@1054a000 {
 432                         compatible = "apm,xgene-efuse", "syscon";
 433                         reg = <0x0 0x1054a000 0x0 0x20>;
 434                 };
 435
 436                 edac@78800000 {
 437                         compatible = "apm,xgene-edac";
 438                         #address-cells = <2>;
 439                         #size-cells = <2>;
 440                         ranges;
 441                         regmap-csw = <&csw>;
 442                         regmap-mcba = <&mcba>;
 443                         regmap-mcbb = <&mcbb>;
 444                         regmap-efuse = <&efuse>;
 445                         reg = <0x0 0x78800000 0x0 0x100>;
 446                         interrupts = <0x0 0x20 0x4>,
 447                                      <0x0 0x21 0x4>,
 448                                      <0x0 0x27 0x4>;
 449
 450                         edacmc@7e800000 {
 451                                 compatible = "apm,xgene-edac-mc";
 452                                 reg = <0x0 0x7e800000 0x0 0x1000>;
 453                                 memory-controller = <0>;
 454                         };
 455
 456                         edacmc@7e840000 {
 457                                 compatible = "apm,xgene-edac-mc";
 458                                 reg = <0x0 0x7e840000 0x0 0x1000>;
 459                                 memory-controller = <1>;
 460                         };
 461
 462                         edacmc@7e880000 {
 463                                 compatible = "apm,xgene-edac-mc";
 464                                 reg = <0x0 0x7e880000 0x0 0x1000>;
 465                                 memory-controller = <2>;
 466                         };
 467
 468                         edacmc@7e8c0000 {
 469                                 compatible = "apm,xgene-edac-mc";
 470                                 reg = <0x0 0x7e8c0000 0x0 0x1000>;
 471                                 memory-controller = <3>;
 472                         };
 473
 474                         edacpmd@7c000000 {
 475                                 compatible = "apm,xgene-edac-pmd";
 476                                 reg = <0x0 0x7c000000 0x0 0x200000>;
 477                                 pmd-controller = <0>;
 478                         };
 479
 480                         edacpmd@7c200000 {
 481                                 compatible = "apm,xgene-edac-pmd";
 482                                 reg = <0x0 0x7c200000 0x0 0x200000>;
 483                                 pmd-controller = <1>;
 484                         };
 485
 486                         edacpmd@7c400000 {
 487                                 compatible = "apm,xgene-edac-pmd";
 488                                 reg = <0x0 0x7c400000 0x0 0x200000>;
 489                                 pmd-controller = <2>;
 490                         };
 491
 492                         edacpmd@7c600000 {
 493                                 compatible = "apm,xgene-edac-pmd";
 494                                 reg = <0x0 0x7c600000 0x0 0x200000>;
 495                                 pmd-controller = <3>;
 496                         };
 497                 };
 498
 499                 pcie0: pcie@1f2b0000 {
 500                         status = "disabled";
 501                         device_type = "pci";
 502                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 503                         #interrupt-cells = <1>;
 504                         #size-cells = <2>;
 505                         #address-cells = <3>;
 506                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 507                                 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 508                         reg-names = "csr", "cfg";
 509                         ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 510                                   0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
 511                                   0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
 512                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 513                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 514                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 515                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
 516                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
 517                                          0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
 518                                          0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
 519                         dma-coherent;
 520                         clocks = <&pcie0clk 0>;
 521                         msi-parent = <&msi>;
 522                 };
 523
 524                 pcie1: pcie@1f2c0000 {
 525                         status = "disabled";
 526                         device_type = "pci";
 527                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 528                         #interrupt-cells = <1>;
 529                         #size-cells = <2>;
 530                         #address-cells = <3>;
 531                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 532                                 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 533                         reg-names = "csr", "cfg";
 534                         ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 535                                   0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
 536                                   0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
 537                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 538                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 539                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 540                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
 541                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
 542                                          0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
 543                                          0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
 544                         dma-coherent;
 545                         clocks = <&pcie1clk 0>;
 546                         msi-parent = <&msi>;
 547                 };
 548
 549                 pcie2: pcie@1f2d0000 {
 550                         status = "disabled";
 551                         device_type = "pci";
 552                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 553                         #interrupt-cells = <1>;
 554                         #size-cells = <2>;
 555                         #address-cells = <3>;
 556                         reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
 557                                  0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
 558                         reg-names = "csr", "cfg";
 559                         ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
 560                                   0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
 561                                   0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
 562                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 563                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 564                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 565                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
 566                                          0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
 567                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
 568                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
 569                         dma-coherent;
 570                         clocks = <&pcie2clk 0>;
 571                         msi-parent = <&msi>;
 572                 };
 573
 574                 pcie3: pcie@1f500000 {
 575                         status = "disabled";
 576                         device_type = "pci";
 577                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 578                         #interrupt-cells = <1>;
 579                         #size-cells = <2>;
 580                         #address-cells = <3>;
 581                         reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
 582                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 583                         reg-names = "csr", "cfg";
 584                         ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
 585                                   0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
 586                                   0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
 587                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 588                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 589                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 590                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
 591                                          0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
 592                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
 593                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
 594                         dma-coherent;
 595                         clocks = <&pcie3clk 0>;
 596                         msi-parent = <&msi>;
 597                 };
 598
 599                 pcie4: pcie@1f510000 {
 600                         status = "disabled";
 601                         device_type = "pci";
 602                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 603                         #interrupt-cells = <1>;
 604                         #size-cells = <2>;
 605                         #address-cells = <3>;
 606                         reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
 607                                 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
 608                         reg-names = "csr", "cfg";
 609                         ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
 610                                   0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
 611                                   0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
 612                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 613                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 614                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 615                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
 616                                          0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
 617                                          0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
 618                                          0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
 619                         dma-coherent;
 620                         clocks = <&pcie4clk 0>;
 621                         msi-parent = <&msi>;
 622                 };
 623
 624                 serial0: serial@1c020000 {
 625                         status = "disabled";
 626                         device_type = "serial";
 627                         compatible = "ns16550a";
 628                         reg = <0 0x1c020000 0x0 0x1000>;
 629                         reg-shift = <2>;
 630                         clock-frequency = <10000000>; /* Updated by bootloader */
 631                         interrupt-parent = <&gic>;
 632                         interrupts = <0x0 0x4c 0x4>;
 633                 };
 634
 635                 serial1: serial@1c021000 {
 636                         status = "disabled";
 637                         device_type = "serial";
 638                         compatible = "ns16550a";
 639                         reg = <0 0x1c021000 0x0 0x1000>;
 640                         reg-shift = <2>;
 641                         clock-frequency = <10000000>; /* Updated by bootloader */
 642                         interrupt-parent = <&gic>;
 643                         interrupts = <0x0 0x4d 0x4>;
 644                 };
 645
 646                 serial2: serial@1c022000 {
 647                         status = "disabled";
 648                         device_type = "serial";
 649                         compatible = "ns16550a";
 650                         reg = <0 0x1c022000 0x0 0x1000>;
 651                         reg-shift = <2>;
 652                         clock-frequency = <10000000>; /* Updated by bootloader */
 653                         interrupt-parent = <&gic>;
 654                         interrupts = <0x0 0x4e 0x4>;
 655                 };
 656
 657                 serial3: serial@1c023000 {
 658                         status = "disabled";
 659                         device_type = "serial";
 660                         compatible = "ns16550a";
 661                         reg = <0 0x1c023000 0x0 0x1000>;
 662                         reg-shift = <2>;
 663                         clock-frequency = <10000000>; /* Updated by bootloader */
 664                         interrupt-parent = <&gic>;
 665                         interrupts = <0x0 0x4f 0x4>;
 666                 };
 667
 668                 phy1: phy@1f21a000 {
 669                         compatible = "apm,xgene-phy";
 670                         reg = <0x0 0x1f21a000 0x0 0x100>;
 671                         #phy-cells = <1>;
 672                         clocks = <&sataphy1clk 0>;
 673                         status = "disabled";
 674                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 675                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 676                 };
 677
 678                 phy2: phy@1f22a000 {
 679                         compatible = "apm,xgene-phy";
 680                         reg = <0x0 0x1f22a000 0x0 0x100>;
 681                         #phy-cells = <1>;
 682                         clocks = <&sataphy2clk 0>;
 683                         status = "ok";
 684                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 685                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 686                 };
 687
 688                 phy3: phy@1f23a000 {
 689                         compatible = "apm,xgene-phy";
 690                         reg = <0x0 0x1f23a000 0x0 0x100>;
 691                         #phy-cells = <1>;
 692                         clocks = <&sataphy3clk 0>;
 693                         status = "ok";
 694                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 695                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 696                 };
 697
 698                 sata1: sata@1a000000 {
 699                         compatible = "apm,xgene-ahci";
 700                         reg = <0x0 0x1a000000 0x0 0x1000>,
 701                               <0x0 0x1f210000 0x0 0x1000>,
 702                               <0x0 0x1f21d000 0x0 0x1000>,
 703                               <0x0 0x1f21e000 0x0 0x1000>,
 704                               <0x0 0x1f217000 0x0 0x1000>;
 705                         interrupts = <0x0 0x86 0x4>;
 706                         dma-coherent;
 707                         status = "disabled";
 708                         clocks = <&sata01clk 0>;
 709                         phys = <&phy1 0>;
 710                         phy-names = "sata-phy";
 711                 };
 712
 713                 sata2: sata@1a400000 {
 714                         compatible = "apm,xgene-ahci";
 715                         reg = <0x0 0x1a400000 0x0 0x1000>,
 716                               <0x0 0x1f220000 0x0 0x1000>,
 717                               <0x0 0x1f22d000 0x0 0x1000>,
 718                               <0x0 0x1f22e000 0x0 0x1000>,
 719                               <0x0 0x1f227000 0x0 0x1000>;
 720                         interrupts = <0x0 0x87 0x4>;
 721                         dma-coherent;
 722                         status = "ok";
 723                         clocks = <&sata23clk 0>;
 724                         phys = <&phy2 0>;
 725                         phy-names = "sata-phy";
 726                 };
 727
 728                 sata3: sata@1a800000 {
 729                         compatible = "apm,xgene-ahci";
 730                         reg = <0x0 0x1a800000 0x0 0x1000>,
 731                               <0x0 0x1f230000 0x0 0x1000>,
 732                               <0x0 0x1f23d000 0x0 0x1000>,
 733                               <0x0 0x1f23e000 0x0 0x1000>;
 734                         interrupts = <0x0 0x88 0x4>;
 735                         dma-coherent;
 736                         status = "ok";
 737                         clocks = <&sata45clk 0>;
 738                         phys = <&phy3 0>;
 739                         phy-names = "sata-phy";
 740                 };
 741
 742                 sbgpio: sbgpio@17001000{
 743                         compatible = "apm,xgene-gpio-sb";
 744                         reg = <0x0 0x17001000 0x0 0x400>;
 745                         #gpio-cells = <2>;
 746                         gpio-controller;
 747                         interrupts =    <0x0 0x28 0x1>,
 748                                         <0x0 0x29 0x1>,
 749                                         <0x0 0x2a 0x1>,
 750                                         <0x0 0x2b 0x1>,
 751                                         <0x0 0x2c 0x1>,
 752                                         <0x0 0x2d 0x1>;
 753                 };
 754
 755                 rtc: rtc@10510000 {
 756                         compatible = "apm,xgene-rtc";
 757                         reg = <0x0 0x10510000 0x0 0x400>;
 758                         interrupts = <0x0 0x46 0x4>;
 759                         #clock-cells = <1>;
 760                         clocks = <&rtcclk 0>;
 761                 };
 762
 763                 menet: ethernet@17020000 {
 764                         compatible = "apm,xgene-enet";
 765                         status = "disabled";
 766                         reg = <0x0 0x17020000 0x0 0xd100>,
 767                               <0x0 0X17030000 0x0 0Xc300>,
 768                               <0x0 0X10000000 0x0 0X200>;
 769                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 770                         interrupts = <0x0 0x3c 0x4>;
 771                         dma-coherent;
 772                         clocks = <&menetclk 0>;
 773                         /* mac address will be overwritten by the bootloader */
 774                         local-mac-address = [00 00 00 00 00 00];
 775                         phy-connection-type = "rgmii";
 776                         phy-handle = <&menetphy>;
 777                         mdio {
 778                                 compatible = "apm,xgene-mdio";
 779                                 #address-cells = <1>;
 780                                 #size-cells = <0>;
 781                                 menetphy: menetphy@3 {
 782                                         compatible = "ethernet-phy-id001c.c915";
 783                                         reg = <0x3>;
 784                                 };
 785
 786                         };
 787                 };
 788
 789                 sgenet0: ethernet@1f210000 {
 790                         compatible = "apm,xgene1-sgenet";
 791                         status = "disabled";
 792                         reg = <0x0 0x1f210000 0x0 0xd100>,
 793                               <0x0 0x1f200000 0x0 0Xc300>,
 794                               <0x0 0x1B000000 0x0 0X200>;
 795                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 796                         interrupts = <0x0 0xA0 0x4>,
 797                                      <0x0 0xA1 0x4>;
 798                         dma-coherent;
 799                         clocks = <&sge0clk 0>;
 800                         local-mac-address = [00 00 00 00 00 00];
 801                         phy-connection-type = "sgmii";
 802                 };
 803
 804                 sgenet1: ethernet@1f210030 {
 805                         compatible = "apm,xgene1-sgenet";
 806                         status = "disabled";
 807                         reg = <0x0 0x1f210030 0x0 0xd100>,
 808                               <0x0 0x1f200000 0x0 0Xc300>,
 809                               <0x0 0x1B000000 0x0 0X8000>;
 810                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 811                         interrupts = <0x0 0xAC 0x4>,
 812                                      <0x0 0xAD 0x4>;
 813                         port-id = <1>;
 814                         dma-coherent;
 815                         clocks = <&sge1clk 0>;
 816                         local-mac-address = [00 00 00 00 00 00];
 817                         phy-connection-type = "sgmii";
 818                 };
 819
 820                 xgenet: ethernet@1f610000 {
 821                         compatible = "apm,xgene1-xgenet";
 822                         status = "disabled";
 823                         reg = <0x0 0x1f610000 0x0 0xd100>,
 824                               <0x0 0x1f600000 0x0 0Xc300>,
 825                               <0x0 0x18000000 0x0 0X200>;
 826                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 827                         interrupts = <0x0 0x60 0x4>,
 828                                      <0x0 0x61 0x4>;
 829                         dma-coherent;
 830                         clocks = <&xge0clk 0>;
 831                         /* mac address will be overwritten by the bootloader */
 832                         local-mac-address = [00 00 00 00 00 00];
 833                         phy-connection-type = "xgmii";
 834                 };
 835
 836                 rng: rng@10520000 {
 837                         compatible = "apm,xgene-rng";
 838                         reg = <0x0 0x10520000 0x0 0x100>;
 839                         interrupts = <0x0 0x41 0x4>;
 840                         clocks = <&rngpkaclk 0>;
 841                 };
 842
 843                 dma: dma@1f270000 {
 844                         compatible = "apm,xgene-storm-dma";
 845                         device_type = "dma";
 846                         reg = <0x0 0x1f270000 0x0 0x10000>,
 847                               <0x0 0x1f200000 0x0 0x10000>,
 848                               <0x0 0x1b000000 0x0 0x400000>,
 849                               <0x0 0x1054a000 0x0 0x100>;
 850                         interrupts = <0x0 0x82 0x4>,
 851                                      <0x0 0xb8 0x4>,
 852                                      <0x0 0xb9 0x4>,
 853                                      <0x0 0xba 0x4>,
 854                                      <0x0 0xbb 0x4>;
 855                         dma-coherent;
 856                         clocks = <&dmaclk 0>;
 857                 };
 858         };
 859 };