arch/arm64/boot/dts/broadcom/ns2.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright (c) 2015 Broadcom.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /memreserve/ 0x81000000 0x00200000;
  34
  35 #include <dt-bindings/interrupt-controller/arm-gic.h>
  36 #include <dt-bindings/clock/bcm-ns2.h>
  37
  38 / {
  39         compatible = "brcm,ns2";
  40         interrupt-parent = <&gic>;
  41         #address-cells = <2>;
  42         #size-cells = <2>;
  43
  44         cpus {
  45                 #address-cells = <2>;
  46                 #size-cells = <0>;
  47
  48                 A57_0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a57", "arm,armv8";
  51                         reg = <0 0>;
  52                         enable-method = "psci";
  53                         next-level-cache = <&CLUSTER0_L2>;
  54                 };
  55
  56                 A57_1: cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a57", "arm,armv8";
  59                         reg = <0 1>;
  60                         enable-method = "psci";
  61                         next-level-cache = <&CLUSTER0_L2>;
  62                 };
  63
  64                 A57_2: cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a57", "arm,armv8";
  67                         reg = <0 2>;
  68                         enable-method = "psci";
  69                         next-level-cache = <&CLUSTER0_L2>;
  70                 };
  71
  72                 A57_3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a57", "arm,armv8";
  75                         reg = <0 3>;
  76                         enable-method = "psci";
  77                         next-level-cache = <&CLUSTER0_L2>;
  78                 };
  79
  80                 CLUSTER0_L2: l2-cache@000 {
  81                         compatible = "cache";
  82                 };
  83         };
  84
  85         psci {
  86                 compatible = "arm,psci-1.0";
  87                 method = "smc";
  88         };
  89
  90         timer {
  91                 compatible = "arm,armv8-timer";
  92                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
  93                               IRQ_TYPE_LEVEL_LOW)>,
  94                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
  95                               IRQ_TYPE_LEVEL_LOW)>,
  96                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
  97                               IRQ_TYPE_LEVEL_LOW)>,
  98                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
  99                               IRQ_TYPE_LEVEL_LOW)>;
 100         };
 101
 102         pmu {
 103                 compatible = "arm,armv8-pmuv3";
 104                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 107                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 108                 interrupt-affinity = <&A57_0>,
 109                                      <&A57_1>,
 110                                      <&A57_2>,
 111                                      <&A57_3>;
 112         };
 113
 114         pcie0: pcie@20020000 {
 115                 compatible = "brcm,iproc-pcie";
 116                 reg = <0 0x20020000 0 0x1000>;
 117                 dma-coherent;
 118
 119                 #interrupt-cells = <1>;
 120                 interrupt-map-mask = <0 0 0 0>;
 121                 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_NONE>;
 122
 123                 linux,pci-domain = <0>;
 124
 125                 bus-range = <0x00 0xff>;
 126
 127                 #address-cells = <3>;
 128                 #size-cells = <2>;
 129                 device_type = "pci";
 130                 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
 131
 132                 brcm,pcie-ob;
 133                 brcm,pcie-ob-oarr-size;
 134                 brcm,pcie-ob-axi-offset = <0x00000000>;
 135                 brcm,pcie-ob-window-size = <256>;
 136
 137                 status = "disabled";
 138
 139                 phys = <&pci_phy0>;
 140                 phy-names = "pcie-phy";
 141
 142                 msi-parent = <&v2m0>;
 143         };
 144
 145         pcie4: pcie@50020000 {
 146                 compatible = "brcm,iproc-pcie";
 147                 reg = <0 0x50020000 0 0x1000>;
 148                 dma-coherent;
 149
 150                 #interrupt-cells = <1>;
 151                 interrupt-map-mask = <0 0 0 0>;
 152                 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_NONE>;
 153
 154                 linux,pci-domain = <4>;
 155
 156                 bus-range = <0x00 0xff>;
 157
 158                 #address-cells = <3>;
 159                 #size-cells = <2>;
 160                 device_type = "pci";
 161                 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
 162
 163                 brcm,pcie-ob;
 164                 brcm,pcie-ob-oarr-size;
 165                 brcm,pcie-ob-axi-offset = <0x30000000>;
 166                 brcm,pcie-ob-window-size = <256>;
 167
 168                 status = "disabled";
 169
 170                 phys = <&pci_phy1>;
 171                 phy-names = "pcie-phy";
 172
 173                 msi-parent = <&v2m0>;
 174         };
 175
 176         pcie8: pcie@60c00000 {
 177                 compatible = "brcm,iproc-pcie-paxc";
 178                 reg = <0 0x60c00000 0 0x1000>;
 179                 dma-coherent;
 180                 linux,pci-domain = <8>;
 181
 182                 bus-range = <0x0 0x1>;
 183
 184                 #address-cells = <3>;
 185                 #size-cells = <2>;
 186                 device_type = "pci";
 187                 ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
 188
 189                 status = "disabled";
 190
 191                 msi-parent = <&v2m0>;
 192         };
 193
 194         soc: soc {
 195                 compatible = "simple-bus";
 196                 #address-cells = <1>;
 197                 #size-cells = <1>;
 198                 ranges = <0 0 0 0xffffffff>;
 199
 200                 #include "ns2-clock.dtsi"
 201
 202                 enet: ethernet@61000000 {
 203                         compatible = "brcm,ns2-amac";
 204                         reg = <0x61000000 0x1000>,
 205                               <0x61090000 0x1000>,
 206                               <0x61030000 0x100>;
 207                         reg-names = "amac_base", "idm_base", "nicpm_base";
 208                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 209                         dma-coherent;
 210                         phy-handle = <&gphy0>;
 211                         phy-mode = "rgmii";
 212                         status = "disabled";
 213                 };
 214
 215                 pdc0: iproc-pdc0@612c0000 {
 216                         compatible = "brcm,iproc-pdc-mbox";
 217                         reg = <0x612c0000 0x445>;  /* PDC FS0 regs */
 218                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 219                         #mbox-cells = <1>;
 220                         dma-coherent;
 221                         brcm,rx-status-len = <32>;
 222                         brcm,use-bcm-hdr;
 223                 };
 224
 225                 crypto0: crypto@612d0000 {
 226                         compatible = "brcm,spum-crypto";
 227                         reg = <0x612d0000 0x900>;
 228                         mboxes = <&pdc0 0>;
 229                 };
 230
 231                 pdc1: iproc-pdc1@612e0000 {
 232                         compatible = "brcm,iproc-pdc-mbox";
 233                         reg = <0x612e0000 0x445>;  /* PDC FS1 regs */
 234                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 235                         #mbox-cells = <1>;
 236                         dma-coherent;
 237                         brcm,rx-status-len = <32>;
 238                         brcm,use-bcm-hdr;
 239                 };
 240
 241                 crypto1: crypto@612f0000 {
 242                         compatible = "brcm,spum-crypto";
 243                         reg = <0x612f0000 0x900>;
 244                         mboxes = <&pdc1 0>;
 245                 };
 246
 247                 pdc2: iproc-pdc2@61300000 {
 248                         compatible = "brcm,iproc-pdc-mbox";
 249                         reg = <0x61300000 0x445>;  /* PDC FS2 regs */
 250                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 251                         #mbox-cells = <1>;
 252                         dma-coherent;
 253                         brcm,rx-status-len = <32>;
 254                         brcm,use-bcm-hdr;
 255                 };
 256
 257                 crypto2: crypto@61310000 {
 258                         compatible = "brcm,spum-crypto";
 259                         reg = <0x61310000 0x900>;
 260                         mboxes = <&pdc2 0>;
 261                 };
 262
 263                 pdc3: iproc-pdc3@61320000 {
 264                         compatible = "brcm,iproc-pdc-mbox";
 265                         reg = <0x61320000 0x445>;  /* PDC FS3 regs */
 266                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 267                         #mbox-cells = <1>;
 268                         dma-coherent;
 269                         brcm,rx-status-len = <32>;
 270                         brcm,use-bcm-hdr;
 271                 };
 272
 273                 crypto3: crypto@61330000 {
 274                         compatible = "brcm,spum-crypto";
 275                         reg = <0x61330000 0x900>;
 276                         mboxes = <&pdc3 0>;
 277                 };
 278
 279                 dma0: dma@61360000 {
 280                         compatible = "arm,pl330", "arm,primecell";
 281                         reg = <0x61360000 0x1000>;
 282                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
 284                                      <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 287                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 288                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 291                         #dma-cells = <1>;
 292                         #dma-channels = <8>;
 293                         #dma-requests = <32>;
 294                         clocks = <&iprocslow>;
 295                         clock-names = "apb_pclk";
 296                 };
 297
 298                 smmu: mmu@64000000 {
 299                         compatible = "arm,mmu-500";
 300                         reg = <0x64000000 0x40000>;
 301                         #global-interrupts = <2>;
 302                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
 306                                      <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
 307                                      <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
 309                                      <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 312                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 313                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 314                                      <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 315                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 316                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 317                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 318                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 319                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 320                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 321                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 322                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 324                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 325                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 326                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 327                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 328                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 329                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 330                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 331                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 332                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 333                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 334                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 335                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
 336                         #iommu-cells = <1>;
 337                 };
 338
 339                 pinctrl: pinctrl@6501d130 {
 340                         compatible = "brcm,ns2-pinmux";
 341                         reg = <0x6501d130 0x08>,
 342                               <0x660a0028 0x04>,
 343                               <0x660009b0 0x40>;
 344                 };
 345
 346                 gpio_aon: gpio@65024800 {
 347                         compatible = "brcm,iproc-gpio";
 348                         reg = <0x65024800 0x50>,
 349                               <0x65024008 0x18>;
 350                         ngpios = <6>;
 351                         #gpio-cells = <2>;
 352                         gpio-controller;
 353                 };
 354
 355                 gic: interrupt-controller@65210000 {
 356                         compatible = "arm,gic-400";
 357                         #interrupt-cells = <3>;
 358                         interrupt-controller;
 359                         reg = <0x65210000 0x1000>,
 360                               <0x65220000 0x1000>,
 361                               <0x65240000 0x2000>,
 362                               <0x65260000 0x1000>;
 363                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 364                                       IRQ_TYPE_LEVEL_HIGH)>;
 365
 366                         #address-cells = <1>;
 367                         #size-cells = <1>;
 368                         ranges = <0 0x652e0000 0x80000>;
 369
 370                         v2m0: v2m@00000 {
 371                                 compatible = "arm,gic-v2m-frame";
 372                                 interrupt-parent = <&gic>;
 373                                 msi-controller;
 374                                 reg = <0x00000 0x1000>;
 375                                 arm,msi-base-spi = <72>;
 376                                 arm,msi-num-spis = <16>;
 377                         };
 378
 379                         v2m1: v2m@10000 {
 380                                 compatible = "arm,gic-v2m-frame";
 381                                 interrupt-parent = <&gic>;
 382                                 msi-controller;
 383                                 reg = <0x10000 0x1000>;
 384                                 arm,msi-base-spi = <88>;
 385                                 arm,msi-num-spis = <16>;
 386                         };
 387
 388                         v2m2: v2m@20000 {
 389                                 compatible = "arm,gic-v2m-frame";
 390                                 interrupt-parent = <&gic>;
 391                                 msi-controller;
 392                                 reg = <0x20000 0x1000>;
 393                                 arm,msi-base-spi = <104>;
 394                                 arm,msi-num-spis = <16>;
 395                         };
 396
 397                         v2m3: v2m@30000 {
 398                                 compatible = "arm,gic-v2m-frame";
 399                                 interrupt-parent = <&gic>;
 400                                 msi-controller;
 401                                 reg = <0x30000 0x1000>;
 402                                 arm,msi-base-spi = <120>;
 403                                 arm,msi-num-spis = <16>;
 404                         };
 405
 406                         v2m4: v2m@40000 {
 407                                 compatible = "arm,gic-v2m-frame";
 408                                 interrupt-parent = <&gic>;
 409                                 msi-controller;
 410                                 reg = <0x40000 0x1000>;
 411                                 arm,msi-base-spi = <136>;
 412                                 arm,msi-num-spis = <16>;
 413                         };
 414
 415                         v2m5: v2m@50000 {
 416                                 compatible = "arm,gic-v2m-frame";
 417                                 interrupt-parent = <&gic>;
 418                                 msi-controller;
 419                                 reg = <0x50000 0x1000>;
 420                                 arm,msi-base-spi = <152>;
 421                                 arm,msi-num-spis = <16>;
 422                         };
 423
 424                         v2m6: v2m@60000 {
 425                                 compatible = "arm,gic-v2m-frame";
 426                                 interrupt-parent = <&gic>;
 427                                 msi-controller;
 428                                 reg = <0x60000 0x1000>;
 429                                 arm,msi-base-spi = <168>;
 430                                 arm,msi-num-spis = <16>;
 431                         };
 432
 433                         v2m7: v2m@70000 {
 434                                 compatible = "arm,gic-v2m-frame";
 435                                 interrupt-parent = <&gic>;
 436                                 msi-controller;
 437                                 reg = <0x70000 0x1000>;
 438                                 arm,msi-base-spi = <184>;
 439                                 arm,msi-num-spis = <16>;
 440                         };
 441                 };
 442
 443                 cci@65590000 {
 444                         compatible = "arm,cci-400";
 445                         #address-cells = <1>;
 446                         #size-cells = <1>;
 447                         reg = <0x65590000 0x1000>;
 448                         ranges = <0 0x65590000 0x10000>;
 449
 450                         pmu@9000 {
 451                                 compatible = "arm,cci-400-pmu,r1",
 452                                              "arm,cci-400-pmu";
 453                                 reg = <0x9000 0x4000>;
 454                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 455                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 456                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
 457                                              <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 458                                              <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 459                                              <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
 460                         };
 461                 };
 462
 463                 pwm: pwm@66010000 {
 464                         compatible = "brcm,iproc-pwm";
 465                         reg = <0x66010000 0x28>;
 466                         clocks = <&osc>;
 467                         #pwm-cells = <3>;
 468                         status = "disabled";
 469                 };
 470
 471                 mdio_mux_iproc: mdio-mux@6602023c {
 472                         compatible = "brcm,mdio-mux-iproc";
 473                         reg = <0x6602023c 0x14>;
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476
 477                         mdio@0 {
 478                                 reg = <0x0>;
 479                                 #address-cells = <1>;
 480                                 #size-cells = <0>;
 481
 482                                 pci_phy0: pci-phy@0 {
 483                                         compatible = "brcm,ns2-pcie-phy";
 484                                         reg = <0x0>;
 485                                         #phy-cells = <0>;
 486                                         status = "disabled";
 487                                 };
 488                         };
 489
 490                         mdio@7 {
 491                                 reg = <0x7>;
 492                                 #address-cells = <1>;
 493                                 #size-cells = <0>;
 494
 495                                 pci_phy1: pci-phy@0 {
 496                                         compatible = "brcm,ns2-pcie-phy";
 497                                         reg = <0x0>;
 498                                         #phy-cells = <0>;
 499                                         status = "disabled";
 500                                 };
 501                         };
 502
 503                         mdio@10 {
 504                                 reg = <0x10>;
 505                                 #address-cells = <1>;
 506                                 #size-cells = <0>;
 507                         };
 508                 };
 509
 510                 timer0: timer@66030000 {
 511                         compatible = "arm,sp804", "arm,primecell";
 512                         reg = <0x66030000 0x1000>;
 513                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
 514                         clocks = <&iprocslow>,
 515                                  <&iprocslow>,
 516                                  <&iprocslow>;
 517                         clock-names = "timer1", "timer2", "apb_pclk";
 518                 };
 519
 520                 timer1: timer@66040000 {
 521                         compatible = "arm,sp804", "arm,primecell";
 522                         reg = <0x66040000 0x1000>;
 523                         interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&iprocslow>,
 525                                  <&iprocslow>,
 526                                  <&iprocslow>;
 527                         clock-names = "timer1", "timer2", "apb_pclk";
 528                 };
 529
 530                 timer2: timer@66050000 {
 531                         compatible = "arm,sp804", "arm,primecell";
 532                         reg = <0x66050000 0x1000>;
 533                         interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&iprocslow>,
 535                                  <&iprocslow>,
 536                                  <&iprocslow>;
 537                         clock-names = "timer1", "timer2", "apb_pclk";
 538                 };
 539
 540                 timer3: timer@66060000 {
 541                         compatible = "arm,sp804", "arm,primecell";
 542                         reg = <0x66060000 0x1000>;
 543                         interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&iprocslow>,
 545                                  <&iprocslow>,
 546                                  <&iprocslow>;
 547                         clock-names = "timer1", "timer2", "apb_pclk";
 548                 };
 549
 550                 i2c0: i2c@66080000 {
 551                         compatible = "brcm,iproc-i2c";
 552                         reg = <0x66080000 0x100>;
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
 556                         clock-frequency = <100000>;
 557                         status = "disabled";
 558                 };
 559
 560                 wdt0: watchdog@66090000 {
 561                         compatible = "arm,sp805", "arm,primecell";
 562                         reg = <0x66090000 0x1000>;
 563                         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&iprocslow>, <&iprocslow>;
 565                         clock-names = "wdogclk", "apb_pclk";
 566                 };
 567
 568                 gpio_g: gpio@660a0000 {
 569                         compatible = "brcm,iproc-gpio";
 570                         reg = <0x660a0000 0x50>;
 571                         ngpios = <32>;
 572                         #gpio-cells = <2>;
 573                         gpio-controller;
 574                         interrupt-controller;
 575                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
 576                 };
 577
 578                 i2c1: i2c@660b0000 {
 579                         compatible = "brcm,iproc-i2c";
 580                         reg = <0x660b0000 0x100>;
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583                         interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
 584                         clock-frequency = <100000>;
 585                         status = "disabled";
 586                 };
 587
 588                 uart0: serial@66100000 {
 589                         compatible = "snps,dw-apb-uart";
 590                         reg = <0x66100000 0x100>;
 591                         interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
 592                         clocks = <&iprocslow>;
 593                         reg-shift = <2>;
 594                         reg-io-width = <4>;
 595                         status = "disabled";
 596                 };
 597
 598                 uart1: serial@66110000 {
 599                         compatible = "snps,dw-apb-uart";
 600                         reg = <0x66110000 0x100>;
 601                         interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
 602                         clocks = <&iprocslow>;
 603                         reg-shift = <2>;
 604                         reg-io-width = <4>;
 605                         status = "disabled";
 606                 };
 607
 608                 uart2: serial@66120000 {
 609                         compatible = "snps,dw-apb-uart";
 610                         reg = <0x66120000 0x100>;
 611                         interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
 612                         clocks = <&iprocslow>;
 613                         reg-shift = <2>;
 614                         reg-io-width = <4>;
 615                         status = "disabled";
 616                 };
 617
 618                 uart3: serial@66130000 {
 619                         compatible = "snps,dw-apb-uart";
 620                         reg = <0x66130000 0x100>;
 621                         interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
 622                         reg-shift = <2>;
 623                         reg-io-width = <4>;
 624                         clocks = <&osc>;
 625                         status = "disabled";
 626                 };
 627
 628                 ssp0: ssp@66180000 {
 629                         compatible = "arm,pl022", "arm,primecell";
 630                         reg = <0x66180000 0x1000>;
 631                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 632                         clocks = <&iprocslow>, <&iprocslow>;
 633                         clock-names = "spiclk", "apb_pclk";
 634                         #address-cells = <1>;
 635                         #size-cells = <0>;
 636                         status = "disabled";
 637                 };
 638
 639                 ssp1: ssp@66190000 {
 640                         compatible = "arm,pl022", "arm,primecell";
 641                         reg = <0x66190000 0x1000>;
 642                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 643                         clocks = <&iprocslow>, <&iprocslow>;
 644                         clock-names = "spiclk", "apb_pclk";
 645                         #address-cells = <1>;
 646                         #size-cells = <0>;
 647                         status = "disabled";
 648                 };
 649
 650                 hwrng: hwrng@66220000 {
 651                         compatible = "brcm,iproc-rng200";
 652                         reg = <0x66220000 0x28>;
 653                 };
 654
 655                 sata_phy: sata_phy@663f0100 {
 656                         compatible = "brcm,iproc-ns2-sata-phy";
 657                         reg = <0x663f0100 0x1f00>,
 658                               <0x663f004c 0x10>;
 659                         reg-names = "phy", "phy-ctrl";
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662
 663                         sata_phy0: sata-phy@0 {
 664                                 reg = <0>;
 665                                 #phy-cells = <0>;
 666                                 status = "disabled";
 667                         };
 668
 669                         sata_phy1: sata-phy@1 {
 670                                 reg = <1>;
 671                                 #phy-cells = <0>;
 672                                 status = "disabled";
 673                         };
 674                 };
 675
 676                 sata: ahci@663f2000 {
 677                         compatible = "brcm,iproc-ahci", "generic-ahci";
 678                         reg = <0x663f2000 0x1000>;
 679                         dma-coherent;
 680                         reg-names = "ahci";
 681                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
 682                         #address-cells = <1>;
 683                         #size-cells = <0>;
 684                         status = "disabled";
 685
 686                         sata0: sata-port@0 {
 687                                 reg = <0>;
 688                                 phys = <&sata_phy0>;
 689                                 phy-names = "sata-phy";
 690                         };
 691
 692                         sata1: sata-port@1 {
 693                                 reg = <1>;
 694                                 phys = <&sata_phy1>;
 695                                 phy-names = "sata-phy";
 696                         };
 697                 };
 698
 699                 sdio0: sdhci@66420000 {
 700                         compatible = "brcm,sdhci-iproc-cygnus";
 701                         reg = <0x66420000 0x100>;
 702                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 703                         dma-coherent;
 704                         bus-width = <8>;
 705                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 706                         status = "disabled";
 707                 };
 708
 709                 sdio1: sdhci@66430000 {
 710                         compatible = "brcm,sdhci-iproc-cygnus";
 711                         reg = <0x66430000 0x100>;
 712                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 713                         dma-coherent;
 714                         bus-width = <8>;
 715                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 716                         status = "disabled";
 717                 };
 718
 719                 nand: nand@66460000 {
 720                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 721                         reg = <0x66460000 0x600>,
 722                               <0x67015408 0x600>,
 723                               <0x66460f00 0x20>;
 724                         reg-names = "nand", "iproc-idm", "iproc-ext";
 725                         interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 726
 727                         #address-cells = <1>;
 728                         #size-cells = <0>;
 729
 730                         brcm,nand-has-wp;
 731                 };
 732
 733                 qspi: spi@66470200 {
 734                         compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
 735                         reg = <0x66470200 0x184>,
 736                                 <0x66470000 0x124>,
 737                                 <0x67017408 0x004>,
 738                                 <0x664703a0 0x01c>;
 739                         reg-names = "mspi", "bspi", "intr_regs",
 740                                 "intr_status_reg";
 741                         interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
 742                         interrupt-names = "spi_l1_intr";
 743                         clocks = <&iprocmed>;
 744                         clock-names = "iprocmed";
 745                         num-cs = <2>;
 746                         #address-cells = <1>;
 747                         #size-cells = <0>;
 748                 };
 749
 750         };
 751 };