2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/assembler.h>
25 #include <asm/asm-offsets.h>
26 #include <asm/errno.h>
28 #include <asm/thread_info.h>
29 #include <asm/unistd.h>
30 #include <asm/unistd32.h>
41 .macro kernel_entry, el, regsize = 64
42 sub sp, sp, #S_FRAME_SIZE - S_LR // room for LR, SP, SPSR, ELR
44 mov w0, w0 // zero upper 32 bits of x0
63 get_thread_info tsk // Ensure MDSCR_EL1.SS is clear,
64 ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
65 disable_step_tsk x19, x20 // exceptions when scheduling.
67 add x21, sp, #S_FRAME_SIZE
71 stp lr, x21, [sp, #S_LR]
72 stp x22, x23, [sp, #S_PC]
75 * Set syscallno to -1 by default (overridden later if real syscall).
79 str x21, [sp, #S_SYSCALLNO]
83 * Registers that may be useful after this macro is invoked:
87 * x23 - aborted PSTATE
91 .macro kernel_exit, el, ret = 0
92 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
94 ldr x23, [sp, #S_SP] // load return stack pointer
97 ldr x1, [sp, #S_X1] // preserve x0 (syscall return)
102 pop x2, x3 // load the rest of the registers
106 msr elr_el1, x21 // set up the return data
121 ldr lr, [sp], #S_FRAME_SIZE - S_LR // load LR and restore SP
122 eret // return to kernel
125 .macro get_thread_info, rd
127 and \rd, \rd, #~(THREAD_SIZE - 1) // top of stack
131 * These are the registers used in the syscall handler, and allow us to
132 * have in theory up to 7 arguments to a function - x0 to x6.
134 * x7 is reserved for the system call number in 32-bit mode.
136 sc_nr .req x25 // number of system calls
137 scno .req x26 // syscall number
138 stbl .req x27 // syscall table pointer
139 tsk .req x28 // current thread_info
142 * Interrupt handling.
145 ldr x1, handle_arch_irq
158 ventry el1_sync_invalid // Synchronous EL1t
159 ventry el1_irq_invalid // IRQ EL1t
160 ventry el1_fiq_invalid // FIQ EL1t
161 ventry el1_error_invalid // Error EL1t
163 ventry el1_sync // Synchronous EL1h
164 ventry el1_irq // IRQ EL1h
165 ventry el1_fiq_invalid // FIQ EL1h
166 ventry el1_error_invalid // Error EL1h
168 ventry el0_sync // Synchronous 64-bit EL0
169 ventry el0_irq // IRQ 64-bit EL0
170 ventry el0_fiq_invalid // FIQ 64-bit EL0
171 ventry el0_error_invalid // Error 64-bit EL0
174 ventry el0_sync_compat // Synchronous 32-bit EL0
175 ventry el0_irq_compat // IRQ 32-bit EL0
176 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
177 ventry el0_error_invalid_compat // Error 32-bit EL0
179 ventry el0_sync_invalid // Synchronous 32-bit EL0
180 ventry el0_irq_invalid // IRQ 32-bit EL0
181 ventry el0_fiq_invalid // FIQ 32-bit EL0
182 ventry el0_error_invalid // Error 32-bit EL0
187 * Invalid mode handlers
189 .macro inv_entry, el, reason, regsize = 64
190 kernel_entry el, \regsize
198 inv_entry 0, BAD_SYNC
199 ENDPROC(el0_sync_invalid)
203 ENDPROC(el0_irq_invalid)
207 ENDPROC(el0_fiq_invalid)
210 inv_entry 0, BAD_ERROR
211 ENDPROC(el0_error_invalid)
214 el0_fiq_invalid_compat:
215 inv_entry 0, BAD_FIQ, 32
216 ENDPROC(el0_fiq_invalid_compat)
218 el0_error_invalid_compat:
219 inv_entry 0, BAD_ERROR, 32
220 ENDPROC(el0_error_invalid_compat)
224 inv_entry 1, BAD_SYNC
225 ENDPROC(el1_sync_invalid)
229 ENDPROC(el1_irq_invalid)
233 ENDPROC(el1_fiq_invalid)
236 inv_entry 1, BAD_ERROR
237 ENDPROC(el1_error_invalid)
245 mrs x1, esr_el1 // read the syndrome register
246 lsr x24, x1, #ESR_EL1_EC_SHIFT // exception class
247 cmp x24, #ESR_EL1_EC_DABT_EL1 // data abort in EL1
249 cmp x24, #ESR_EL1_EC_SYS64 // configurable trap
251 cmp x24, #ESR_EL1_EC_SP_ALIGN // stack alignment exception
253 cmp x24, #ESR_EL1_EC_PC_ALIGN // pc alignment exception
255 cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL1
257 cmp x24, #ESR_EL1_EC_BREAKPT_EL1 // debug exception in EL1
262 * Data abort handling
266 // re-enable interrupts if they were enabled in the aborted context
267 tbnz x23, #7, 1f // PSR_I_BIT
270 mov x2, sp // struct pt_regs
273 // disable interrupts before pulling preserved data off the stack
278 * Stack or PC alignment exception handling
286 * Undefined instruction
293 * Debug exception handling
295 cmp x24, #ESR_EL1_EC_BRK64 // if BRK64
296 cinc x24, x24, eq // set bit '0'
297 tbz x24, #0, el1_inv // EL1 only
299 mov x2, sp // struct pt_regs
300 bl do_debug_exception
304 // TODO: add support for undefined instructions in kernel mode
316 #ifdef CONFIG_TRACE_IRQFLAGS
317 bl trace_hardirqs_off
322 #ifdef CONFIG_PREEMPT
324 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
325 cbnz w24, 1f // preempt count != 0
326 ldr x0, [tsk, #TI_FLAGS] // get flags
327 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
331 #ifdef CONFIG_TRACE_IRQFLAGS
337 #ifdef CONFIG_PREEMPT
340 1: bl preempt_schedule_irq // irq en/disable is done inside
341 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
342 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
352 mrs x25, esr_el1 // read the syndrome register
353 lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
354 cmp x24, #ESR_EL1_EC_SVC64 // SVC in 64-bit state
356 cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
358 cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
360 cmp x24, #ESR_EL1_EC_FP_ASIMD // FP/ASIMD access
362 cmp x24, #ESR_EL1_EC_FP_EXC64 // FP/ASIMD exception
364 cmp x24, #ESR_EL1_EC_SYS64 // configurable trap
366 cmp x24, #ESR_EL1_EC_SP_ALIGN // stack alignment exception
368 cmp x24, #ESR_EL1_EC_PC_ALIGN // pc alignment exception
370 cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL0
372 cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
380 mrs x25, esr_el1 // read the syndrome register
381 lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
382 cmp x24, #ESR_EL1_EC_SVC32 // SVC in 32-bit state
384 cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
386 cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
388 cmp x24, #ESR_EL1_EC_FP_ASIMD // FP/ASIMD access
390 cmp x24, #ESR_EL1_EC_FP_EXC32 // FP/ASIMD exception
392 cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL0
394 cmp x24, #ESR_EL1_EC_CP15_32 // CP15 MRC/MCR trap
396 cmp x24, #ESR_EL1_EC_CP15_64 // CP15 MRRC/MCRR trap
398 cmp x24, #ESR_EL1_EC_CP14_MR // CP14 MRC/MCR trap
400 cmp x24, #ESR_EL1_EC_CP14_LS // CP14 LDC/STC trap
402 cmp x24, #ESR_EL1_EC_CP14_64 // CP14 MRRC/MCRR trap
404 cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
409 * AArch32 syscall handling
411 adr stbl, compat_sys_call_table // load compat syscall table pointer
412 uxtw scno, w7 // syscall number in w7 (r7)
413 mov sc_nr, #__NR_compat_syscalls
424 * Data abort handling
427 // enable interrupts before calling the main handler
429 bic x0, x26, #(0xff << 56)
436 * Instruction abort handling
439 // enable interrupts before calling the main handler
442 orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts
448 * Floating Point or Advanced SIMD access
457 * Floating Point or Advanced SIMD exception
466 * Stack or PC alignment exception handling
469 // enable interrupts before calling the main handler
478 * Undefined instruction
480 // enable interrupts before calling the main handler
487 * Debug exception handling
489 tbnz x24, #0, el0_inv // EL0 only
493 bl do_debug_exception
510 #ifdef CONFIG_TRACE_IRQFLAGS
511 bl trace_hardirqs_off
516 #ifdef CONFIG_TRACE_IRQFLAGS
523 * Register switch for AArch64. The callee-saved registers need to be saved
524 * and restored. On entry:
525 * x0 = previous task_struct (must be preserved across the switch)
526 * x1 = next task_struct
527 * Previous and next are guaranteed not to be the same.
531 add x8, x0, #THREAD_CPU_CONTEXT
533 stp x19, x20, [x8], #16 // store callee-saved registers
534 stp x21, x22, [x8], #16
535 stp x23, x24, [x8], #16
536 stp x25, x26, [x8], #16
537 stp x27, x28, [x8], #16
538 stp x29, x9, [x8], #16
540 add x8, x1, #THREAD_CPU_CONTEXT
541 ldp x19, x20, [x8], #16 // restore callee-saved registers
542 ldp x21, x22, [x8], #16
543 ldp x23, x24, [x8], #16
544 ldp x25, x26, [x8], #16
545 ldp x27, x28, [x8], #16
546 ldp x29, x9, [x8], #16
550 ENDPROC(cpu_switch_to)
553 * This is the fast syscall return path. We do as little as possible here,
554 * and this includes saving x0 back into the kernel stack.
557 disable_irq // disable interrupts
558 ldr x1, [tsk, #TI_FLAGS]
559 and x2, x1, #_TIF_WORK_MASK
560 cbnz x2, fast_work_pending
561 enable_step_tsk x1, x2
562 kernel_exit 0, ret = 1
565 * Ok, we need to do extra processing, enter the slow path.
568 str x0, [sp, #S_X0] // returned x0
570 tbnz x1, #TIF_NEED_RESCHED, work_resched
571 /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */
572 ldr x2, [sp, #S_PSTATE]
574 tst x2, #PSR_MODE_MASK // user mode regs?
575 b.ne no_work_pending // returning to kernel
576 enable_irq // enable interrupts for do_notify_resume()
583 * "slow" syscall return path.
586 disable_irq // disable interrupts
587 ldr x1, [tsk, #TI_FLAGS]
588 and x2, x1, #_TIF_WORK_MASK
589 cbnz x2, work_pending
590 enable_step_tsk x1, x2
592 kernel_exit 0, ret = 0
596 * This is how we return from a fork.
600 cbz x19, 1f // not a kernel thread
603 1: get_thread_info tsk
605 ENDPROC(ret_from_fork)
612 adrp stbl, sys_call_table // load syscall table pointer
613 uxtw scno, w8 // syscall number in w8
614 mov sc_nr, #__NR_syscalls
615 el0_svc_naked: // compat entry point
616 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
619 ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks
620 tst x16, #_TIF_SYSCALL_WORK
622 adr lr, ret_fast_syscall // return address
623 cmp scno, sc_nr // check upper syscall limit
625 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
626 br x16 // call sys_* routine
633 * This is the really slow path. We're going to be doing context
634 * switches, and waiting for our parent to respond.
638 bl syscall_trace_enter
639 adr lr, __sys_trace_return // return address
640 uxtw scno, w0 // syscall number (possibly new)
641 mov x1, sp // pointer to regs
642 cmp scno, sc_nr // check upper syscall limit
644 ldp x0, x1, [sp] // restore the syscall args
645 ldp x2, x3, [sp, #S_X2]
646 ldp x4, x5, [sp, #S_X4]
647 ldp x6, x7, [sp, #S_X6]
648 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
649 br x16 // call sys_* routine
652 str x0, [sp] // save returned x0
654 bl syscall_trace_exit
658 * Special system call wrappers.
660 ENTRY(sys_rt_sigreturn_wrapper)
663 ENDPROC(sys_rt_sigreturn_wrapper)
665 ENTRY(handle_arch_irq)