arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/mm.h>
  25 #include <linux/uaccess.h>
  26
  27 #include <asm/cacheflush.h>
  28 #include <asm/cputype.h>
  29 #include <asm/debug-monitors.h>
  30 #include <asm/esr.h>
  31 #include <asm/kvm_arm.h>
  32 #include <asm/kvm_coproc.h>
  33 #include <asm/kvm_emulate.h>
  34 #include <asm/kvm_host.h>
  35 #include <asm/kvm_mmu.h>
  36
  37 #include <trace/events/kvm.h>
  38
  39 #include "sys_regs.h"
  40
  41 /*
  42  * All of this file is extremly similar to the ARM coproc.c, but the
  43  * types are different. My gut feeling is that it should be pretty
  44  * easy to merge, but that would be an ABI breakage -- again. VFP
  45  * would also need to be abstracted.
  46  *
  47  * For AArch32, we only take care of what is being trapped. Anything
  48  * that has to do with init and userspace access has to go via the
  49  * 64bit interface.
  50  */
  51
  52 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  53 static u32 cache_levels;
  54
  55 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  56 #define CSSELR_MAX 12
  57
  58 /* Which cache CCSIDR represents depends on CSSELR value. */
  59 static u32 get_ccsidr(u32 csselr)
  60 {
  61         u32 ccsidr;
  62
  63         /* Make sure noone else changes CSSELR during this! */
  64         local_irq_disable();
  65         /* Put value into CSSELR */
  66         asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
  67         isb();
  68         /* Read result out of CCSIDR */
  69         asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
  70         local_irq_enable();
  71
  72         return ccsidr;
  73 }
  74
  75 static void do_dc_cisw(u32 val)
  76 {
  77         asm volatile("dc cisw, %x0" : : "r" (val));
  78         dsb(ish);
  79 }
  80
  81 static void do_dc_csw(u32 val)
  82 {
  83         asm volatile("dc csw, %x0" : : "r" (val));
  84         dsb(ish);
  85 }
  86
  87 /* See note at ARM ARM B1.14.4 */
  88 static bool access_dcsw(struct kvm_vcpu *vcpu,
  89                         const struct sys_reg_params *p,
  90                         const struct sys_reg_desc *r)
  91 {
  92         unsigned long val;
  93         int cpu;
  94
  95         if (!p->is_write)
  96                 return read_from_write_only(vcpu, p);
  97
  98         cpu = get_cpu();
  99
 100         cpumask_setall(&vcpu->arch.require_dcache_flush);
 101         cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
 102
 103         /* If we were already preempted, take the long way around */
 104         if (cpu != vcpu->arch.last_pcpu) {
 105                 flush_cache_all();
 106                 goto done;
 107         }
 108
 109         val = *vcpu_reg(vcpu, p->Rt);
 110
 111         switch (p->CRm) {
 112         case 6:                 /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
 113         case 14:                /* DCCISW */
 114                 do_dc_cisw(val);
 115                 break;
 116
 117         case 10:                /* DCCSW */
 118                 do_dc_csw(val);
 119                 break;
 120         }
 121
 122 done:
 123         put_cpu();
 124
 125         return true;
 126 }
 127
 128 /*
 129  * Generic accessor for VM registers. Only called as long as HCR_TVM
 130  * is set.
 131  */
 132 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 133                           const struct sys_reg_params *p,
 134                           const struct sys_reg_desc *r)
 135 {
 136         unsigned long val;
 137
 138         BUG_ON(!p->is_write);
 139
 140         val = *vcpu_reg(vcpu, p->Rt);
 141         if (!p->is_aarch32) {
 142                 vcpu_sys_reg(vcpu, r->reg) = val;
 143         } else {
 144                 if (!p->is_32bit)
 145                         vcpu_cp15_64_high(vcpu, r->reg) = val >> 32;
 146                 vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL;
 147         }
 148
 149         return true;
 150 }
 151
 152 /*
 153  * SCTLR_EL1 accessor. Only called as long as HCR_TVM is set.  If the
 154  * guest enables the MMU, we stop trapping the VM sys_regs and leave
 155  * it in complete control of the caches.
 156  */
 157 static bool access_sctlr(struct kvm_vcpu *vcpu,
 158                          const struct sys_reg_params *p,
 159                          const struct sys_reg_desc *r)
 160 {
 161         access_vm_reg(vcpu, p, r);
 162
 163         if (vcpu_has_cache_enabled(vcpu)) {     /* MMU+Caches enabled? */
 164                 vcpu->arch.hcr_el2 &= ~HCR_TVM;
 165                 stage2_flush_vm(vcpu->kvm);
 166         }
 167
 168         return true;
 169 }
 170
 171 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 172                         const struct sys_reg_params *p,
 173                         const struct sys_reg_desc *r)
 174 {
 175         if (p->is_write)
 176                 return ignore_write(vcpu, p);
 177         else
 178                 return read_zero(vcpu, p);
 179 }
 180
 181 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 182                            const struct sys_reg_params *p,
 183                            const struct sys_reg_desc *r)
 184 {
 185         if (p->is_write) {
 186                 return ignore_write(vcpu, p);
 187         } else {
 188                 *vcpu_reg(vcpu, p->Rt) = (1 << 3);
 189                 return true;
 190         }
 191 }
 192
 193 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 194                                    const struct sys_reg_params *p,
 195                                    const struct sys_reg_desc *r)
 196 {
 197         if (p->is_write) {
 198                 return ignore_write(vcpu, p);
 199         } else {
 200                 u32 val;
 201                 asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
 202                 *vcpu_reg(vcpu, p->Rt) = val;
 203                 return true;
 204         }
 205 }
 206
 207 /*
 208  * We want to avoid world-switching all the DBG registers all the
 209  * time:
 210  *
 211  * - If we've touched any debug register, it is likely that we're
 212  *   going to touch more of them. It then makes sense to disable the
 213  *   traps and start doing the save/restore dance
 214  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 215  *   then mandatory to save/restore the registers, as the guest
 216  *   depends on them.
 217  *
 218  * For this, we use a DIRTY bit, indicating the guest has modified the
 219  * debug registers, used as follow:
 220  *
 221  * On guest entry:
 222  * - If the dirty bit is set (because we're coming back from trapping),
 223  *   disable the traps, save host registers, restore guest registers.
 224  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 225  *   set the dirty bit, disable the traps, save host registers,
 226  *   restore guest registers.
 227  * - Otherwise, enable the traps
 228  *
 229  * On guest exit:
 230  * - If the dirty bit is set, save guest registers, restore host
 231  *   registers and clear the dirty bit. This ensure that the host can
 232  *   now use the debug registers.
 233  */
 234 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 235                             const struct sys_reg_params *p,
 236                             const struct sys_reg_desc *r)
 237 {
 238         if (p->is_write) {
 239                 vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
 240                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 241         } else {
 242                 *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
 243         }
 244
 245         return true;
 246 }
 247
 248 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 249 {
 250         u64 amair;
 251
 252         asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
 253         vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
 254 }
 255
 256 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 257 {
 258         /*
 259          * Simply map the vcpu_id into the Aff0 field of the MPIDR.
 260          */
 261         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
 262 }
 263
 264 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 265 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 266         /* DBGBVRn_EL1 */                                               \
 267         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100),     \
 268           trap_debug_regs, reset_val, (DBGBVR0_EL1 + (n)), 0 },         \
 269         /* DBGBCRn_EL1 */                                               \
 270         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101),     \
 271           trap_debug_regs, reset_val, (DBGBCR0_EL1 + (n)), 0 },         \
 272         /* DBGWVRn_EL1 */                                               \
 273         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110),     \
 274           trap_debug_regs, reset_val, (DBGWVR0_EL1 + (n)), 0 },         \
 275         /* DBGWCRn_EL1 */                                               \
 276         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),     \
 277           trap_debug_regs, reset_val, (DBGWCR0_EL1 + (n)), 0 }
 278
 279 /*
 280  * Architected system registers.
 281  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 282  *
 283  * We could trap ID_DFR0 and tell the guest we don't support performance
 284  * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 285  * NAKed, so it will read the PMCR anyway.
 286  *
 287  * Therefore we tell the guest we have 0 counters.  Unfortunately, we
 288  * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
 289  * all PM registers, which doesn't crash the guest kernel at least.
 290  *
 291  * Debug handling: We do trap most, if not all debug related system
 292  * registers. The implementation is good enough to ensure that a guest
 293  * can use these with minimal performance degradation. The drawback is
 294  * that we don't implement any of the external debug, none of the
 295  * OSlock protocol. This should be revisited if we ever encounter a
 296  * more demanding guest...
 297  */
 298 static const struct sys_reg_desc sys_reg_descs[] = {
 299         /* DC ISW */
 300         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
 301           access_dcsw },
 302         /* DC CSW */
 303         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
 304           access_dcsw },
 305         /* DC CISW */
 306         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 307           access_dcsw },
 308
 309         DBG_BCR_BVR_WCR_WVR_EL1(0),
 310         DBG_BCR_BVR_WCR_WVR_EL1(1),
 311         /* MDCCINT_EL1 */
 312         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
 313           trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
 314         /* MDSCR_EL1 */
 315         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
 316           trap_debug_regs, reset_val, MDSCR_EL1, 0 },
 317         DBG_BCR_BVR_WCR_WVR_EL1(2),
 318         DBG_BCR_BVR_WCR_WVR_EL1(3),
 319         DBG_BCR_BVR_WCR_WVR_EL1(4),
 320         DBG_BCR_BVR_WCR_WVR_EL1(5),
 321         DBG_BCR_BVR_WCR_WVR_EL1(6),
 322         DBG_BCR_BVR_WCR_WVR_EL1(7),
 323         DBG_BCR_BVR_WCR_WVR_EL1(8),
 324         DBG_BCR_BVR_WCR_WVR_EL1(9),
 325         DBG_BCR_BVR_WCR_WVR_EL1(10),
 326         DBG_BCR_BVR_WCR_WVR_EL1(11),
 327         DBG_BCR_BVR_WCR_WVR_EL1(12),
 328         DBG_BCR_BVR_WCR_WVR_EL1(13),
 329         DBG_BCR_BVR_WCR_WVR_EL1(14),
 330         DBG_BCR_BVR_WCR_WVR_EL1(15),
 331
 332         /* MDRAR_EL1 */
 333         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 334           trap_raz_wi },
 335         /* OSLAR_EL1 */
 336         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
 337           trap_raz_wi },
 338         /* OSLSR_EL1 */
 339         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
 340           trap_oslsr_el1 },
 341         /* OSDLR_EL1 */
 342         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
 343           trap_raz_wi },
 344         /* DBGPRCR_EL1 */
 345         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
 346           trap_raz_wi },
 347         /* DBGCLAIMSET_EL1 */
 348         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
 349           trap_raz_wi },
 350         /* DBGCLAIMCLR_EL1 */
 351         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
 352           trap_raz_wi },
 353         /* DBGAUTHSTATUS_EL1 */
 354         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
 355           trap_dbgauthstatus_el1 },
 356
 357         /* TEECR32_EL1 */
 358         { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 359           NULL, reset_val, TEECR32_EL1, 0 },
 360         /* TEEHBR32_EL1 */
 361         { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
 362           NULL, reset_val, TEEHBR32_EL1, 0 },
 363
 364         /* MDCCSR_EL1 */
 365         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
 366           trap_raz_wi },
 367         /* DBGDTR_EL0 */
 368         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
 369           trap_raz_wi },
 370         /* DBGDTR[TR]X_EL0 */
 371         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
 372           trap_raz_wi },
 373
 374         /* DBGVCR32_EL2 */
 375         { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
 376           NULL, reset_val, DBGVCR32_EL2, 0 },
 377
 378         /* MPIDR_EL1 */
 379         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 380           NULL, reset_mpidr, MPIDR_EL1 },
 381         /* SCTLR_EL1 */
 382         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 383           access_sctlr, reset_val, SCTLR_EL1, 0x00C50078 },
 384         /* CPACR_EL1 */
 385         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
 386           NULL, reset_val, CPACR_EL1, 0 },
 387         /* TTBR0_EL1 */
 388         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
 389           access_vm_reg, reset_unknown, TTBR0_EL1 },
 390         /* TTBR1_EL1 */
 391         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
 392           access_vm_reg, reset_unknown, TTBR1_EL1 },
 393         /* TCR_EL1 */
 394         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
 395           access_vm_reg, reset_val, TCR_EL1, 0 },
 396
 397         /* AFSR0_EL1 */
 398         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
 399           access_vm_reg, reset_unknown, AFSR0_EL1 },
 400         /* AFSR1_EL1 */
 401         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
 402           access_vm_reg, reset_unknown, AFSR1_EL1 },
 403         /* ESR_EL1 */
 404         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
 405           access_vm_reg, reset_unknown, ESR_EL1 },
 406         /* FAR_EL1 */
 407         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
 408           access_vm_reg, reset_unknown, FAR_EL1 },
 409         /* PAR_EL1 */
 410         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
 411           NULL, reset_unknown, PAR_EL1 },
 412
 413         /* PMINTENSET_EL1 */
 414         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
 415           trap_raz_wi },
 416         /* PMINTENCLR_EL1 */
 417         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
 418           trap_raz_wi },
 419
 420         /* MAIR_EL1 */
 421         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
 422           access_vm_reg, reset_unknown, MAIR_EL1 },
 423         /* AMAIR_EL1 */
 424         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
 425           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 426
 427         /* VBAR_EL1 */
 428         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
 429           NULL, reset_val, VBAR_EL1, 0 },
 430
 431         /* ICC_SRE_EL1 */
 432         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
 433           trap_raz_wi },
 434
 435         /* CONTEXTIDR_EL1 */
 436         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
 437           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 438         /* TPIDR_EL1 */
 439         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
 440           NULL, reset_unknown, TPIDR_EL1 },
 441
 442         /* CNTKCTL_EL1 */
 443         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
 444           NULL, reset_val, CNTKCTL_EL1, 0},
 445
 446         /* CSSELR_EL1 */
 447         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 448           NULL, reset_unknown, CSSELR_EL1 },
 449
 450         /* PMCR_EL0 */
 451         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
 452           trap_raz_wi },
 453         /* PMCNTENSET_EL0 */
 454         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
 455           trap_raz_wi },
 456         /* PMCNTENCLR_EL0 */
 457         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
 458           trap_raz_wi },
 459         /* PMOVSCLR_EL0 */
 460         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
 461           trap_raz_wi },
 462         /* PMSWINC_EL0 */
 463         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
 464           trap_raz_wi },
 465         /* PMSELR_EL0 */
 466         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
 467           trap_raz_wi },
 468         /* PMCEID0_EL0 */
 469         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 470           trap_raz_wi },
 471         /* PMCEID1_EL0 */
 472         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
 473           trap_raz_wi },
 474         /* PMCCNTR_EL0 */
 475         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
 476           trap_raz_wi },
 477         /* PMXEVTYPER_EL0 */
 478         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
 479           trap_raz_wi },
 480         /* PMXEVCNTR_EL0 */
 481         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
 482           trap_raz_wi },
 483         /* PMUSERENR_EL0 */
 484         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
 485           trap_raz_wi },
 486         /* PMOVSSET_EL0 */
 487         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
 488           trap_raz_wi },
 489
 490         /* TPIDR_EL0 */
 491         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
 492           NULL, reset_unknown, TPIDR_EL0 },
 493         /* TPIDRRO_EL0 */
 494         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
 495           NULL, reset_unknown, TPIDRRO_EL0 },
 496
 497         /* DACR32_EL2 */
 498         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
 499           NULL, reset_unknown, DACR32_EL2 },
 500         /* IFSR32_EL2 */
 501         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
 502           NULL, reset_unknown, IFSR32_EL2 },
 503         /* FPEXC32_EL2 */
 504         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
 505           NULL, reset_val, FPEXC32_EL2, 0x70 },
 506 };
 507
 508 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
 509                         const struct sys_reg_params *p,
 510                         const struct sys_reg_desc *r)
 511 {
 512         if (p->is_write) {
 513                 return ignore_write(vcpu, p);
 514         } else {
 515                 u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
 516                 u64 pfr = read_cpuid(ID_AA64PFR0_EL1);
 517                 u32 el3 = !!((pfr >> 12) & 0xf);
 518
 519                 *vcpu_reg(vcpu, p->Rt) = ((((dfr >> 20) & 0xf) << 28) |
 520                                           (((dfr >> 12) & 0xf) << 24) |
 521                                           (((dfr >> 28) & 0xf) << 20) |
 522                                           (6 << 16) | (el3 << 14) | (el3 << 12));
 523                 return true;
 524         }
 525 }
 526
 527 static bool trap_debug32(struct kvm_vcpu *vcpu,
 528                          const struct sys_reg_params *p,
 529                          const struct sys_reg_desc *r)
 530 {
 531         if (p->is_write) {
 532                 vcpu_cp14(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
 533                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 534         } else {
 535                 *vcpu_reg(vcpu, p->Rt) = vcpu_cp14(vcpu, r->reg);
 536         }
 537
 538         return true;
 539 }
 540
 541 #define DBG_BCR_BVR_WCR_WVR(n)                                  \
 542         /* DBGBVRn */                                           \
 543         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_debug32,    \
 544           NULL, (cp14_DBGBVR0 + (n) * 2) },                     \
 545         /* DBGBCRn */                                           \
 546         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_debug32,    \
 547           NULL, (cp14_DBGBCR0 + (n) * 2) },                     \
 548         /* DBGWVRn */                                           \
 549         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_debug32,    \
 550           NULL, (cp14_DBGWVR0 + (n) * 2) },                     \
 551         /* DBGWCRn */                                           \
 552         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_debug32,    \
 553           NULL, (cp14_DBGWCR0 + (n) * 2) }
 554
 555 #define DBGBXVR(n)                                              \
 556         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_debug32,    \
 557           NULL, cp14_DBGBXVR0 + n * 2 }
 558
 559 /*
 560  * Trapped cp14 registers. We generally ignore most of the external
 561  * debug, on the principle that they don't really make sense to a
 562  * guest. Revisit this one day, whould this principle change.
 563  */
 564 static const struct sys_reg_desc cp14_regs[] = {
 565         /* DBGIDR */
 566         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
 567         /* DBGDTRRXext */
 568         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
 569
 570         DBG_BCR_BVR_WCR_WVR(0),
 571         /* DBGDSCRint */
 572         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
 573         DBG_BCR_BVR_WCR_WVR(1),
 574         /* DBGDCCINT */
 575         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
 576         /* DBGDSCRext */
 577         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
 578         DBG_BCR_BVR_WCR_WVR(2),
 579         /* DBGDTR[RT]Xint */
 580         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
 581         /* DBGDTR[RT]Xext */
 582         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
 583         DBG_BCR_BVR_WCR_WVR(3),
 584         DBG_BCR_BVR_WCR_WVR(4),
 585         DBG_BCR_BVR_WCR_WVR(5),
 586         /* DBGWFAR */
 587         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
 588         /* DBGOSECCR */
 589         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
 590         DBG_BCR_BVR_WCR_WVR(6),
 591         /* DBGVCR */
 592         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
 593         DBG_BCR_BVR_WCR_WVR(7),
 594         DBG_BCR_BVR_WCR_WVR(8),
 595         DBG_BCR_BVR_WCR_WVR(9),
 596         DBG_BCR_BVR_WCR_WVR(10),
 597         DBG_BCR_BVR_WCR_WVR(11),
 598         DBG_BCR_BVR_WCR_WVR(12),
 599         DBG_BCR_BVR_WCR_WVR(13),
 600         DBG_BCR_BVR_WCR_WVR(14),
 601         DBG_BCR_BVR_WCR_WVR(15),
 602
 603         /* DBGDRAR (32bit) */
 604         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
 605
 606         DBGBXVR(0),
 607         /* DBGOSLAR */
 608         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
 609         DBGBXVR(1),
 610         /* DBGOSLSR */
 611         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
 612         DBGBXVR(2),
 613         DBGBXVR(3),
 614         /* DBGOSDLR */
 615         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
 616         DBGBXVR(4),
 617         /* DBGPRCR */
 618         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
 619         DBGBXVR(5),
 620         DBGBXVR(6),
 621         DBGBXVR(7),
 622         DBGBXVR(8),
 623         DBGBXVR(9),
 624         DBGBXVR(10),
 625         DBGBXVR(11),
 626         DBGBXVR(12),
 627         DBGBXVR(13),
 628         DBGBXVR(14),
 629         DBGBXVR(15),
 630
 631         /* DBGDSAR (32bit) */
 632         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
 633
 634         /* DBGDEVID2 */
 635         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
 636         /* DBGDEVID1 */
 637         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
 638         /* DBGDEVID */
 639         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
 640         /* DBGCLAIMSET */
 641         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
 642         /* DBGCLAIMCLR */
 643         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
 644         /* DBGAUTHSTATUS */
 645         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
 646 };
 647
 648 /* Trapped cp14 64bit registers */
 649 static const struct sys_reg_desc cp14_64_regs[] = {
 650         /* DBGDRAR (64bit) */
 651         { Op1( 0), CRm( 1), .access = trap_raz_wi },
 652
 653         /* DBGDSAR (64bit) */
 654         { Op1( 0), CRm( 2), .access = trap_raz_wi },
 655 };
 656
 657 /*
 658  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
 659  * depending on the way they are accessed (as a 32bit or a 64bit
 660  * register).
 661  */
 662 static const struct sys_reg_desc cp15_regs[] = {
 663         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR },
 664         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 665         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
 666         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
 667         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
 668         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
 669         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
 670         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
 671         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
 672         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
 673         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
 674
 675         /*
 676          * DC{C,I,CI}SW operations:
 677          */
 678         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
 679         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
 680         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
 681
 682         /* PMU */
 683         { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
 684         { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 685         { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 686         { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
 687         { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
 688         { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 689         { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 690         { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
 691         { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
 692         { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
 693         { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
 694         { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
 695         { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
 696
 697         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
 698         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
 699         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
 700         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
 701
 702         /* ICC_SRE */
 703         { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
 704
 705         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
 706 };
 707
 708 static const struct sys_reg_desc cp15_64_regs[] = {
 709         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 710         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
 711 };
 712
 713 /* Target specific emulation tables */
 714 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
 715
 716 void kvm_register_target_sys_reg_table(unsigned int target,
 717                                        struct kvm_sys_reg_target_table *table)
 718 {
 719         target_tables[target] = table;
 720 }
 721
 722 /* Get specific register table for this target. */
 723 static const struct sys_reg_desc *get_target_table(unsigned target,
 724                                                    bool mode_is_64,
 725                                                    size_t *num)
 726 {
 727         struct kvm_sys_reg_target_table *table;
 728
 729         table = target_tables[target];
 730         if (mode_is_64) {
 731                 *num = table->table64.num;
 732                 return table->table64.table;
 733         } else {
 734                 *num = table->table32.num;
 735                 return table->table32.table;
 736         }
 737 }
 738
 739 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
 740                                          const struct sys_reg_desc table[],
 741                                          unsigned int num)
 742 {
 743         unsigned int i;
 744
 745         for (i = 0; i < num; i++) {
 746                 const struct sys_reg_desc *r = &table[i];
 747
 748                 if (params->Op0 != r->Op0)
 749                         continue;
 750                 if (params->Op1 != r->Op1)
 751                         continue;
 752                 if (params->CRn != r->CRn)
 753                         continue;
 754                 if (params->CRm != r->CRm)
 755                         continue;
 756                 if (params->Op2 != r->Op2)
 757                         continue;
 758
 759                 return r;
 760         }
 761         return NULL;
 762 }
 763
 764 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
 765 {
 766         kvm_inject_undefined(vcpu);
 767         return 1;
 768 }
 769
 770 /*
 771  * emulate_cp --  tries to match a sys_reg access in a handling table, and
 772  *                call the corresponding trap handler.
 773  *
 774  * @params: pointer to the descriptor of the access
 775  * @table: array of trap descriptors
 776  * @num: size of the trap descriptor array
 777  *
 778  * Return 0 if the access has been handled, and -1 if not.
 779  */
 780 static int emulate_cp(struct kvm_vcpu *vcpu,
 781                       const struct sys_reg_params *params,
 782                       const struct sys_reg_desc *table,
 783                       size_t num)
 784 {
 785         const struct sys_reg_desc *r;
 786
 787         if (!table)
 788                 return -1;      /* Not handled */
 789
 790         r = find_reg(params, table, num);
 791
 792         if (r) {
 793                 /*
 794                  * Not having an accessor means that we have
 795                  * configured a trap that we don't know how to
 796                  * handle. This certainly qualifies as a gross bug
 797                  * that should be fixed right away.
 798                  */
 799                 BUG_ON(!r->access);
 800
 801                 if (likely(r->access(vcpu, params, r))) {
 802                         /* Skip instruction, since it was emulated */
 803                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 804                 }
 805
 806                 /* Handled */
 807                 return 0;
 808         }
 809
 810         /* Not handled */
 811         return -1;
 812 }
 813
 814 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
 815                                 struct sys_reg_params *params)
 816 {
 817         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
 818         int cp;
 819
 820         switch(hsr_ec) {
 821         case ESR_ELx_EC_CP15_32:
 822         case ESR_ELx_EC_CP15_64:
 823                 cp = 15;
 824                 break;
 825         case ESR_ELx_EC_CP14_MR:
 826         case ESR_ELx_EC_CP14_64:
 827                 cp = 14;
 828                 break;
 829         default:
 830                 WARN_ON((cp = -1));
 831         }
 832
 833         kvm_err("Unsupported guest CP%d access at: %08lx\n",
 834                 cp, *vcpu_pc(vcpu));
 835         print_sys_reg_instr(params);
 836         kvm_inject_undefined(vcpu);
 837 }
 838
 839 /**
 840  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP15 access
 841  * @vcpu: The VCPU pointer
 842  * @run:  The kvm_run struct
 843  */
 844 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
 845                             const struct sys_reg_desc *global,
 846                             size_t nr_global,
 847                             const struct sys_reg_desc *target_specific,
 848                             size_t nr_specific)
 849 {
 850         struct sys_reg_params params;
 851         u32 hsr = kvm_vcpu_get_hsr(vcpu);
 852         int Rt2 = (hsr >> 10) & 0xf;
 853
 854         params.is_aarch32 = true;
 855         params.is_32bit = false;
 856         params.CRm = (hsr >> 1) & 0xf;
 857         params.Rt = (hsr >> 5) & 0xf;
 858         params.is_write = ((hsr & 1) == 0);
 859
 860         params.Op0 = 0;
 861         params.Op1 = (hsr >> 16) & 0xf;
 862         params.Op2 = 0;
 863         params.CRn = 0;
 864
 865         /*
 866          * Massive hack here. Store Rt2 in the top 32bits so we only
 867          * have one register to deal with. As we use the same trap
 868          * backends between AArch32 and AArch64, we get away with it.
 869          */
 870         if (params.is_write) {
 871                 u64 val = *vcpu_reg(vcpu, params.Rt);
 872                 val &= 0xffffffff;
 873                 val |= *vcpu_reg(vcpu, Rt2) << 32;
 874                 *vcpu_reg(vcpu, params.Rt) = val;
 875         }
 876
 877         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
 878                 goto out;
 879         if (!emulate_cp(vcpu, &params, global, nr_global))
 880                 goto out;
 881
 882         unhandled_cp_access(vcpu, &params);
 883
 884 out:
 885         /* Do the opposite hack for the read side */
 886         if (!params.is_write) {
 887                 u64 val = *vcpu_reg(vcpu, params.Rt);
 888                 val >>= 32;
 889                 *vcpu_reg(vcpu, Rt2) = val;
 890         }
 891
 892         return 1;
 893 }
 894
 895 /**
 896  * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
 897  * @vcpu: The VCPU pointer
 898  * @run:  The kvm_run struct
 899  */
 900 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
 901                             const struct sys_reg_desc *global,
 902                             size_t nr_global,
 903                             const struct sys_reg_desc *target_specific,
 904                             size_t nr_specific)
 905 {
 906         struct sys_reg_params params;
 907         u32 hsr = kvm_vcpu_get_hsr(vcpu);
 908
 909         params.is_aarch32 = true;
 910         params.is_32bit = true;
 911         params.CRm = (hsr >> 1) & 0xf;
 912         params.Rt  = (hsr >> 5) & 0xf;
 913         params.is_write = ((hsr & 1) == 0);
 914         params.CRn = (hsr >> 10) & 0xf;
 915         params.Op0 = 0;
 916         params.Op1 = (hsr >> 14) & 0x7;
 917         params.Op2 = (hsr >> 17) & 0x7;
 918
 919         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
 920                 return 1;
 921         if (!emulate_cp(vcpu, &params, global, nr_global))
 922                 return 1;
 923
 924         unhandled_cp_access(vcpu, &params);
 925         return 1;
 926 }
 927
 928 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 929 {
 930         const struct sys_reg_desc *target_specific;
 931         size_t num;
 932
 933         target_specific = get_target_table(vcpu->arch.target, false, &num);
 934         return kvm_handle_cp_64(vcpu,
 935                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
 936                                 target_specific, num);
 937 }
 938
 939 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 940 {
 941         const struct sys_reg_desc *target_specific;
 942         size_t num;
 943
 944         target_specific = get_target_table(vcpu->arch.target, false, &num);
 945         return kvm_handle_cp_32(vcpu,
 946                                 cp15_regs, ARRAY_SIZE(cp15_regs),
 947                                 target_specific, num);
 948 }
 949
 950 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 951 {
 952         return kvm_handle_cp_64(vcpu,
 953                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
 954                                 NULL, 0);
 955 }
 956
 957 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 958 {
 959         return kvm_handle_cp_32(vcpu,
 960                                 cp14_regs, ARRAY_SIZE(cp14_regs),
 961                                 NULL, 0);
 962 }
 963
 964 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
 965                            const struct sys_reg_params *params)
 966 {
 967         size_t num;
 968         const struct sys_reg_desc *table, *r;
 969
 970         table = get_target_table(vcpu->arch.target, true, &num);
 971
 972         /* Search target-specific then generic table. */
 973         r = find_reg(params, table, num);
 974         if (!r)
 975                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
 976
 977         if (likely(r)) {
 978                 /*
 979                  * Not having an accessor means that we have
 980                  * configured a trap that we don't know how to
 981                  * handle. This certainly qualifies as a gross bug
 982                  * that should be fixed right away.
 983                  */
 984                 BUG_ON(!r->access);
 985
 986                 if (likely(r->access(vcpu, params, r))) {
 987                         /* Skip instruction, since it was emulated */
 988                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 989                         return 1;
 990                 }
 991                 /* If access function fails, it should complain. */
 992         } else {
 993                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
 994                         *vcpu_pc(vcpu));
 995                 print_sys_reg_instr(params);
 996         }
 997         kvm_inject_undefined(vcpu);
 998         return 1;
 999 }
1000
1001 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1002                               const struct sys_reg_desc *table, size_t num)
1003 {
1004         unsigned long i;
1005
1006         for (i = 0; i < num; i++)
1007                 if (table[i].reset)
1008                         table[i].reset(vcpu, &table[i]);
1009 }
1010
1011 /**
1012  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1013  * @vcpu: The VCPU pointer
1014  * @run:  The kvm_run struct
1015  */
1016 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1017 {
1018         struct sys_reg_params params;
1019         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1020
1021         params.is_aarch32 = false;
1022         params.is_32bit = false;
1023         params.Op0 = (esr >> 20) & 3;
1024         params.Op1 = (esr >> 14) & 0x7;
1025         params.CRn = (esr >> 10) & 0xf;
1026         params.CRm = (esr >> 1) & 0xf;
1027         params.Op2 = (esr >> 17) & 0x7;
1028         params.Rt = (esr >> 5) & 0x1f;
1029         params.is_write = !(esr & 1);
1030
1031         return emulate_sys_reg(vcpu, &params);
1032 }
1033
1034 /******************************************************************************
1035  * Userspace API
1036  *****************************************************************************/
1037
1038 static bool index_to_params(u64 id, struct sys_reg_params *params)
1039 {
1040         switch (id & KVM_REG_SIZE_MASK) {
1041         case KVM_REG_SIZE_U64:
1042                 /* Any unused index bits means it's not valid. */
1043                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1044                               | KVM_REG_ARM_COPROC_MASK
1045                               | KVM_REG_ARM64_SYSREG_OP0_MASK
1046                               | KVM_REG_ARM64_SYSREG_OP1_MASK
1047                               | KVM_REG_ARM64_SYSREG_CRN_MASK
1048                               | KVM_REG_ARM64_SYSREG_CRM_MASK
1049                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
1050                         return false;
1051                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1052                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1053                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1054                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1055                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1056                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1057                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1058                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1059                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1060                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1061                 return true;
1062         default:
1063                 return false;
1064         }
1065 }
1066
1067 /* Decode an index value, and find the sys_reg_desc entry. */
1068 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1069                                                     u64 id)
1070 {
1071         size_t num;
1072         const struct sys_reg_desc *table, *r;
1073         struct sys_reg_params params;
1074
1075         /* We only do sys_reg for now. */
1076         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1077                 return NULL;
1078
1079         if (!index_to_params(id, &params))
1080                 return NULL;
1081
1082         table = get_target_table(vcpu->arch.target, true, &num);
1083         r = find_reg(&params, table, num);
1084         if (!r)
1085                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1086
1087         /* Not saved in the sys_reg array? */
1088         if (r && !r->reg)
1089                 r = NULL;
1090
1091         return r;
1092 }
1093
1094 /*
1095  * These are the invariant sys_reg registers: we let the guest see the
1096  * host versions of these, so they're part of the guest state.
1097  *
1098  * A future CPU may provide a mechanism to present different values to
1099  * the guest, or a future kvm may trap them.
1100  */
1101
1102 #define FUNCTION_INVARIANT(reg)                                         \
1103         static void get_##reg(struct kvm_vcpu *v,                       \
1104                               const struct sys_reg_desc *r)             \
1105         {                                                               \
1106                 u64 val;                                                \
1107                                                                         \
1108                 asm volatile("mrs %0, " __stringify(reg) "\n"           \
1109                              : "=r" (val));                             \
1110                 ((struct sys_reg_desc *)r)->val = val;                  \
1111         }
1112
1113 FUNCTION_INVARIANT(midr_el1)
1114 FUNCTION_INVARIANT(ctr_el0)
1115 FUNCTION_INVARIANT(revidr_el1)
1116 FUNCTION_INVARIANT(id_pfr0_el1)
1117 FUNCTION_INVARIANT(id_pfr1_el1)
1118 FUNCTION_INVARIANT(id_dfr0_el1)
1119 FUNCTION_INVARIANT(id_afr0_el1)
1120 FUNCTION_INVARIANT(id_mmfr0_el1)
1121 FUNCTION_INVARIANT(id_mmfr1_el1)
1122 FUNCTION_INVARIANT(id_mmfr2_el1)
1123 FUNCTION_INVARIANT(id_mmfr3_el1)
1124 FUNCTION_INVARIANT(id_isar0_el1)
1125 FUNCTION_INVARIANT(id_isar1_el1)
1126 FUNCTION_INVARIANT(id_isar2_el1)
1127 FUNCTION_INVARIANT(id_isar3_el1)
1128 FUNCTION_INVARIANT(id_isar4_el1)
1129 FUNCTION_INVARIANT(id_isar5_el1)
1130 FUNCTION_INVARIANT(clidr_el1)
1131 FUNCTION_INVARIANT(aidr_el1)
1132
1133 /* ->val is filled in by kvm_sys_reg_table_init() */
1134 static struct sys_reg_desc invariant_sys_regs[] = {
1135         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1136           NULL, get_midr_el1 },
1137         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1138           NULL, get_revidr_el1 },
1139         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1140           NULL, get_id_pfr0_el1 },
1141         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1142           NULL, get_id_pfr1_el1 },
1143         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1144           NULL, get_id_dfr0_el1 },
1145         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1146           NULL, get_id_afr0_el1 },
1147         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1148           NULL, get_id_mmfr0_el1 },
1149         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1150           NULL, get_id_mmfr1_el1 },
1151         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1152           NULL, get_id_mmfr2_el1 },
1153         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1154           NULL, get_id_mmfr3_el1 },
1155         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1156           NULL, get_id_isar0_el1 },
1157         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1158           NULL, get_id_isar1_el1 },
1159         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1160           NULL, get_id_isar2_el1 },
1161         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1162           NULL, get_id_isar3_el1 },
1163         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1164           NULL, get_id_isar4_el1 },
1165         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1166           NULL, get_id_isar5_el1 },
1167         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1168           NULL, get_clidr_el1 },
1169         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1170           NULL, get_aidr_el1 },
1171         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1172           NULL, get_ctr_el0 },
1173 };
1174
1175 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1176 {
1177         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1178                 return -EFAULT;
1179         return 0;
1180 }
1181
1182 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1183 {
1184         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1185                 return -EFAULT;
1186         return 0;
1187 }
1188
1189 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1190 {
1191         struct sys_reg_params params;
1192         const struct sys_reg_desc *r;
1193
1194         if (!index_to_params(id, &params))
1195                 return -ENOENT;
1196
1197         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1198         if (!r)
1199                 return -ENOENT;
1200
1201         return reg_to_user(uaddr, &r->val, id);
1202 }
1203
1204 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1205 {
1206         struct sys_reg_params params;
1207         const struct sys_reg_desc *r;
1208         int err;
1209         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1210
1211         if (!index_to_params(id, &params))
1212                 return -ENOENT;
1213         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1214         if (!r)
1215                 return -ENOENT;
1216
1217         err = reg_from_user(&val, uaddr, id);
1218         if (err)
1219                 return err;
1220
1221         /* This is what we mean by invariant: you can't change it. */
1222         if (r->val != val)
1223                 return -EINVAL;
1224
1225         return 0;
1226 }
1227
1228 static bool is_valid_cache(u32 val)
1229 {
1230         u32 level, ctype;
1231
1232         if (val >= CSSELR_MAX)
1233                 return false;
1234
1235         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1236         level = (val >> 1);
1237         ctype = (cache_levels >> (level * 3)) & 7;
1238
1239         switch (ctype) {
1240         case 0: /* No cache */
1241                 return false;
1242         case 1: /* Instruction cache only */
1243                 return (val & 1);
1244         case 2: /* Data cache only */
1245         case 4: /* Unified cache */
1246                 return !(val & 1);
1247         case 3: /* Separate instruction and data caches */
1248                 return true;
1249         default: /* Reserved: we can't know instruction or data. */
1250                 return false;
1251         }
1252 }
1253
1254 static int demux_c15_get(u64 id, void __user *uaddr)
1255 {
1256         u32 val;
1257         u32 __user *uval = uaddr;
1258
1259         /* Fail if we have unknown bits set. */
1260         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1261                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1262                 return -ENOENT;
1263
1264         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1265         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1266                 if (KVM_REG_SIZE(id) != 4)
1267                         return -ENOENT;
1268                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1269                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1270                 if (!is_valid_cache(val))
1271                         return -ENOENT;
1272
1273                 return put_user(get_ccsidr(val), uval);
1274         default:
1275                 return -ENOENT;
1276         }
1277 }
1278
1279 static int demux_c15_set(u64 id, void __user *uaddr)
1280 {
1281         u32 val, newval;
1282         u32 __user *uval = uaddr;
1283
1284         /* Fail if we have unknown bits set. */
1285         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1286                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1287                 return -ENOENT;
1288
1289         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1290         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1291                 if (KVM_REG_SIZE(id) != 4)
1292                         return -ENOENT;
1293                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1294                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1295                 if (!is_valid_cache(val))
1296                         return -ENOENT;
1297
1298                 if (get_user(newval, uval))
1299                         return -EFAULT;
1300
1301                 /* This is also invariant: you can't change it. */
1302                 if (newval != get_ccsidr(val))
1303                         return -EINVAL;
1304                 return 0;
1305         default:
1306                 return -ENOENT;
1307         }
1308 }
1309
1310 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1311 {
1312         const struct sys_reg_desc *r;
1313         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1314
1315         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1316                 return demux_c15_get(reg->id, uaddr);
1317
1318         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1319                 return -ENOENT;
1320
1321         r = index_to_sys_reg_desc(vcpu, reg->id);
1322         if (!r)
1323                 return get_invariant_sys_reg(reg->id, uaddr);
1324
1325         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
1326 }
1327
1328 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1329 {
1330         const struct sys_reg_desc *r;
1331         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1332
1333         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1334                 return demux_c15_set(reg->id, uaddr);
1335
1336         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1337                 return -ENOENT;
1338
1339         r = index_to_sys_reg_desc(vcpu, reg->id);
1340         if (!r)
1341                 return set_invariant_sys_reg(reg->id, uaddr);
1342
1343         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
1344 }
1345
1346 static unsigned int num_demux_regs(void)
1347 {
1348         unsigned int i, count = 0;
1349
1350         for (i = 0; i < CSSELR_MAX; i++)
1351                 if (is_valid_cache(i))
1352                         count++;
1353
1354         return count;
1355 }
1356
1357 static int write_demux_regids(u64 __user *uindices)
1358 {
1359         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1360         unsigned int i;
1361
1362         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1363         for (i = 0; i < CSSELR_MAX; i++) {
1364                 if (!is_valid_cache(i))
1365                         continue;
1366                 if (put_user(val | i, uindices))
1367                         return -EFAULT;
1368                 uindices++;
1369         }
1370         return 0;
1371 }
1372
1373 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
1374 {
1375         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
1376                 KVM_REG_ARM64_SYSREG |
1377                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
1378                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
1379                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
1380                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
1381                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
1382 }
1383
1384 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
1385 {
1386         if (!*uind)
1387                 return true;
1388
1389         if (put_user(sys_reg_to_index(reg), *uind))
1390                 return false;
1391
1392         (*uind)++;
1393         return true;
1394 }
1395
1396 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
1397 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
1398 {
1399         const struct sys_reg_desc *i1, *i2, *end1, *end2;
1400         unsigned int total = 0;
1401         size_t num;
1402
1403         /* We check for duplicates here, to allow arch-specific overrides. */
1404         i1 = get_target_table(vcpu->arch.target, true, &num);
1405         end1 = i1 + num;
1406         i2 = sys_reg_descs;
1407         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
1408
1409         BUG_ON(i1 == end1 || i2 == end2);
1410
1411         /* Walk carefully, as both tables may refer to the same register. */
1412         while (i1 || i2) {
1413                 int cmp = cmp_sys_reg(i1, i2);
1414                 /* target-specific overrides generic entry. */
1415                 if (cmp <= 0) {
1416                         /* Ignore registers we trap but don't save. */
1417                         if (i1->reg) {
1418                                 if (!copy_reg_to_user(i1, &uind))
1419                                         return -EFAULT;
1420                                 total++;
1421                         }
1422                 } else {
1423                         /* Ignore registers we trap but don't save. */
1424                         if (i2->reg) {
1425                                 if (!copy_reg_to_user(i2, &uind))
1426                                         return -EFAULT;
1427                                 total++;
1428                         }
1429                 }
1430
1431                 if (cmp <= 0 && ++i1 == end1)
1432                         i1 = NULL;
1433                 if (cmp >= 0 && ++i2 == end2)
1434                         i2 = NULL;
1435         }
1436         return total;
1437 }
1438
1439 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
1440 {
1441         return ARRAY_SIZE(invariant_sys_regs)
1442                 + num_demux_regs()
1443                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
1444 }
1445
1446 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1447 {
1448         unsigned int i;
1449         int err;
1450
1451         /* Then give them all the invariant registers' indices. */
1452         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
1453                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
1454                         return -EFAULT;
1455                 uindices++;
1456         }
1457
1458         err = walk_sys_regs(vcpu, uindices);
1459         if (err < 0)
1460                 return err;
1461         uindices += err;
1462
1463         return write_demux_regids(uindices);
1464 }
1465
1466 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
1467 {
1468         unsigned int i;
1469
1470         for (i = 1; i < n; i++) {
1471                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
1472                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
1473                         return 1;
1474                 }
1475         }
1476
1477         return 0;
1478 }
1479
1480 void kvm_sys_reg_table_init(void)
1481 {
1482         unsigned int i;
1483         struct sys_reg_desc clidr;
1484
1485         /* Make sure tables are unique and in order. */
1486         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
1487         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
1488         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
1489         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
1490         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
1491         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
1492
1493         /* We abuse the reset function to overwrite the table itself. */
1494         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
1495                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
1496
1497         /*
1498          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
1499          *
1500          *   If software reads the Cache Type fields from Ctype1
1501          *   upwards, once it has seen a value of 0b000, no caches
1502          *   exist at further-out levels of the hierarchy. So, for
1503          *   example, if Ctype3 is the first Cache Type field with a
1504          *   value of 0b000, the values of Ctype4 to Ctype7 must be
1505          *   ignored.
1506          */
1507         get_clidr_el1(NULL, &clidr); /* Ugly... */
1508         cache_levels = clidr.val;
1509         for (i = 0; i < 7; i++)
1510                 if (((cache_levels >> (i*3)) & 7) == 0)
1511                         break;
1512         /* Clear all higher bits. */
1513         cache_levels &= (1 << (i*3))-1;
1514 }
1515
1516 /**
1517  * kvm_reset_sys_regs - sets system registers to reset value
1518  * @vcpu: The VCPU pointer
1519  *
1520  * This function finds the right table above and sets the registers on the
1521  * virtual CPU struct to their architecturally defined reset values.
1522  */
1523 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
1524 {
1525         size_t num;
1526         const struct sys_reg_desc *table;
1527
1528         /* Catch someone adding a register without putting in reset entry. */
1529         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
1530
1531         /* Generic chip reset first (so target could override). */
1532         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1533
1534         table = get_target_table(vcpu->arch.target, true, &num);
1535         reset_sys_reg_descs(vcpu, table, num);
1536
1537         for (num = 1; num < NR_SYS_REGS; num++)
1538                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
1539                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
1540 }