11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
28 select HAVE_KERNEL_GZIP if RAMKERNEL
29 select HAVE_KERNEL_BZIP2 if RAMKERNEL
30 select HAVE_KERNEL_LZMA if RAMKERNEL
31 select HAVE_KERNEL_LZO if RAMKERNEL
33 select HAVE_PERF_EVENTS
34 select ARCH_HAVE_CUSTOM_GPIO_H
35 select ARCH_WANT_OPTIONAL_GPIOLIB
37 select ARCH_WANT_IPC_PARSE_VERSION
38 select HAVE_GENERIC_HARDIRQS
39 select GENERIC_ATOMIC64
40 select GENERIC_IRQ_PROBE
41 select IRQ_PER_CPU if SMP
42 select USE_GENERIC_SMP_HELPERS if SMP
43 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
44 select GENERIC_SMP_IDLE_THREAD
45 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
46 select HAVE_MOD_ARCH_SPECIFIC
47 select MODULES_USE_ELF_RELA
48 select GENERIC_SIGALTSTACK
63 config FORCE_MAX_ZONEORDER
67 config GENERIC_CALIBRATE_DELAY
70 config LOCKDEP_SUPPORT
73 config STACKTRACE_SUPPORT
76 config TRACE_IRQFLAGS_SUPPORT
81 source "kernel/Kconfig.preempt"
83 source "kernel/Kconfig.freezer"
85 menu "Blackfin Processor Options"
87 comment "Processor and Board Settings"
96 BF512 Processor Support.
101 BF514 Processor Support.
106 BF516 Processor Support.
111 BF518 Processor Support.
116 BF522 Processor Support.
121 BF523 Processor Support.
126 BF524 Processor Support.
131 BF525 Processor Support.
136 BF526 Processor Support.
141 BF527 Processor Support.
146 BF531 Processor Support.
151 BF532 Processor Support.
156 BF533 Processor Support.
161 BF534 Processor Support.
166 BF536 Processor Support.
171 BF537 Processor Support.
176 BF538 Processor Support.
181 BF539 Processor Support.
186 BF542 Processor Support.
191 BF542 Processor Support.
196 BF544 Processor Support.
201 BF544 Processor Support.
206 BF547 Processor Support.
211 BF547 Processor Support.
216 BF548 Processor Support.
221 BF548 Processor Support.
226 BF549 Processor Support.
231 BF549 Processor Support.
236 BF561 Processor Support.
242 BF609 Processor Support.
248 select TICKSOURCE_CORETMR
249 bool "Symmetric multi-processing support"
251 This enables support for systems with more than one CPU,
252 like the dual core BF561. If you have a system with only one
253 CPU, say N. If you have a system with more than one CPU, say Y.
255 If you don't know what to do here, say N.
263 bool "Support for hot-pluggable CPUs"
264 depends on SMP && HOTPLUG
269 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
270 default 2 if (BF537 || BF536 || BF534)
271 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
272 default 4 if (BF538 || BF539)
276 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
277 default 3 if (BF537 || BF536 || BF534 || BF54xM)
278 default 5 if (BF561 || BF538 || BF539)
279 default 6 if (BF533 || BF532 || BF531)
283 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
284 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
285 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
289 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
293 depends on (BF51x || BF52x || (BF54x && !BF54xM))
297 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
301 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
305 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
309 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
313 depends on (BF533 || BF532 || BF531)
325 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
328 config MEM_MT48LC64M4A2FB_7E
330 depends on (BFIN533_STAMP)
333 config MEM_MT48LC16M16A2TG_75
335 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
336 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
337 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
338 || BFIN527_BLUETECHNIX_CM)
341 config MEM_MT48LC32M8A2_75
343 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
346 config MEM_MT48LC8M32B2B5_7
348 depends on (BFIN561_BLUETECHNIX_CM)
351 config MEM_MT48LC32M16A2TG_75
353 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
356 config MEM_MT48H32M16LFCJ_75
358 depends on (BFIN526_EZBRD)
361 config MEM_MT47H64M16
363 depends on (BFIN609_EZKIT)
366 source "arch/blackfin/mach-bf518/Kconfig"
367 source "arch/blackfin/mach-bf527/Kconfig"
368 source "arch/blackfin/mach-bf533/Kconfig"
369 source "arch/blackfin/mach-bf561/Kconfig"
370 source "arch/blackfin/mach-bf537/Kconfig"
371 source "arch/blackfin/mach-bf538/Kconfig"
372 source "arch/blackfin/mach-bf548/Kconfig"
373 source "arch/blackfin/mach-bf609/Kconfig"
375 menu "Board customizations"
378 bool "Default bootloader kernel arguments"
381 string "Initial kernel command string"
382 depends on CMDLINE_BOOL
383 default "console=ttyBF0,57600"
385 If you don't have a boot loader capable of passing a command line string
386 to the kernel, you may specify one here. As a minimum, you should specify
387 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
390 hex "Kernel load address for booting"
392 range 0x1000 0x20000000
394 This option allows you to set the load address of the kernel.
395 This can be useful if you are on a board which has a small amount
396 of memory or you wish to reserve some memory at the beginning of
399 Note that you need to keep this value above 4k (0x1000) as this
400 memory region is used to capture NULL pointer references as well
401 as some core kernel functions.
403 config PHY_RAM_BASE_ADDRESS
404 hex "Physical RAM Base"
407 set BF609 FPGA physical SRAM base address
410 hex "Kernel ROM Base"
413 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
414 range 0x20000000 0x30000000 if (BF54x || BF561)
415 range 0xB0000000 0xC0000000 if (BF60x)
417 Make sure your ROM base does not include any file-header
418 information that is prepended to the kernel.
420 For example, the bootable U-Boot format (created with
421 mkimage) has a 64 byte header (0x40). So while the image
422 you write to flash might start at say 0x20080000, you have
423 to add 0x40 to get the kernel's ROM base as it will come
426 comment "Clock/PLL Setup"
429 int "Frequency of the crystal on the board in Hz"
430 default "10000000" if BFIN532_IP0X
431 default "11059200" if BFIN533_STAMP
432 default "24576000" if PNAV10
433 default "25000000" # most people use this
434 default "27000000" if BFIN533_EZKIT
435 default "30000000" if BFIN561_EZKIT
436 default "24000000" if BFIN527_AD7160EVAL
438 The frequency of CLKIN crystal oscillator on the board in Hz.
439 Warning: This value should match the crystal on the board. Otherwise,
440 peripherals won't work properly.
442 config BFIN_KERNEL_CLOCK
443 bool "Re-program Clocks while Kernel boots?"
446 This option decides if kernel clocks are re-programed from the
447 bootloader settings. If the clocks are not set, the SDRAM settings
448 are also not changed, and the Bootloader does 100% of the hardware
453 depends on BFIN_KERNEL_CLOCK && (!BF60x)
458 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
461 If this is set the clock will be divided by 2, before it goes to the PLL.
465 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
467 default "22" if BFIN533_EZKIT
468 default "45" if BFIN533_STAMP
469 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
470 default "22" if BFIN533_BLUETECHNIX_CM
471 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
472 default "20" if (BFIN561_EZKIT || BF609)
473 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
474 default "25" if BFIN527_AD7160EVAL
476 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
477 PLL Frequency = (Crystal Frequency) * (this setting)
480 prompt "Core Clock Divider"
481 depends on BFIN_KERNEL_CLOCK
484 This sets the frequency of the core. It can be 1, 2, 4 or 8
485 Core Frequency = (PLL frequency) / (this setting)
501 int "System Clock Divider"
502 depends on BFIN_KERNEL_CLOCK
506 This sets the frequency of the system clock (including SDRAM or DDR) on
507 !BF60x else it set the clock for system buses and provides the
508 source from which SCLK0 and SCLK1 are derived.
509 This can be between 1 and 15
510 System Clock = (PLL frequency) / (this setting)
513 int "System Clock0 Divider"
514 depends on BFIN_KERNEL_CLOCK && BF60x
518 This sets the frequency of the system clock0 for PVP and all other
519 peripherals not clocked by SCLK1.
520 This can be between 1 and 15
521 System Clock0 = (System Clock) / (this setting)
524 int "System Clock1 Divider"
525 depends on BFIN_KERNEL_CLOCK && BF60x
529 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
530 This can be between 1 and 15
531 System Clock1 = (System Clock) / (this setting)
534 int "DDR Clock Divider"
535 depends on BFIN_KERNEL_CLOCK && BF60x
539 This sets the frequency of the DDR memory.
540 This can be between 1 and 15
541 DDR Clock = (PLL frequency) / (this setting)
544 prompt "DDR SDRAM Chip Type"
545 depends on BFIN_KERNEL_CLOCK
547 default MEM_MT46V32M16_5B
549 config MEM_MT46V32M16_6T
552 config MEM_MT46V32M16_5B
557 prompt "DDR/SDRAM Timing"
558 depends on BFIN_KERNEL_CLOCK && !BF60x
559 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
561 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
562 The calculated SDRAM timing parameters may not be 100%
563 accurate - This option is therefore marked experimental.
565 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
566 bool "Calculate Timings (EXPERIMENTAL)"
567 depends on EXPERIMENTAL
569 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
570 bool "Provide accurate Timings based on target SCLK"
572 Please consult the Blackfin Hardware Reference Manuals as well
573 as the memory device datasheet.
574 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
577 menu "Memory Init Control"
578 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
595 config MEM_EBIU_DDRQUE
612 # Max & Min Speeds for various Chips
616 default 400000000 if BF512
617 default 400000000 if BF514
618 default 400000000 if BF516
619 default 400000000 if BF518
620 default 400000000 if BF522
621 default 600000000 if BF523
622 default 400000000 if BF524
623 default 600000000 if BF525
624 default 400000000 if BF526
625 default 600000000 if BF527
626 default 400000000 if BF531
627 default 400000000 if BF532
628 default 750000000 if BF533
629 default 500000000 if BF534
630 default 400000000 if BF536
631 default 600000000 if BF537
632 default 533333333 if BF538
633 default 533333333 if BF539
634 default 600000000 if BF542
635 default 533333333 if BF544
636 default 600000000 if BF547
637 default 600000000 if BF548
638 default 533333333 if BF549
639 default 600000000 if BF561
640 default 800000000 if BF609
648 default 200000000 if BF609
655 comment "Kernel Timer/Scheduler"
657 source kernel/Kconfig.hz
659 config SET_GENERIC_CLOCKEVENTS
660 bool "Generic clock events"
662 select GENERIC_CLOCKEVENTS
664 menu "Clock event device"
665 depends on GENERIC_CLOCKEVENTS
666 config TICKSOURCE_GPTMR0
671 config TICKSOURCE_CORETMR
677 depends on GENERIC_CLOCKEVENTS
678 config CYCLES_CLOCKSOURCE
681 depends on !BFIN_SCRATCH_REG_CYCLES
684 If you say Y here, you will enable support for using the 'cycles'
685 registers as a clock source. Doing so means you will be unable to
686 safely write to the 'cycles' register during runtime. You will
687 still be able to read it (such as for performance monitoring), but
688 writing the registers will most likely crash the kernel.
690 config GPTMR0_CLOCKSOURCE
693 depends on !TICKSOURCE_GPTMR0
699 prompt "Blackfin Exception Scratch Register"
700 default BFIN_SCRATCH_REG_RETN
702 Select the resource to reserve for the Exception handler:
703 - RETN: Non-Maskable Interrupt (NMI)
704 - RETE: Exception Return (JTAG/ICE)
705 - CYCLES: Performance counter
707 If you are unsure, please select "RETN".
709 config BFIN_SCRATCH_REG_RETN
712 Use the RETN register in the Blackfin exception handler
713 as a stack scratch register. This means you cannot
714 safely use NMI on the Blackfin while running Linux, but
715 you can debug the system with a JTAG ICE and use the
716 CYCLES performance registers.
718 If you are unsure, please select "RETN".
720 config BFIN_SCRATCH_REG_RETE
723 Use the RETE register in the Blackfin exception handler
724 as a stack scratch register. This means you cannot
725 safely use a JTAG ICE while debugging a Blackfin board,
726 but you can safely use the CYCLES performance registers
729 If you are unsure, please select "RETN".
731 config BFIN_SCRATCH_REG_CYCLES
734 Use the CYCLES register in the Blackfin exception handler
735 as a stack scratch register. This means you cannot
736 safely use the CYCLES performance registers on a Blackfin
737 board at anytime, but you can debug the system with a JTAG
740 If you are unsure, please select "RETN".
747 menu "Blackfin Kernel Optimizations"
749 comment "Memory Optimizations"
752 bool "Locate interrupt entry code in L1 Memory"
756 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
757 into L1 instruction memory. (less latency)
759 config EXCPT_IRQ_SYSC_L1
760 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
764 If enabled, the entire ASM lowlevel exception and interrupt entry code
765 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
769 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
773 If enabled, the frequently called do_irq dispatcher function is linked
774 into L1 instruction memory. (less latency)
776 config CORE_TIMER_IRQ_L1
777 bool "Locate frequently called timer_interrupt() function in L1 Memory"
781 If enabled, the frequently called timer_interrupt() function is linked
782 into L1 instruction memory. (less latency)
785 bool "Locate frequently idle function in L1 Memory"
789 If enabled, the frequently called idle function is linked
790 into L1 instruction memory. (less latency)
793 bool "Locate kernel schedule function in L1 Memory"
797 If enabled, the frequently called kernel schedule is linked
798 into L1 instruction memory. (less latency)
800 config ARITHMETIC_OPS_L1
801 bool "Locate kernel owned arithmetic functions in L1 Memory"
805 If enabled, arithmetic functions are linked
806 into L1 instruction memory. (less latency)
809 bool "Locate access_ok function in L1 Memory"
813 If enabled, the access_ok function is linked
814 into L1 instruction memory. (less latency)
817 bool "Locate memset function in L1 Memory"
821 If enabled, the memset function is linked
822 into L1 instruction memory. (less latency)
825 bool "Locate memcpy function in L1 Memory"
829 If enabled, the memcpy function is linked
830 into L1 instruction memory. (less latency)
833 bool "locate strcmp function in L1 Memory"
837 If enabled, the strcmp function is linked
838 into L1 instruction memory (less latency).
841 bool "locate strncmp function in L1 Memory"
845 If enabled, the strncmp function is linked
846 into L1 instruction memory (less latency).
849 bool "locate strcpy function in L1 Memory"
853 If enabled, the strcpy function is linked
854 into L1 instruction memory (less latency).
857 bool "locate strncpy function in L1 Memory"
861 If enabled, the strncpy function is linked
862 into L1 instruction memory (less latency).
864 config SYS_BFIN_SPINLOCK_L1
865 bool "Locate sys_bfin_spinlock function in L1 Memory"
869 If enabled, sys_bfin_spinlock function is linked
870 into L1 instruction memory. (less latency)
872 config IP_CHECKSUM_L1
873 bool "Locate IP Checksum function in L1 Memory"
877 If enabled, the IP Checksum function is linked
878 into L1 instruction memory. (less latency)
880 config CACHELINE_ALIGNED_L1
881 bool "Locate cacheline_aligned data to L1 Data Memory"
884 depends on !SMP && !BF531 && !CRC32
886 If enabled, cacheline_aligned data is linked
887 into L1 data memory. (less latency)
889 config SYSCALL_TAB_L1
890 bool "Locate Syscall Table L1 Data Memory"
892 depends on !SMP && !BF531
894 If enabled, the Syscall LUT is linked
895 into L1 data memory. (less latency)
897 config CPLB_SWITCH_TAB_L1
898 bool "Locate CPLB Switch Tables L1 Data Memory"
900 depends on !SMP && !BF531
902 If enabled, the CPLB Switch Tables are linked
903 into L1 data memory. (less latency)
905 config ICACHE_FLUSH_L1
906 bool "Locate icache flush funcs in L1 Inst Memory"
909 If enabled, the Blackfin icache flushing functions are linked
910 into L1 instruction memory.
912 Note that this might be required to address anomalies, but
913 these functions are pretty small, so it shouldn't be too bad.
914 If you are using a processor affected by an anomaly, the build
915 system will double check for you and prevent it.
917 config DCACHE_FLUSH_L1
918 bool "Locate dcache flush funcs in L1 Inst Memory"
922 If enabled, the Blackfin dcache flushing functions are linked
923 into L1 instruction memory.
926 bool "Support locating application stack in L1 Scratch Memory"
930 If enabled the application stack can be located in L1
931 scratch memory (less latency).
933 Currently only works with FLAT binaries.
935 config EXCEPTION_L1_SCRATCH
936 bool "Locate exception stack in L1 Scratch Memory"
938 depends on !SMP && !APP_STACK_L1
940 Whenever an exception occurs, use the L1 Scratch memory for
941 stack storage. You cannot place the stacks of FLAT binaries
942 in L1 when using this option.
944 If you don't use L1 Scratch, then you should say Y here.
946 comment "Speed Optimizations"
947 config BFIN_INS_LOWOVERHEAD
948 bool "ins[bwl] low overhead, higher interrupt latency"
952 Reads on the Blackfin are speculative. In Blackfin terms, this means
953 they can be interrupted at any time (even after they have been issued
954 on to the external bus), and re-issued after the interrupt occurs.
955 For memory - this is not a big deal, since memory does not change if
958 If a FIFO is sitting on the end of the read, it will see two reads,
959 when the core only sees one since the FIFO receives both the read
960 which is cancelled (and not delivered to the core) and the one which
961 is re-issued (which is delivered to the core).
963 To solve this, interrupts are turned off before reads occur to
964 I/O space. This option controls which the overhead/latency of
965 controlling interrupts during this time
966 "n" turns interrupts off every read
967 (higher overhead, but lower interrupt latency)
968 "y" turns interrupts off every loop
969 (low overhead, but longer interrupt latency)
971 default behavior is to leave this set to on (type "Y"). If you are experiencing
972 interrupt latency issues, it is safe and OK to turn this off.
977 prompt "Kernel executes from"
979 Choose the memory type that the kernel will be running in.
984 The kernel will be resident in RAM when running.
989 The kernel will be resident in FLASH/ROM when running.
993 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
1001 config BFIN_GPTIMERS
1002 tristate "Enable Blackfin General Purpose Timers API"
1005 Enable support for the General Purpose Timers API. If you
1008 To compile this driver as a module, choose M here: the module
1009 will be called gptimers.
1012 prompt "Uncached DMA region"
1013 default DMA_UNCACHED_1M
1014 config DMA_UNCACHED_32M
1015 bool "Enable 32M DMA region"
1016 config DMA_UNCACHED_16M
1017 bool "Enable 16M DMA region"
1018 config DMA_UNCACHED_8M
1019 bool "Enable 8M DMA region"
1020 config DMA_UNCACHED_4M
1021 bool "Enable 4M DMA region"
1022 config DMA_UNCACHED_2M
1023 bool "Enable 2M DMA region"
1024 config DMA_UNCACHED_1M
1025 bool "Enable 1M DMA region"
1026 config DMA_UNCACHED_512K
1027 bool "Enable 512K DMA region"
1028 config DMA_UNCACHED_256K
1029 bool "Enable 256K DMA region"
1030 config DMA_UNCACHED_128K
1031 bool "Enable 128K DMA region"
1032 config DMA_UNCACHED_NONE
1033 bool "Disable DMA region"
1037 comment "Cache Support"
1040 bool "Enable ICACHE"
1042 config BFIN_EXTMEM_ICACHEABLE
1043 bool "Enable ICACHE for external memory"
1044 depends on BFIN_ICACHE
1046 config BFIN_L2_ICACHEABLE
1047 bool "Enable ICACHE for L2 SRAM"
1048 depends on BFIN_ICACHE
1049 depends on (BF54x || BF561 || BF60x) && !SMP
1053 bool "Enable DCACHE"
1055 config BFIN_DCACHE_BANKA
1056 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1057 depends on BFIN_DCACHE && !BF531
1059 config BFIN_EXTMEM_DCACHEABLE
1060 bool "Enable DCACHE for external memory"
1061 depends on BFIN_DCACHE
1064 prompt "External memory DCACHE policy"
1065 depends on BFIN_EXTMEM_DCACHEABLE
1066 default BFIN_EXTMEM_WRITEBACK if !SMP
1067 default BFIN_EXTMEM_WRITETHROUGH if SMP
1068 config BFIN_EXTMEM_WRITEBACK
1073 Cached data will be written back to SDRAM only when needed.
1074 This can give a nice increase in performance, but beware of
1075 broken drivers that do not properly invalidate/flush their
1078 Write Through Policy:
1079 Cached data will always be written back to SDRAM when the
1080 cache is updated. This is a completely safe setting, but
1081 performance is worse than Write Back.
1083 If you are unsure of the options and you want to be safe,
1084 then go with Write Through.
1086 config BFIN_EXTMEM_WRITETHROUGH
1087 bool "Write through"
1090 Cached data will be written back to SDRAM only when needed.
1091 This can give a nice increase in performance, but beware of
1092 broken drivers that do not properly invalidate/flush their
1095 Write Through Policy:
1096 Cached data will always be written back to SDRAM when the
1097 cache is updated. This is a completely safe setting, but
1098 performance is worse than Write Back.
1100 If you are unsure of the options and you want to be safe,
1101 then go with Write Through.
1105 config BFIN_L2_DCACHEABLE
1106 bool "Enable DCACHE for L2 SRAM"
1107 depends on BFIN_DCACHE
1108 depends on (BF54x || BF561 || BF60x) && !SMP
1111 prompt "L2 SRAM DCACHE policy"
1112 depends on BFIN_L2_DCACHEABLE
1113 default BFIN_L2_WRITEBACK
1114 config BFIN_L2_WRITEBACK
1117 config BFIN_L2_WRITETHROUGH
1118 bool "Write through"
1122 comment "Memory Protection Unit"
1124 bool "Enable the memory protection unit (EXPERIMENTAL)"
1127 Use the processor's MPU to protect applications from accessing
1128 memory they do not own. This comes at a performance penalty
1129 and is recommended only for debugging.
1131 comment "Asynchronous Memory Configuration"
1133 menu "EBIU_AMGCTL Global Control"
1136 bool "Enable CLKOUT"
1140 bool "DMA has priority over core for ext. accesses"
1145 bool "Bank 0 16 bit packing enable"
1150 bool "Bank 1 16 bit packing enable"
1155 bool "Bank 2 16 bit packing enable"
1160 bool "Bank 3 16 bit packing enable"
1164 prompt "Enable Asynchronous Memory Banks"
1168 bool "Disable All Banks"
1171 bool "Enable Bank 0"
1173 config C_AMBEN_B0_B1
1174 bool "Enable Bank 0 & 1"
1176 config C_AMBEN_B0_B1_B2
1177 bool "Enable Bank 0 & 1 & 2"
1180 bool "Enable All Banks"
1184 menu "EBIU_AMBCTL Control"
1187 hex "Bank 0 (AMBCTL0.L)"
1190 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1191 used to control the Asynchronous Memory Bank 0 settings.
1194 hex "Bank 1 (AMBCTL0.H)"
1196 default 0x5558 if BF54x
1198 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1199 used to control the Asynchronous Memory Bank 1 settings.
1202 hex "Bank 2 (AMBCTL1.L)"
1205 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1206 used to control the Asynchronous Memory Bank 2 settings.
1209 hex "Bank 3 (AMBCTL1.H)"
1212 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1213 used to control the Asynchronous Memory Bank 3 settings.
1217 config EBIU_MBSCTLVAL
1218 hex "EBIU Bank Select Control Register"
1223 hex "Flash Memory Mode Control Register"
1228 hex "Flash Memory Bank Control Register"
1233 #############################################################################
1234 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1240 Support for PCI bus.
1242 source "drivers/pci/Kconfig"
1244 source "drivers/pcmcia/Kconfig"
1246 source "drivers/pci/hotplug/Kconfig"
1250 menu "Executable file formats"
1252 source "fs/Kconfig.binfmt"
1256 menu "Power management options"
1258 source "kernel/power/Kconfig"
1260 config ARCH_SUSPEND_POSSIBLE
1264 prompt "Standby Power Saving Mode"
1265 depends on PM && !BF60x
1266 default PM_BFIN_SLEEP_DEEPER
1267 config PM_BFIN_SLEEP_DEEPER
1270 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1271 power dissipation by disabling the clock to the processor core (CCLK).
1272 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1273 to 0.85 V to provide the greatest power savings, while preserving the
1275 The PLL and system clock (SCLK) continue to operate at a very low
1276 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1277 the SDRAM is put into Self Refresh Mode. Typically an external event
1278 such as GPIO interrupt or RTC activity wakes up the processor.
1279 Various Peripherals such as UART, SPORT, PPI may not function as
1280 normal during Sleep Deeper, due to the reduced SCLK frequency.
1281 When in the sleep mode, system DMA access to L1 memory is not supported.
1283 If unsure, select "Sleep Deeper".
1285 config PM_BFIN_SLEEP
1288 Sleep Mode (High Power Savings) - The sleep mode reduces power
1289 dissipation by disabling the clock to the processor core (CCLK).
1290 The PLL and system clock (SCLK), however, continue to operate in
1291 this mode. Typically an external event or RTC activity will wake
1292 up the processor. When in the sleep mode, system DMA access to L1
1293 memory is not supported.
1295 If unsure, select "Sleep Deeper".
1298 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1301 config PM_BFIN_WAKE_PH6
1302 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1303 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1306 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1308 config PM_BFIN_WAKE_GP
1309 bool "Allow Wake-Up from GPIOs"
1310 depends on PM && BF54x
1313 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1314 (all processors, except ADSP-BF549). This option sets
1315 the general-purpose wake-up enable (GPWE) control bit to enable
1316 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1317 On ADSP-BF549 this option enables the same functionality on the
1318 /MRXON pin also PH7.
1320 config PM_BFIN_WAKE_PA15
1321 bool "Allow Wake-Up from PA15"
1322 depends on PM && BF60x
1327 config PM_BFIN_WAKE_PA15_POL
1328 int "Wake-up priority"
1329 depends on PM_BFIN_WAKE_PA15
1332 Wake-Up priority 0(low) 1(high)
1334 config PM_BFIN_WAKE_PB15
1335 bool "Allow Wake-Up from PB15"
1336 depends on PM && BF60x
1341 config PM_BFIN_WAKE_PB15_POL
1342 int "Wake-up priority"
1343 depends on PM_BFIN_WAKE_PB15
1346 Wake-Up priority 0(low) 1(high)
1348 config PM_BFIN_WAKE_PC15
1349 bool "Allow Wake-Up from PC15"
1350 depends on PM && BF60x
1355 config PM_BFIN_WAKE_PC15_POL
1356 int "Wake-up priority"
1357 depends on PM_BFIN_WAKE_PC15
1360 Wake-Up priority 0(low) 1(high)
1362 config PM_BFIN_WAKE_PD06
1363 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1364 depends on PM && BF60x
1367 Enable PD06(ETH0_PHYINT) Wake-up
1369 config PM_BFIN_WAKE_PD06_POL
1370 int "Wake-up priority"
1371 depends on PM_BFIN_WAKE_PD06
1374 Wake-Up priority 0(low) 1(high)
1376 config PM_BFIN_WAKE_PE12
1377 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1378 depends on PM && BF60x
1381 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1383 config PM_BFIN_WAKE_PE12_POL
1384 int "Wake-up priority"
1385 depends on PM_BFIN_WAKE_PE12
1388 Wake-Up priority 0(low) 1(high)
1390 config PM_BFIN_WAKE_PG04
1391 bool "Allow Wake-Up from PG04(CAN0_RX)"
1392 depends on PM && BF60x
1395 Enable PG04(CAN0_RX) Wake-up
1397 config PM_BFIN_WAKE_PG04_POL
1398 int "Wake-up priority"
1399 depends on PM_BFIN_WAKE_PG04
1402 Wake-Up priority 0(low) 1(high)
1404 config PM_BFIN_WAKE_PG13
1405 bool "Allow Wake-Up from PG13"
1406 depends on PM && BF60x
1411 config PM_BFIN_WAKE_PG13_POL
1412 int "Wake-up priority"
1413 depends on PM_BFIN_WAKE_PG13
1416 Wake-Up priority 0(low) 1(high)
1418 config PM_BFIN_WAKE_USB
1419 bool "Allow Wake-Up from (USB)"
1420 depends on PM && BF60x
1423 Enable (USB) Wake-up
1425 config PM_BFIN_WAKE_USB_POL
1426 int "Wake-up priority"
1427 depends on PM_BFIN_WAKE_USB
1430 Wake-Up priority 0(low) 1(high)
1434 menu "CPU Frequency scaling"
1436 source "drivers/cpufreq/Kconfig"
1438 config BFIN_CPU_FREQ
1441 select CPU_FREQ_TABLE
1445 bool "CPU Voltage scaling"
1446 depends on EXPERIMENTAL
1450 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1451 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1452 manuals. There is a theoretical risk that during VDDINT transitions
1457 source "net/Kconfig"
1459 source "drivers/Kconfig"
1461 source "drivers/firmware/Kconfig"
1465 source "arch/blackfin/Kconfig.debug"
1467 source "security/Kconfig"
1469 source "crypto/Kconfig"
1471 source "lib/Kconfig"