arch/c6x/kernel/setup.c

   1 /*
   2  *  Port on Texas Instruments TMS320C6x architecture
   3  *
   4  *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
   5  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 as
   9  *  published by the Free Software Foundation.
  10  */
  11 #include <linux/dma-mapping.h>
  12 #include <linux/memblock.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/bootmem.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/initrd.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of_fdt.h>
  20 #include <linux/string.h>
  21 #include <linux/errno.h>
  22 #include <linux/cache.h>
  23 #include <linux/delay.h>
  24 #include <linux/sched.h>
  25 #include <linux/clk.h>
  26 #include <linux/cpu.h>
  27 #include <linux/fs.h>
  28 #include <linux/of.h>
  29
  30
  31 #include <asm/sections.h>
  32 #include <asm/div64.h>
  33 #include <asm/setup.h>
  34 #include <asm/dscr.h>
  35 #include <asm/clock.h>
  36 #include <asm/soc.h>
  37 #include <asm/special_insns.h>
  38
  39 static const char *c6x_soc_name;
  40
  41 int c6x_num_cores;
  42 EXPORT_SYMBOL_GPL(c6x_num_cores);
  43
  44 unsigned int c6x_silicon_rev;
  45 EXPORT_SYMBOL_GPL(c6x_silicon_rev);
  46
  47 /*
  48  * Device status register. This holds information
  49  * about device configuration needed by some drivers.
  50  */
  51 unsigned int c6x_devstat;
  52 EXPORT_SYMBOL_GPL(c6x_devstat);
  53
  54 /*
  55  * Some SoCs have fuse registers holding a unique MAC
  56  * address. This is parsed out of the device tree with
  57  * the resulting MAC being held here.
  58  */
  59 unsigned char c6x_fuse_mac[6];
  60
  61 unsigned long memory_start;
  62 unsigned long memory_end;
  63
  64 unsigned long ram_start;
  65 unsigned long ram_end;
  66
  67 /* Uncached memory for DMA consistent use (memdma=) */
  68 static unsigned long dma_start __initdata;
  69 static unsigned long dma_size __initdata;
  70
  71 char c6x_command_line[COMMAND_LINE_SIZE];
  72
  73 #if defined(CONFIG_CMDLINE_BOOL)
  74 static const char default_command_line[COMMAND_LINE_SIZE] __section(.cmdline) =
  75         CONFIG_CMDLINE;
  76 #endif
  77
  78 struct cpuinfo_c6x {
  79         const char *cpu_name;
  80         const char *cpu_voltage;
  81         const char *mmu;
  82         const char *fpu;
  83         char *cpu_rev;
  84         unsigned int core_id;
  85         char __cpu_rev[5];
  86 };
  87
  88 static DEFINE_PER_CPU(struct cpuinfo_c6x, cpu_data);
  89
  90 unsigned int ticks_per_ns_scaled;
  91 EXPORT_SYMBOL(ticks_per_ns_scaled);
  92
  93 unsigned int c6x_core_freq;
  94
  95 static void __init get_cpuinfo(void)
  96 {
  97         unsigned cpu_id, rev_id, csr;
  98         struct clk *coreclk = clk_get_sys(NULL, "core");
  99         unsigned long core_khz;
 100         u64 tmp;
 101         struct cpuinfo_c6x *p;
 102         struct device_node *node, *np;
 103
 104         p = &per_cpu(cpu_data, smp_processor_id());
 105
 106         if (!IS_ERR(coreclk))
 107                 c6x_core_freq = clk_get_rate(coreclk);
 108         else {
 109                 printk(KERN_WARNING
 110                        "Cannot find core clock frequency. Using 700MHz\n");
 111                 c6x_core_freq = 700000000;
 112         }
 113
 114         core_khz = c6x_core_freq / 1000;
 115
 116         tmp = (uint64_t)core_khz << C6X_NDELAY_SCALE;
 117         do_div(tmp, 1000000);
 118         ticks_per_ns_scaled = tmp;
 119
 120         csr = get_creg(CSR);
 121         cpu_id = csr >> 24;
 122         rev_id = (csr >> 16) & 0xff;
 123
 124         p->mmu = "none";
 125         p->fpu = "none";
 126         p->cpu_voltage = "unknown";
 127
 128         switch (cpu_id) {
 129         case 0:
 130                 p->cpu_name = "C67x";
 131                 p->fpu = "yes";
 132                 break;
 133         case 2:
 134                 p->cpu_name = "C62x";
 135                 break;
 136         case 8:
 137                 p->cpu_name = "C64x";
 138                 break;
 139         case 12:
 140                 p->cpu_name = "C64x";
 141                 break;
 142         case 16:
 143                 p->cpu_name = "C64x+";
 144                 p->cpu_voltage = "1.2";
 145                 break;
 146         default:
 147                 p->cpu_name = "unknown";
 148                 break;
 149         }
 150
 151         if (cpu_id < 16) {
 152                 switch (rev_id) {
 153                 case 0x1:
 154                         if (cpu_id > 8) {
 155                                 p->cpu_rev = "DM640/DM641/DM642/DM643";
 156                                 p->cpu_voltage = "1.2 - 1.4";
 157                         } else {
 158                                 p->cpu_rev = "C6201";
 159                                 p->cpu_voltage = "2.5";
 160                         }
 161                         break;
 162                 case 0x2:
 163                         p->cpu_rev = "C6201B/C6202/C6211";
 164                         p->cpu_voltage = "1.8";
 165                         break;
 166                 case 0x3:
 167                         p->cpu_rev = "C6202B/C6203/C6204/C6205";
 168                         p->cpu_voltage = "1.5";
 169                         break;
 170                 case 0x201:
 171                         p->cpu_rev = "C6701 revision 0 (early CPU)";
 172                         p->cpu_voltage = "1.8";
 173                         break;
 174                 case 0x202:
 175                         p->cpu_rev = "C6701/C6711/C6712";
 176                         p->cpu_voltage = "1.8";
 177                         break;
 178                 case 0x801:
 179                         p->cpu_rev = "C64x";
 180                         p->cpu_voltage = "1.5";
 181                         break;
 182                 default:
 183                         p->cpu_rev = "unknown";
 184                 }
 185         } else {
 186                 p->cpu_rev = p->__cpu_rev;
 187                 snprintf(p->__cpu_rev, sizeof(p->__cpu_rev), "0x%x", cpu_id);
 188         }
 189
 190         p->core_id = get_coreid();
 191
 192         node = of_find_node_by_name(NULL, "cpus");
 193         if (node) {
 194                 for_each_child_of_node(node, np)
 195                         if (!strcmp("cpu", np->name))
 196                                 ++c6x_num_cores;
 197                 of_node_put(node);
 198         }
 199
 200         node = of_find_node_by_name(NULL, "soc");
 201         if (node) {
 202                 if (of_property_read_string(node, "model", &c6x_soc_name))
 203                         c6x_soc_name = "unknown";
 204                 of_node_put(node);
 205         } else
 206                 c6x_soc_name = "unknown";
 207
 208         printk(KERN_INFO "CPU%d: %s rev %s, %s volts, %uMHz\n",
 209                p->core_id, p->cpu_name, p->cpu_rev,
 210                p->cpu_voltage, c6x_core_freq / 1000000);
 211 }
 212
 213 /*
 214  * Early parsing of the command line
 215  */
 216 static u32 mem_size __initdata;
 217
 218 /* "mem=" parsing. */
 219 static int __init early_mem(char *p)
 220 {
 221         if (!p)
 222                 return -EINVAL;
 223
 224         mem_size = memparse(p, &p);
 225         /* don't remove all of memory when handling "mem={invalid}" */
 226         if (mem_size == 0)
 227                 return -EINVAL;
 228
 229         return 0;
 230 }
 231 early_param("mem", early_mem);
 232
 233 /* "memdma=<size>[@<address>]" parsing. */
 234 static int __init early_memdma(char *p)
 235 {
 236         if (!p)
 237                 return -EINVAL;
 238
 239         dma_size = memparse(p, &p);
 240         if (*p == '@')
 241                 dma_start = memparse(p, &p);
 242
 243         return 0;
 244 }
 245 early_param("memdma", early_memdma);
 246
 247 int __init c6x_add_memory(phys_addr_t start, unsigned long size)
 248 {
 249         static int ram_found __initdata;
 250
 251         /* We only handle one bank (the one with PAGE_OFFSET) for now */
 252         if (ram_found)
 253                 return -EINVAL;
 254
 255         if (start > PAGE_OFFSET || PAGE_OFFSET >= (start + size))
 256                 return 0;
 257
 258         ram_start = start;
 259         ram_end = start + size;
 260
 261         ram_found = 1;
 262         return 0;
 263 }
 264
 265 /*
 266  * Do early machine setup and device tree parsing. This is called very
 267  * early on the boot process.
 268  */
 269 notrace void __init machine_init(unsigned long dt_ptr)
 270 {
 271         struct boot_param_header *dtb = __va(dt_ptr);
 272         struct boot_param_header *fdt = (struct boot_param_header *)_fdt_start;
 273
 274         /* interrupts must be masked */
 275         set_creg(IER, 2);
 276
 277         /*
 278          * Set the Interrupt Service Table (IST) to the beginning of the
 279          * vector table.
 280          */
 281         set_ist(_vectors_start);
 282
 283         lockdep_init();
 284
 285         /*
 286          * dtb is passed in from bootloader.
 287          * fdt is linked in blob.
 288          */
 289         if (dtb && dtb != fdt)
 290                 fdt = dtb;
 291
 292         /* Do some early initialization based on the flat device tree */
 293         early_init_devtree(fdt);
 294
 295         /* parse_early_param needs a boot_command_line */
 296         strlcpy(boot_command_line, c6x_command_line, COMMAND_LINE_SIZE);
 297         parse_early_param();
 298 }
 299
 300 void __init setup_arch(char **cmdline_p)
 301 {
 302         int bootmap_size;
 303         struct memblock_region *reg;
 304
 305         printk(KERN_INFO "Initializing kernel\n");
 306
 307         /* Initialize command line */
 308         *cmdline_p = c6x_command_line;
 309
 310         memory_end = ram_end;
 311         memory_end &= ~(PAGE_SIZE - 1);
 312
 313         if (mem_size && (PAGE_OFFSET + PAGE_ALIGN(mem_size)) < memory_end)
 314                 memory_end = PAGE_OFFSET + PAGE_ALIGN(mem_size);
 315
 316         /* add block that this kernel can use */
 317         memblock_add(PAGE_OFFSET, memory_end - PAGE_OFFSET);
 318
 319         /* reserve kernel text/data/bss */
 320         memblock_reserve(PAGE_OFFSET,
 321                          PAGE_ALIGN((unsigned long)&_end - PAGE_OFFSET));
 322
 323         if (dma_size) {
 324                 /* align to cacheability granularity */
 325                 dma_size = CACHE_REGION_END(dma_size);
 326
 327                 if (!dma_start)
 328                         dma_start = memory_end - dma_size;
 329
 330                 /* align to cacheability granularity */
 331                 dma_start = CACHE_REGION_START(dma_start);
 332
 333                 /* reserve DMA memory taken from kernel memory */
 334                 if (memblock_is_region_memory(dma_start, dma_size))
 335                         memblock_reserve(dma_start, dma_size);
 336         }
 337
 338         memory_start = PAGE_ALIGN((unsigned int) &_end);
 339
 340         printk(KERN_INFO "Memory Start=%08lx, Memory End=%08lx\n",
 341                memory_start, memory_end);
 342
 343 #ifdef CONFIG_BLK_DEV_INITRD
 344         /*
 345          * Reserve initrd memory if in kernel memory.
 346          */
 347         if (initrd_start < initrd_end)
 348                 if (memblock_is_region_memory(initrd_start,
 349                                               initrd_end - initrd_start))
 350                         memblock_reserve(initrd_start,
 351                                          initrd_end - initrd_start);
 352 #endif
 353
 354         init_mm.start_code = (unsigned long) &_stext;
 355         init_mm.end_code   = (unsigned long) &_etext;
 356         init_mm.end_data   = memory_start;
 357         init_mm.brk        = memory_start;
 358
 359         /*
 360          * Give all the memory to the bootmap allocator,  tell it to put the
 361          * boot mem_map at the start of memory
 362          */
 363         bootmap_size = init_bootmem_node(NODE_DATA(0),
 364                                          memory_start >> PAGE_SHIFT,
 365                                          PAGE_OFFSET >> PAGE_SHIFT,
 366                                          memory_end >> PAGE_SHIFT);
 367         memblock_reserve(memory_start, bootmap_size);
 368
 369         unflatten_device_tree();
 370
 371         c6x_cache_init();
 372
 373         /* Set the whole external memory as non-cacheable */
 374         disable_caching(ram_start, ram_end - 1);
 375
 376         /* Set caching of external RAM used by Linux */
 377         for_each_memblock(memory, reg)
 378                 enable_caching(CACHE_REGION_START(reg->base),
 379                                CACHE_REGION_START(reg->base + reg->size - 1));
 380
 381 #ifdef CONFIG_BLK_DEV_INITRD
 382         /*
 383          * Enable caching for initrd which falls outside kernel memory.
 384          */
 385         if (initrd_start < initrd_end) {
 386                 if (!memblock_is_region_memory(initrd_start,
 387                                                initrd_end - initrd_start))
 388                         enable_caching(CACHE_REGION_START(initrd_start),
 389                                        CACHE_REGION_START(initrd_end - 1));
 390         }
 391 #endif
 392
 393         /*
 394          * Disable caching for dma coherent memory taken from kernel memory.
 395          */
 396         if (dma_size && memblock_is_region_memory(dma_start, dma_size))
 397                 disable_caching(dma_start,
 398                                 CACHE_REGION_START(dma_start + dma_size - 1));
 399
 400         /* Initialize the coherent memory allocator */
 401         coherent_mem_init(dma_start, dma_size);
 402
 403         /*
 404          * Free all memory as a starting point.
 405          */
 406         free_bootmem(PAGE_OFFSET, memory_end - PAGE_OFFSET);
 407
 408         /*
 409          * Then reserve memory which is already being used.
 410          */
 411         for_each_memblock(reserved, reg) {
 412                 pr_debug("reserved - 0x%08x-0x%08x\n",
 413                          (u32) reg->base, (u32) reg->size);
 414                 reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
 415         }
 416
 417         max_low_pfn = PFN_DOWN(memory_end);
 418         min_low_pfn = PFN_UP(memory_start);
 419         max_mapnr = max_low_pfn - min_low_pfn;
 420
 421         /* Get kmalloc into gear */
 422         paging_init();
 423
 424         /*
 425          * Probe for Device State Configuration Registers.
 426          * We have to do this early in case timer needs to be enabled
 427          * through DSCR.
 428          */
 429         dscr_probe();
 430
 431         /* We do this early for timer and core clock frequency */
 432         c64x_setup_clocks();
 433
 434         /* Get CPU info */
 435         get_cpuinfo();
 436
 437 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
 438         conswitchp = &dummy_con;
 439 #endif
 440 }
 441
 442 #define cpu_to_ptr(n) ((void *)((long)(n)+1))
 443 #define ptr_to_cpu(p) ((long)(p) - 1)
 444
 445 static int show_cpuinfo(struct seq_file *m, void *v)
 446 {
 447         int n = ptr_to_cpu(v);
 448         struct cpuinfo_c6x *p = &per_cpu(cpu_data, n);
 449
 450         if (n == 0) {
 451                 seq_printf(m,
 452                            "soc\t\t: %s\n"
 453                            "soc revision\t: 0x%x\n"
 454                            "soc cores\t: %d\n",
 455                            c6x_soc_name, c6x_silicon_rev, c6x_num_cores);
 456         }
 457
 458         seq_printf(m,
 459                    "\n"
 460                    "processor\t: %d\n"
 461                    "cpu\t\t: %s\n"
 462                    "core revision\t: %s\n"
 463                    "core voltage\t: %s\n"
 464                    "core id\t\t: %d\n"
 465                    "mmu\t\t: %s\n"
 466                    "fpu\t\t: %s\n"
 467                    "cpu MHz\t\t: %u\n"
 468                    "bogomips\t: %lu.%02lu\n\n",
 469                    n,
 470                    p->cpu_name, p->cpu_rev, p->cpu_voltage,
 471                    p->core_id, p->mmu, p->fpu,
 472                    (c6x_core_freq + 500000) / 1000000,
 473                    (loops_per_jiffy/(500000/HZ)),
 474                    (loops_per_jiffy/(5000/HZ))%100);
 475
 476         return 0;
 477 }
 478
 479 static void *c_start(struct seq_file *m, loff_t *pos)
 480 {
 481         return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
 482 }
 483 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 484 {
 485         ++*pos;
 486         return NULL;
 487 }
 488 static void c_stop(struct seq_file *m, void *v)
 489 {
 490 }
 491
 492 const struct seq_operations cpuinfo_op = {
 493         c_start,
 494         c_stop,
 495         c_next,
 496         show_cpuinfo
 497 };
 498
 499 static struct cpu cpu_devices[NR_CPUS];
 500
 501 static int __init topology_init(void)
 502 {
 503         int i;
 504
 505         for_each_present_cpu(i)
 506                 register_cpu(&cpu_devices[i], i);
 507
 508         return 0;
 509 }
 510
 511 subsys_initcall(topology_init);