3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/immap.h>
18 #include <linux/compiler.h>
21 * Breath some life into the CPU...
23 * Set up the memory map,
24 * initialize a bunch of registers,
25 * initialize the UPM's
29 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
30 fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
32 #if !defined(CONFIG_CF_SBF)
33 scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
34 pll_t *pll = (pll_t *)MMAP_PLL;
36 /* Workaround, must place before fbcs */
37 out_be32(&pll->psr, 0x12);
39 out_be32(&scm1->mpr, 0x77777777);
40 out_be32(&scm1->pacra, 0);
41 out_be32(&scm1->pacrb, 0);
42 out_be32(&scm1->pacrc, 0);
43 out_be32(&scm1->pacrd, 0);
44 out_be32(&scm1->pacre, 0);
45 out_be32(&scm1->pacrf, 0);
46 out_be32(&scm1->pacrg, 0);
47 out_be32(&scm1->pacri, 0);
49 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
50 && defined(CONFIG_SYS_CS0_CTRL))
51 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
52 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
53 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
55 #endif /* CONFIG_CF_SBF */
57 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
58 && defined(CONFIG_SYS_CS1_CTRL))
59 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
60 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
61 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
64 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
65 && defined(CONFIG_SYS_CS2_CTRL))
66 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
67 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
68 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
71 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
72 && defined(CONFIG_SYS_CS3_CTRL))
73 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
74 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
75 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
78 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
79 && defined(CONFIG_SYS_CS4_CTRL))
80 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
81 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
82 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
85 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
86 && defined(CONFIG_SYS_CS5_CTRL))
87 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
88 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
89 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
92 #ifdef CONFIG_SYS_I2C_FSL
93 out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
100 * initialize higher level parts of CPU like timers
105 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
106 rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
108 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
109 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
115 void uart_port_conf(int port)
117 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
122 clrbits_be16(&gpio->par_uart,
123 ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
124 setbits_be16(&gpio->par_uart,
125 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
128 clrbits_be16(&gpio->par_uart,
129 ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
130 setbits_be16(&gpio->par_uart,
131 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
134 clrbits_8(&gpio->par_dspi,
135 ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
136 out_8(&gpio->par_dspi,
137 GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
142 #ifdef CONFIG_CF_DSPI
143 void cfspi_port_conf(void)
145 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
147 out_8(&gpio->par_dspi,
148 GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
149 GPIO_PAR_DSPI_SCK_SCK);
152 int cfspi_claim_bus(uint bus, uint cs)
154 dspi_t *dspi = (dspi_t *) MMAP_DSPI;
155 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
157 if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
160 /* Clear FIFO and resume transfer */
161 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
165 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
166 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
169 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
170 setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
177 void cfspi_release_bus(uint bus, uint cs)
179 dspi_t *dspi = (dspi_t *) MMAP_DSPI;
180 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
183 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
187 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
190 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);