2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform IRQ support
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
16 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/types.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/of_irq.h>
22 #include <linux/timex.h>
23 #include <linux/slab.h>
24 #include <linux/delay.h>
28 #include <asm/mach-jz4740/base.h>
29 #include <asm/mach-jz4740/irq.h>
33 #include "../../drivers/irqchip/irqchip.h"
35 static void __iomem *jz_intc_base;
37 #define JZ_REG_INTC_STATUS 0x00
38 #define JZ_REG_INTC_MASK 0x04
39 #define JZ_REG_INTC_SET_MASK 0x08
40 #define JZ_REG_INTC_CLEAR_MASK 0x0c
41 #define JZ_REG_INTC_PENDING 0x10
43 static irqreturn_t jz4740_cascade(int irq, void *data)
47 irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
50 generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
55 static void jz4740_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
57 struct irq_chip_regs *regs = &gc->chip_types->regs;
59 writel(mask, gc->reg_base + regs->enable);
60 writel(~mask, gc->reg_base + regs->disable);
63 void jz4740_irq_suspend(struct irq_data *data)
65 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
66 jz4740_irq_set_mask(gc, gc->wake_active);
69 void jz4740_irq_resume(struct irq_data *data)
71 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
72 jz4740_irq_set_mask(gc, gc->mask_cache);
75 static struct irqaction jz4740_cascade_action = {
76 .handler = jz4740_cascade,
77 .name = "JZ4740 cascade interrupt",
80 static int __init jz4740_intc_of_init(struct device_node *node,
81 struct device_node *parent)
83 struct irq_chip_generic *gc;
84 struct irq_chip_type *ct;
85 struct irq_domain *domain;
88 parent_irq = irq_of_parse_and_map(node, 0);
92 jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
95 writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
97 gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base,
100 gc->wake_enabled = IRQ_MSK(32);
103 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
104 ct->regs.disable = JZ_REG_INTC_SET_MASK;
105 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
106 ct->chip.irq_mask = irq_gc_mask_disable_reg;
107 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
108 ct->chip.irq_set_wake = irq_gc_set_wake;
109 ct->chip.irq_suspend = jz4740_irq_suspend;
110 ct->chip.irq_resume = jz4740_irq_resume;
112 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
114 domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0,
115 &irq_domain_simple_ops, NULL);
117 pr_warn("unable to register IRQ domain\n");
119 setup_irq(parent_irq, &jz4740_cascade_action);
122 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", jz4740_intc_of_init);