2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
29 #include <asm/watch.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
39 * Get the FPU Implementation/Revision.
41 static inline unsigned long cpu_get_fpu_id(void)
43 unsigned long tmp, fpu_id;
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
53 * Check if the CPU has an external FPU.
55 static inline int __cpu_has_fpu(void)
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
60 static inline unsigned long cpu_get_msa_id(void)
62 unsigned long status, msa_id;
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
67 msa_id = read_msa_ir();
69 write_c0_status(status);
74 * Determine the FCSR mask for FPU hardware.
76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
102 * Set the FIR feature flags for the FPU emulator.
104 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
109 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
110 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
112 value |= MIPS_FPIR_D | MIPS_FPIR_S;
113 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
114 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
115 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
119 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
120 static unsigned int mips_nofpu_msk31;
123 * Set options for FPU hardware.
125 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
127 c->fpu_id = cpu_get_fpu_id();
128 mips_nofpu_msk31 = c->fpu_msk31;
130 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
131 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
132 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
133 if (c->fpu_id & MIPS_FPIR_3D)
134 c->ases |= MIPS_ASE_MIPS3D;
135 if (c->fpu_id & MIPS_FPIR_FREP)
136 c->options |= MIPS_CPU_FRE;
139 cpu_set_fpu_fcsr_mask(c);
143 * Set options for the FPU emulator.
145 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
147 c->options &= ~MIPS_CPU_FPU;
148 c->fpu_msk31 = mips_nofpu_msk31;
153 static int mips_fpu_disabled;
155 static int __init fpu_disable(char *s)
157 cpu_set_nofpu_opts(&boot_cpu_data);
158 mips_fpu_disabled = 1;
163 __setup("nofpu", fpu_disable);
165 int mips_dsp_disabled;
167 static int __init dsp_disable(char *s)
169 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
170 mips_dsp_disabled = 1;
175 __setup("nodsp", dsp_disable);
177 static int mips_htw_disabled;
179 static int __init htw_disable(char *s)
181 mips_htw_disabled = 1;
182 cpu_data[0].options &= ~MIPS_CPU_HTW;
183 write_c0_pwctl(read_c0_pwctl() &
184 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
189 __setup("nohtw", htw_disable);
191 static int mips_ftlb_disabled;
192 static int mips_has_ftlb_configured;
194 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
196 static int __init ftlb_disable(char *s)
198 unsigned int config4, mmuextdef;
201 * If the core hasn't done any FTLB configuration, there is nothing
204 if (!mips_has_ftlb_configured)
207 /* Disable it in the boot cpu */
208 if (set_ftlb_enable(&cpu_data[0], 0)) {
209 pr_warn("Can't turn FTLB off\n");
213 back_to_back_c0_hazard();
215 config4 = read_c0_config4();
217 /* Check that FTLB has been disabled */
218 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
219 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
220 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
221 /* This should never happen */
222 pr_warn("FTLB could not be disabled!\n");
226 mips_ftlb_disabled = 1;
227 mips_has_ftlb_configured = 0;
230 * noftlb is mainly used for debug purposes so print
231 * an informative message instead of using pr_debug()
233 pr_info("FTLB has been disabled\n");
236 * Some of these bits are duplicated in the decode_config4.
237 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
238 * once FTLB has been disabled so undo what decode_config4 did.
240 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
241 cpu_data[0].tlbsizeftlbsets;
242 cpu_data[0].tlbsizeftlbsets = 0;
243 cpu_data[0].tlbsizeftlbways = 0;
248 __setup("noftlb", ftlb_disable);
251 static inline void check_errata(void)
253 struct cpuinfo_mips *c = ¤t_cpu_data;
255 switch (current_cpu_type()) {
258 * Erratum "RPS May Cause Incorrect Instruction Execution"
259 * This code only handles VPE0, any SMP/RTOS code
260 * making use of VPE1 will be responsable for that VPE.
262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
270 void __init check_bugs32(void)
276 * Probe whether cpu has config register by trying to play with
277 * alternate cache bit and see whether it matters.
278 * It's used by cpu_probe to distinguish between R3000A and R3081.
280 static inline int cpu_has_confreg(void)
282 #ifdef CONFIG_CPU_R3000
283 extern unsigned long r3k_cache_size(unsigned long);
284 unsigned long size1, size2;
285 unsigned long cfg = read_c0_conf();
287 size1 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg ^ R30XX_CONF_AC);
289 size2 = r3k_cache_size(ST0_ISC);
291 return size1 != size2;
297 static inline void set_elf_platform(int cpu, const char *plat)
300 __elf_platform = plat;
303 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
305 #ifdef __NEED_VMBITS_PROBE
306 write_c0_entryhi(0x3fffffffffffe000ULL);
307 back_to_back_c0_hazard();
308 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
312 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
315 case MIPS_CPU_ISA_M64R2:
316 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
317 case MIPS_CPU_ISA_M64R1:
318 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
320 c->isa_level |= MIPS_CPU_ISA_V;
321 case MIPS_CPU_ISA_IV:
322 c->isa_level |= MIPS_CPU_ISA_IV;
323 case MIPS_CPU_ISA_III:
324 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
327 /* R6 incompatible with everything else */
328 case MIPS_CPU_ISA_M64R6:
329 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
330 case MIPS_CPU_ISA_M32R6:
331 c->isa_level |= MIPS_CPU_ISA_M32R6;
332 /* Break here so we don't add incompatible ISAs */
334 case MIPS_CPU_ISA_M32R2:
335 c->isa_level |= MIPS_CPU_ISA_M32R2;
336 case MIPS_CPU_ISA_M32R1:
337 c->isa_level |= MIPS_CPU_ISA_M32R1;
338 case MIPS_CPU_ISA_II:
339 c->isa_level |= MIPS_CPU_ISA_II;
344 static char unknown_isa[] = KERN_ERR \
345 "Unsupported ISA type, c0.config0: %d.";
347 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
350 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
353 * 0 = All TLBWR instructions go to FTLB
354 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
355 * FTLB and 1 goes to the VTLB.
356 * 2 = 7:1: As above with 7:1 ratio.
357 * 3 = 3:1: As above with 3:1 ratio.
359 * Use the linear midpoint as the probability threshold.
361 if (probability >= 12)
363 else if (probability >= 6)
367 * So FTLB is less than 4 times bigger than VTLB.
368 * A 3:1 ratio can still be useful though.
373 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
377 /* It's implementation dependent how the FTLB can be enabled */
378 switch (c->cputype) {
381 /* proAptiv & related cores use Config6 to enable the FTLB */
382 config = read_c0_config6();
383 /* Clear the old probability value */
384 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
387 write_c0_config6(config |
388 (calculate_ftlb_probability(c)
389 << MIPS_CONF6_FTLBP_SHIFT)
390 | MIPS_CONF6_FTLBEN);
393 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
396 /* I6400 & related cores use Config7 to configure FTLB */
397 config = read_c0_config7();
398 /* Clear the old probability value */
399 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
400 write_c0_config7(config | (calculate_ftlb_probability(c)
401 << MIPS_CONF7_FTLBP_SHIFT));
410 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
412 unsigned int config0;
415 config0 = read_c0_config();
418 * Look for Standard TLB or Dual VTLB and FTLB
420 mt = config0 & MIPS_CONF_MT;
421 if (mt == MIPS_CONF_MT_TLB)
422 c->options |= MIPS_CPU_TLB;
423 else if (mt == MIPS_CONF_MT_FTLB)
424 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
426 isa = (config0 & MIPS_CONF_AT) >> 13;
429 switch ((config0 & MIPS_CONF_AR) >> 10) {
431 set_isa(c, MIPS_CPU_ISA_M32R1);
434 set_isa(c, MIPS_CPU_ISA_M32R2);
437 set_isa(c, MIPS_CPU_ISA_M32R6);
444 switch ((config0 & MIPS_CONF_AR) >> 10) {
446 set_isa(c, MIPS_CPU_ISA_M64R1);
449 set_isa(c, MIPS_CPU_ISA_M64R2);
452 set_isa(c, MIPS_CPU_ISA_M64R6);
462 return config0 & MIPS_CONF_M;
465 panic(unknown_isa, config0);
468 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
470 unsigned int config1;
472 config1 = read_c0_config1();
474 if (config1 & MIPS_CONF1_MD)
475 c->ases |= MIPS_ASE_MDMX;
476 if (config1 & MIPS_CONF1_WR)
477 c->options |= MIPS_CPU_WATCH;
478 if (config1 & MIPS_CONF1_CA)
479 c->ases |= MIPS_ASE_MIPS16;
480 if (config1 & MIPS_CONF1_EP)
481 c->options |= MIPS_CPU_EJTAG;
482 if (config1 & MIPS_CONF1_FP) {
483 c->options |= MIPS_CPU_FPU;
484 c->options |= MIPS_CPU_32FPR;
487 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
488 c->tlbsizevtlb = c->tlbsize;
489 c->tlbsizeftlbsets = 0;
492 return config1 & MIPS_CONF_M;
495 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
497 unsigned int config2;
499 config2 = read_c0_config2();
501 if (config2 & MIPS_CONF2_SL)
502 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
504 return config2 & MIPS_CONF_M;
507 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
509 unsigned int config3;
511 config3 = read_c0_config3();
513 if (config3 & MIPS_CONF3_SM) {
514 c->ases |= MIPS_ASE_SMARTMIPS;
515 c->options |= MIPS_CPU_RIXI;
517 if (config3 & MIPS_CONF3_RXI)
518 c->options |= MIPS_CPU_RIXI;
519 if (config3 & MIPS_CONF3_DSP)
520 c->ases |= MIPS_ASE_DSP;
521 if (config3 & MIPS_CONF3_DSP2P)
522 c->ases |= MIPS_ASE_DSP2P;
523 if (config3 & MIPS_CONF3_VINT)
524 c->options |= MIPS_CPU_VINT;
525 if (config3 & MIPS_CONF3_VEIC)
526 c->options |= MIPS_CPU_VEIC;
527 if (config3 & MIPS_CONF3_MT)
528 c->ases |= MIPS_ASE_MIPSMT;
529 if (config3 & MIPS_CONF3_ULRI)
530 c->options |= MIPS_CPU_ULRI;
531 if (config3 & MIPS_CONF3_ISA)
532 c->options |= MIPS_CPU_MICROMIPS;
533 if (config3 & MIPS_CONF3_VZ)
534 c->ases |= MIPS_ASE_VZ;
535 if (config3 & MIPS_CONF3_SC)
536 c->options |= MIPS_CPU_SEGMENTS;
537 if (config3 & MIPS_CONF3_MSA)
538 c->ases |= MIPS_ASE_MSA;
539 /* Only tested on 32-bit cores */
540 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
542 c->options |= MIPS_CPU_HTW;
544 if (config3 & MIPS_CONF3_CDMM)
545 c->options |= MIPS_CPU_CDMM;
546 if (config3 & MIPS_CONF3_SP)
547 c->options |= MIPS_CPU_SP;
549 return config3 & MIPS_CONF_M;
552 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
554 unsigned int config4;
556 unsigned int mmuextdef;
557 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
559 config4 = read_c0_config4();
562 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
563 c->options |= MIPS_CPU_TLBINV;
566 * R6 has dropped the MMUExtDef field from config4.
567 * On R6 the fields always describe the FTLB, and only if it is
568 * present according to Config.MT.
570 if (!cpu_has_mips_r6)
571 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
572 else if (cpu_has_ftlb)
573 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
578 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
579 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
580 c->tlbsizevtlb = c->tlbsize;
582 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
584 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
585 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
586 c->tlbsize = c->tlbsizevtlb;
587 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
589 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
590 if (mips_ftlb_disabled)
592 newcf4 = (config4 & ~ftlb_page) |
593 (page_size_ftlb(mmuextdef) <<
594 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
595 write_c0_config4(newcf4);
596 back_to_back_c0_hazard();
597 config4 = read_c0_config4();
598 if (config4 != newcf4) {
599 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
601 /* Switch FTLB off */
602 set_ftlb_enable(c, 0);
605 c->tlbsizeftlbsets = 1 <<
606 ((config4 & MIPS_CONF4_FTLBSETS) >>
607 MIPS_CONF4_FTLBSETS_SHIFT);
608 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
609 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
610 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
611 mips_has_ftlb_configured = 1;
616 c->kscratch_mask = (config4 >> 16) & 0xff;
618 return config4 & MIPS_CONF_M;
621 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
623 unsigned int config5;
625 config5 = read_c0_config5();
626 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
627 write_c0_config5(config5);
629 if (config5 & MIPS_CONF5_EVA)
630 c->options |= MIPS_CPU_EVA;
631 if (config5 & MIPS_CONF5_MRP)
632 c->options |= MIPS_CPU_MAAR;
633 if (config5 & MIPS_CONF5_LLB)
634 c->options |= MIPS_CPU_RW_LLB;
636 if (config5 & MIPS_CONF5_MVH)
637 c->options |= MIPS_CPU_XPA;
640 return config5 & MIPS_CONF_M;
643 static void decode_configs(struct cpuinfo_mips *c)
647 /* MIPS32 or MIPS64 compliant CPU. */
648 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
649 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
651 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
653 /* Enable FTLB if present and not disabled */
654 set_ftlb_enable(c, !mips_ftlb_disabled);
656 ok = decode_config0(c); /* Read Config registers. */
657 BUG_ON(!ok); /* Arch spec violation! */
659 ok = decode_config1(c);
661 ok = decode_config2(c);
663 ok = decode_config3(c);
665 ok = decode_config4(c);
667 ok = decode_config5(c);
669 mips_probe_watch_registers(c);
672 /* Enable the RIXI exceptions */
673 set_c0_pagegrain(PG_IEC);
674 back_to_back_c0_hazard();
675 /* Verify the IEC bit is set */
676 if (read_c0_pagegrain() & PG_IEC)
677 c->options |= MIPS_CPU_RIXIEX;
680 #ifndef CONFIG_MIPS_CPS
681 if (cpu_has_mips_r2_r6) {
682 c->core = get_ebase_cpunum();
684 c->core >>= fls(core_nvpes()) - 1;
689 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
692 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
694 switch (c->processor_id & PRID_IMP_MASK) {
696 c->cputype = CPU_R2000;
697 __cpu_name[cpu] = "R2000";
698 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
699 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
702 c->options |= MIPS_CPU_FPU;
706 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
707 if (cpu_has_confreg()) {
708 c->cputype = CPU_R3081E;
709 __cpu_name[cpu] = "R3081";
711 c->cputype = CPU_R3000A;
712 __cpu_name[cpu] = "R3000A";
715 c->cputype = CPU_R3000;
716 __cpu_name[cpu] = "R3000";
718 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
719 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
722 c->options |= MIPS_CPU_FPU;
726 if (read_c0_config() & CONF_SC) {
727 if ((c->processor_id & PRID_REV_MASK) >=
729 c->cputype = CPU_R4400PC;
730 __cpu_name[cpu] = "R4400PC";
732 c->cputype = CPU_R4000PC;
733 __cpu_name[cpu] = "R4000PC";
736 int cca = read_c0_config() & CONF_CM_CMASK;
740 * SC and MC versions can't be reliably told apart,
741 * but only the latter support coherent caching
742 * modes so assume the firmware has set the KSEG0
743 * coherency attribute reasonably (if uncached, we
747 case CONF_CM_CACHABLE_CE:
748 case CONF_CM_CACHABLE_COW:
749 case CONF_CM_CACHABLE_CUW:
756 if ((c->processor_id & PRID_REV_MASK) >=
758 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
759 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
761 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
762 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
766 set_isa(c, MIPS_CPU_ISA_III);
767 c->fpu_msk31 |= FPU_CSR_CONDX;
768 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
769 MIPS_CPU_WATCH | MIPS_CPU_VCE |
773 case PRID_IMP_VR41XX:
774 set_isa(c, MIPS_CPU_ISA_III);
775 c->fpu_msk31 |= FPU_CSR_CONDX;
776 c->options = R4K_OPTS;
778 switch (c->processor_id & 0xf0) {
779 case PRID_REV_VR4111:
780 c->cputype = CPU_VR4111;
781 __cpu_name[cpu] = "NEC VR4111";
783 case PRID_REV_VR4121:
784 c->cputype = CPU_VR4121;
785 __cpu_name[cpu] = "NEC VR4121";
787 case PRID_REV_VR4122:
788 if ((c->processor_id & 0xf) < 0x3) {
789 c->cputype = CPU_VR4122;
790 __cpu_name[cpu] = "NEC VR4122";
792 c->cputype = CPU_VR4181A;
793 __cpu_name[cpu] = "NEC VR4181A";
796 case PRID_REV_VR4130:
797 if ((c->processor_id & 0xf) < 0x4) {
798 c->cputype = CPU_VR4131;
799 __cpu_name[cpu] = "NEC VR4131";
801 c->cputype = CPU_VR4133;
802 c->options |= MIPS_CPU_LLSC;
803 __cpu_name[cpu] = "NEC VR4133";
807 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
808 c->cputype = CPU_VR41XX;
809 __cpu_name[cpu] = "NEC Vr41xx";
814 c->cputype = CPU_R4300;
815 __cpu_name[cpu] = "R4300";
816 set_isa(c, MIPS_CPU_ISA_III);
817 c->fpu_msk31 |= FPU_CSR_CONDX;
818 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
823 c->cputype = CPU_R4600;
824 __cpu_name[cpu] = "R4600";
825 set_isa(c, MIPS_CPU_ISA_III);
826 c->fpu_msk31 |= FPU_CSR_CONDX;
827 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
834 * This processor doesn't have an MMU, so it's not
835 * "real easy" to run Linux on it. It is left purely
836 * for documentation. Commented out because it shares
837 * it's c0_prid id number with the TX3900.
839 c->cputype = CPU_R4650;
840 __cpu_name[cpu] = "R4650";
841 set_isa(c, MIPS_CPU_ISA_III);
842 c->fpu_msk31 |= FPU_CSR_CONDX;
843 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
848 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
849 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
851 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
852 c->cputype = CPU_TX3927;
853 __cpu_name[cpu] = "TX3927";
856 switch (c->processor_id & PRID_REV_MASK) {
857 case PRID_REV_TX3912:
858 c->cputype = CPU_TX3912;
859 __cpu_name[cpu] = "TX3912";
862 case PRID_REV_TX3922:
863 c->cputype = CPU_TX3922;
864 __cpu_name[cpu] = "TX3922";
871 c->cputype = CPU_R4700;
872 __cpu_name[cpu] = "R4700";
873 set_isa(c, MIPS_CPU_ISA_III);
874 c->fpu_msk31 |= FPU_CSR_CONDX;
875 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
880 c->cputype = CPU_TX49XX;
881 __cpu_name[cpu] = "R49XX";
882 set_isa(c, MIPS_CPU_ISA_III);
883 c->fpu_msk31 |= FPU_CSR_CONDX;
884 c->options = R4K_OPTS | MIPS_CPU_LLSC;
885 if (!(c->processor_id & 0x08))
886 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
890 c->cputype = CPU_R5000;
891 __cpu_name[cpu] = "R5000";
892 set_isa(c, MIPS_CPU_ISA_IV);
893 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
898 c->cputype = CPU_R5432;
899 __cpu_name[cpu] = "R5432";
900 set_isa(c, MIPS_CPU_ISA_IV);
901 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
902 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
906 c->cputype = CPU_R5500;
907 __cpu_name[cpu] = "R5500";
908 set_isa(c, MIPS_CPU_ISA_IV);
909 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
910 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
913 case PRID_IMP_NEVADA:
914 c->cputype = CPU_NEVADA;
915 __cpu_name[cpu] = "Nevada";
916 set_isa(c, MIPS_CPU_ISA_IV);
917 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
918 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
922 c->cputype = CPU_R6000;
923 __cpu_name[cpu] = "R6000";
924 set_isa(c, MIPS_CPU_ISA_II);
925 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
926 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
930 case PRID_IMP_R6000A:
931 c->cputype = CPU_R6000A;
932 __cpu_name[cpu] = "R6000A";
933 set_isa(c, MIPS_CPU_ISA_II);
934 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
935 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
939 case PRID_IMP_RM7000:
940 c->cputype = CPU_RM7000;
941 __cpu_name[cpu] = "RM7000";
942 set_isa(c, MIPS_CPU_ISA_IV);
943 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
946 * Undocumented RM7000: Bit 29 in the info register of
947 * the RM7000 v2.0 indicates if the TLB has 48 or 64
950 * 29 1 => 64 entry JTLB
953 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
956 c->cputype = CPU_R8000;
957 __cpu_name[cpu] = "RM8000";
958 set_isa(c, MIPS_CPU_ISA_IV);
959 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
960 MIPS_CPU_FPU | MIPS_CPU_32FPR |
962 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
964 case PRID_IMP_R10000:
965 c->cputype = CPU_R10000;
966 __cpu_name[cpu] = "R10000";
967 set_isa(c, MIPS_CPU_ISA_IV);
968 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
969 MIPS_CPU_FPU | MIPS_CPU_32FPR |
970 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
974 case PRID_IMP_R12000:
975 c->cputype = CPU_R12000;
976 __cpu_name[cpu] = "R12000";
977 set_isa(c, MIPS_CPU_ISA_IV);
978 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
979 MIPS_CPU_FPU | MIPS_CPU_32FPR |
980 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
981 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
984 case PRID_IMP_R14000:
985 if (((c->processor_id >> 4) & 0x0f) > 2) {
986 c->cputype = CPU_R16000;
987 __cpu_name[cpu] = "R16000";
989 c->cputype = CPU_R14000;
990 __cpu_name[cpu] = "R14000";
992 set_isa(c, MIPS_CPU_ISA_IV);
993 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
994 MIPS_CPU_FPU | MIPS_CPU_32FPR |
995 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
996 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
999 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1000 switch (c->processor_id & PRID_REV_MASK) {
1001 case PRID_REV_LOONGSON2E:
1002 c->cputype = CPU_LOONGSON2;
1003 __cpu_name[cpu] = "ICT Loongson-2";
1004 set_elf_platform(cpu, "loongson2e");
1005 set_isa(c, MIPS_CPU_ISA_III);
1006 c->fpu_msk31 |= FPU_CSR_CONDX;
1008 case PRID_REV_LOONGSON2F:
1009 c->cputype = CPU_LOONGSON2;
1010 __cpu_name[cpu] = "ICT Loongson-2";
1011 set_elf_platform(cpu, "loongson2f");
1012 set_isa(c, MIPS_CPU_ISA_III);
1013 c->fpu_msk31 |= FPU_CSR_CONDX;
1015 case PRID_REV_LOONGSON3A:
1016 c->cputype = CPU_LOONGSON3;
1017 __cpu_name[cpu] = "ICT Loongson-3";
1018 set_elf_platform(cpu, "loongson3a");
1019 set_isa(c, MIPS_CPU_ISA_M64R1);
1021 case PRID_REV_LOONGSON3B_R1:
1022 case PRID_REV_LOONGSON3B_R2:
1023 c->cputype = CPU_LOONGSON3;
1024 __cpu_name[cpu] = "ICT Loongson-3";
1025 set_elf_platform(cpu, "loongson3b");
1026 set_isa(c, MIPS_CPU_ISA_M64R1);
1030 c->options = R4K_OPTS |
1031 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1034 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1036 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1039 c->cputype = CPU_LOONGSON1;
1041 switch (c->processor_id & PRID_REV_MASK) {
1042 case PRID_REV_LOONGSON1B:
1043 __cpu_name[cpu] = "Loongson 1B";
1051 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1053 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1054 switch (c->processor_id & PRID_IMP_MASK) {
1055 case PRID_IMP_QEMU_GENERIC:
1056 c->writecombine = _CACHE_UNCACHED;
1057 c->cputype = CPU_QEMU_GENERIC;
1058 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1061 c->cputype = CPU_4KC;
1062 c->writecombine = _CACHE_UNCACHED;
1063 __cpu_name[cpu] = "MIPS 4Kc";
1066 case PRID_IMP_4KECR2:
1067 c->cputype = CPU_4KEC;
1068 c->writecombine = _CACHE_UNCACHED;
1069 __cpu_name[cpu] = "MIPS 4KEc";
1073 c->cputype = CPU_4KSC;
1074 c->writecombine = _CACHE_UNCACHED;
1075 __cpu_name[cpu] = "MIPS 4KSc";
1078 c->cputype = CPU_5KC;
1079 c->writecombine = _CACHE_UNCACHED;
1080 __cpu_name[cpu] = "MIPS 5Kc";
1083 c->cputype = CPU_5KE;
1084 c->writecombine = _CACHE_UNCACHED;
1085 __cpu_name[cpu] = "MIPS 5KE";
1088 c->cputype = CPU_20KC;
1089 c->writecombine = _CACHE_UNCACHED;
1090 __cpu_name[cpu] = "MIPS 20Kc";
1093 c->cputype = CPU_24K;
1094 c->writecombine = _CACHE_UNCACHED;
1095 __cpu_name[cpu] = "MIPS 24Kc";
1098 c->cputype = CPU_24K;
1099 c->writecombine = _CACHE_UNCACHED;
1100 __cpu_name[cpu] = "MIPS 24KEc";
1103 c->cputype = CPU_25KF;
1104 c->writecombine = _CACHE_UNCACHED;
1105 __cpu_name[cpu] = "MIPS 25Kc";
1108 c->cputype = CPU_34K;
1109 c->writecombine = _CACHE_UNCACHED;
1110 __cpu_name[cpu] = "MIPS 34Kc";
1113 c->cputype = CPU_74K;
1114 c->writecombine = _CACHE_UNCACHED;
1115 __cpu_name[cpu] = "MIPS 74Kc";
1117 case PRID_IMP_M14KC:
1118 c->cputype = CPU_M14KC;
1119 c->writecombine = _CACHE_UNCACHED;
1120 __cpu_name[cpu] = "MIPS M14Kc";
1122 case PRID_IMP_M14KEC:
1123 c->cputype = CPU_M14KEC;
1124 c->writecombine = _CACHE_UNCACHED;
1125 __cpu_name[cpu] = "MIPS M14KEc";
1127 case PRID_IMP_1004K:
1128 c->cputype = CPU_1004K;
1129 c->writecombine = _CACHE_UNCACHED;
1130 __cpu_name[cpu] = "MIPS 1004Kc";
1132 case PRID_IMP_1074K:
1133 c->cputype = CPU_1074K;
1134 c->writecombine = _CACHE_UNCACHED;
1135 __cpu_name[cpu] = "MIPS 1074Kc";
1137 case PRID_IMP_INTERAPTIV_UP:
1138 c->cputype = CPU_INTERAPTIV;
1139 __cpu_name[cpu] = "MIPS interAptiv";
1141 case PRID_IMP_INTERAPTIV_MP:
1142 c->cputype = CPU_INTERAPTIV;
1143 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1145 case PRID_IMP_PROAPTIV_UP:
1146 c->cputype = CPU_PROAPTIV;
1147 __cpu_name[cpu] = "MIPS proAptiv";
1149 case PRID_IMP_PROAPTIV_MP:
1150 c->cputype = CPU_PROAPTIV;
1151 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1153 case PRID_IMP_P5600:
1154 c->cputype = CPU_P5600;
1155 __cpu_name[cpu] = "MIPS P5600";
1157 case PRID_IMP_I6400:
1158 c->cputype = CPU_I6400;
1159 __cpu_name[cpu] = "MIPS I6400";
1161 case PRID_IMP_M5150:
1162 c->cputype = CPU_M5150;
1163 __cpu_name[cpu] = "MIPS M5150";
1172 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1175 switch (c->processor_id & PRID_IMP_MASK) {
1176 case PRID_IMP_AU1_REV1:
1177 case PRID_IMP_AU1_REV2:
1178 c->cputype = CPU_ALCHEMY;
1179 switch ((c->processor_id >> 24) & 0xff) {
1181 __cpu_name[cpu] = "Au1000";
1184 __cpu_name[cpu] = "Au1500";
1187 __cpu_name[cpu] = "Au1100";
1190 __cpu_name[cpu] = "Au1550";
1193 __cpu_name[cpu] = "Au1200";
1194 if ((c->processor_id & PRID_REV_MASK) == 2)
1195 __cpu_name[cpu] = "Au1250";
1198 __cpu_name[cpu] = "Au1210";
1201 __cpu_name[cpu] = "Au1xxx";
1208 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1212 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1213 switch (c->processor_id & PRID_IMP_MASK) {
1215 c->cputype = CPU_SB1;
1216 __cpu_name[cpu] = "SiByte SB1";
1217 /* FPU in pass1 is known to have issues. */
1218 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1219 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1222 c->cputype = CPU_SB1A;
1223 __cpu_name[cpu] = "SiByte SB1A";
1228 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1231 switch (c->processor_id & PRID_IMP_MASK) {
1232 case PRID_IMP_SR71000:
1233 c->cputype = CPU_SR71000;
1234 __cpu_name[cpu] = "Sandcraft SR71000";
1241 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1244 switch (c->processor_id & PRID_IMP_MASK) {
1245 case PRID_IMP_PR4450:
1246 c->cputype = CPU_PR4450;
1247 __cpu_name[cpu] = "Philips PR4450";
1248 set_isa(c, MIPS_CPU_ISA_M32R1);
1253 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1256 switch (c->processor_id & PRID_IMP_MASK) {
1257 case PRID_IMP_BMIPS32_REV4:
1258 case PRID_IMP_BMIPS32_REV8:
1259 c->cputype = CPU_BMIPS32;
1260 __cpu_name[cpu] = "Broadcom BMIPS32";
1261 set_elf_platform(cpu, "bmips32");
1263 case PRID_IMP_BMIPS3300:
1264 case PRID_IMP_BMIPS3300_ALT:
1265 case PRID_IMP_BMIPS3300_BUG:
1266 c->cputype = CPU_BMIPS3300;
1267 __cpu_name[cpu] = "Broadcom BMIPS3300";
1268 set_elf_platform(cpu, "bmips3300");
1270 case PRID_IMP_BMIPS43XX: {
1271 int rev = c->processor_id & PRID_REV_MASK;
1273 if (rev >= PRID_REV_BMIPS4380_LO &&
1274 rev <= PRID_REV_BMIPS4380_HI) {
1275 c->cputype = CPU_BMIPS4380;
1276 __cpu_name[cpu] = "Broadcom BMIPS4380";
1277 set_elf_platform(cpu, "bmips4380");
1279 c->cputype = CPU_BMIPS4350;
1280 __cpu_name[cpu] = "Broadcom BMIPS4350";
1281 set_elf_platform(cpu, "bmips4350");
1285 case PRID_IMP_BMIPS5000:
1286 case PRID_IMP_BMIPS5200:
1287 c->cputype = CPU_BMIPS5000;
1288 __cpu_name[cpu] = "Broadcom BMIPS5000";
1289 set_elf_platform(cpu, "bmips5000");
1290 c->options |= MIPS_CPU_ULRI;
1295 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1298 switch (c->processor_id & PRID_IMP_MASK) {
1299 case PRID_IMP_CAVIUM_CN38XX:
1300 case PRID_IMP_CAVIUM_CN31XX:
1301 case PRID_IMP_CAVIUM_CN30XX:
1302 c->cputype = CPU_CAVIUM_OCTEON;
1303 __cpu_name[cpu] = "Cavium Octeon";
1305 case PRID_IMP_CAVIUM_CN58XX:
1306 case PRID_IMP_CAVIUM_CN56XX:
1307 case PRID_IMP_CAVIUM_CN50XX:
1308 case PRID_IMP_CAVIUM_CN52XX:
1309 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1310 __cpu_name[cpu] = "Cavium Octeon+";
1312 set_elf_platform(cpu, "octeon");
1314 case PRID_IMP_CAVIUM_CN61XX:
1315 case PRID_IMP_CAVIUM_CN63XX:
1316 case PRID_IMP_CAVIUM_CN66XX:
1317 case PRID_IMP_CAVIUM_CN68XX:
1318 case PRID_IMP_CAVIUM_CNF71XX:
1319 c->cputype = CPU_CAVIUM_OCTEON2;
1320 __cpu_name[cpu] = "Cavium Octeon II";
1321 set_elf_platform(cpu, "octeon2");
1323 case PRID_IMP_CAVIUM_CN70XX:
1324 case PRID_IMP_CAVIUM_CN78XX:
1325 c->cputype = CPU_CAVIUM_OCTEON3;
1326 __cpu_name[cpu] = "Cavium Octeon III";
1327 set_elf_platform(cpu, "octeon3");
1330 printk(KERN_INFO "Unknown Octeon chip!\n");
1331 c->cputype = CPU_UNKNOWN;
1336 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1339 /* JZRISC does not implement the CP0 counter. */
1340 c->options &= ~MIPS_CPU_COUNTER;
1341 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1342 switch (c->processor_id & PRID_IMP_MASK) {
1343 case PRID_IMP_JZRISC:
1344 c->cputype = CPU_JZRISC;
1345 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1346 __cpu_name[cpu] = "Ingenic JZRISC";
1349 panic("Unknown Ingenic Processor ID!");
1354 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1358 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1359 c->cputype = CPU_ALCHEMY;
1360 __cpu_name[cpu] = "Au1300";
1361 /* following stuff is not for Alchemy */
1365 c->options = (MIPS_CPU_TLB |
1373 switch (c->processor_id & PRID_IMP_MASK) {
1374 case PRID_IMP_NETLOGIC_XLP2XX:
1375 case PRID_IMP_NETLOGIC_XLP9XX:
1376 case PRID_IMP_NETLOGIC_XLP5XX:
1377 c->cputype = CPU_XLP;
1378 __cpu_name[cpu] = "Broadcom XLPII";
1381 case PRID_IMP_NETLOGIC_XLP8XX:
1382 case PRID_IMP_NETLOGIC_XLP3XX:
1383 c->cputype = CPU_XLP;
1384 __cpu_name[cpu] = "Netlogic XLP";
1387 case PRID_IMP_NETLOGIC_XLR732:
1388 case PRID_IMP_NETLOGIC_XLR716:
1389 case PRID_IMP_NETLOGIC_XLR532:
1390 case PRID_IMP_NETLOGIC_XLR308:
1391 case PRID_IMP_NETLOGIC_XLR532C:
1392 case PRID_IMP_NETLOGIC_XLR516C:
1393 case PRID_IMP_NETLOGIC_XLR508C:
1394 case PRID_IMP_NETLOGIC_XLR308C:
1395 c->cputype = CPU_XLR;
1396 __cpu_name[cpu] = "Netlogic XLR";
1399 case PRID_IMP_NETLOGIC_XLS608:
1400 case PRID_IMP_NETLOGIC_XLS408:
1401 case PRID_IMP_NETLOGIC_XLS404:
1402 case PRID_IMP_NETLOGIC_XLS208:
1403 case PRID_IMP_NETLOGIC_XLS204:
1404 case PRID_IMP_NETLOGIC_XLS108:
1405 case PRID_IMP_NETLOGIC_XLS104:
1406 case PRID_IMP_NETLOGIC_XLS616B:
1407 case PRID_IMP_NETLOGIC_XLS608B:
1408 case PRID_IMP_NETLOGIC_XLS416B:
1409 case PRID_IMP_NETLOGIC_XLS412B:
1410 case PRID_IMP_NETLOGIC_XLS408B:
1411 case PRID_IMP_NETLOGIC_XLS404B:
1412 c->cputype = CPU_XLR;
1413 __cpu_name[cpu] = "Netlogic XLS";
1417 pr_info("Unknown Netlogic chip id [%02x]!\n",
1419 c->cputype = CPU_XLR;
1423 if (c->cputype == CPU_XLP) {
1424 set_isa(c, MIPS_CPU_ISA_M64R2);
1425 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1426 /* This will be updated again after all threads are woken up */
1427 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1429 set_isa(c, MIPS_CPU_ISA_M64R1);
1430 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1432 c->kscratch_mask = 0xf;
1436 /* For use by uaccess.h */
1438 EXPORT_SYMBOL(__ua_limit);
1441 const char *__cpu_name[NR_CPUS];
1442 const char *__elf_platform;
1444 void cpu_probe(void)
1446 struct cpuinfo_mips *c = ¤t_cpu_data;
1447 unsigned int cpu = smp_processor_id();
1449 c->processor_id = PRID_IMP_UNKNOWN;
1450 c->fpu_id = FPIR_IMP_NONE;
1451 c->cputype = CPU_UNKNOWN;
1452 c->writecombine = _CACHE_UNCACHED;
1454 c->fpu_csr31 = FPU_CSR_RN;
1455 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1457 c->processor_id = read_c0_prid();
1458 switch (c->processor_id & PRID_COMP_MASK) {
1459 case PRID_COMP_LEGACY:
1460 cpu_probe_legacy(c, cpu);
1462 case PRID_COMP_MIPS:
1463 cpu_probe_mips(c, cpu);
1465 case PRID_COMP_ALCHEMY:
1466 cpu_probe_alchemy(c, cpu);
1468 case PRID_COMP_SIBYTE:
1469 cpu_probe_sibyte(c, cpu);
1471 case PRID_COMP_BROADCOM:
1472 cpu_probe_broadcom(c, cpu);
1474 case PRID_COMP_SANDCRAFT:
1475 cpu_probe_sandcraft(c, cpu);
1478 cpu_probe_nxp(c, cpu);
1480 case PRID_COMP_CAVIUM:
1481 cpu_probe_cavium(c, cpu);
1483 case PRID_COMP_INGENIC_D0:
1484 case PRID_COMP_INGENIC_D1:
1485 case PRID_COMP_INGENIC_E1:
1486 cpu_probe_ingenic(c, cpu);
1488 case PRID_COMP_NETLOGIC:
1489 cpu_probe_netlogic(c, cpu);
1493 BUG_ON(!__cpu_name[cpu]);
1494 BUG_ON(c->cputype == CPU_UNKNOWN);
1497 * Platform code can force the cpu type to optimize code
1498 * generation. In that case be sure the cpu type is correctly
1499 * manually setup otherwise it could trigger some nasty bugs.
1501 BUG_ON(current_cpu_type() != c->cputype);
1503 if (mips_fpu_disabled)
1504 c->options &= ~MIPS_CPU_FPU;
1506 if (mips_dsp_disabled)
1507 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1509 if (mips_htw_disabled) {
1510 c->options &= ~MIPS_CPU_HTW;
1511 write_c0_pwctl(read_c0_pwctl() &
1512 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1515 if (c->options & MIPS_CPU_FPU)
1516 cpu_set_fpu_opts(c);
1518 cpu_set_nofpu_opts(c);
1520 if (cpu_has_bp_ghist)
1521 write_c0_r10k_diag(read_c0_r10k_diag() |
1524 if (cpu_has_mips_r2_r6) {
1525 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1526 /* R2 has Performance Counter Interrupt indicator */
1527 c->options |= MIPS_CPU_PCI;
1532 if (cpu_has_mips_r6)
1533 elf_hwcap |= HWCAP_MIPS_R6;
1536 c->msa_id = cpu_get_msa_id();
1537 WARN(c->msa_id & MSA_IR_WRPF,
1538 "Vector register partitioning unimplemented!");
1539 elf_hwcap |= HWCAP_MIPS_MSA;
1542 cpu_probe_vmbits(c);
1546 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1550 void cpu_report(void)
1552 struct cpuinfo_mips *c = ¤t_cpu_data;
1554 pr_info("CPU%d revision is: %08x (%s)\n",
1555 smp_processor_id(), c->processor_id, cpu_name_string());
1556 if (c->options & MIPS_CPU_FPU)
1557 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1559 pr_info("MSA revision is: %08x\n", c->msa_id);