arch/mips/kernel/csrc-sb1250.c

   1 /*
   2  * Copyright (C) 2000, 2001 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <linux/clocksource.h>
  15
  16 #include <asm/addrspace.h>
  17 #include <asm/io.h>
  18 #include <asm/time.h>
  19
  20 #include <asm/sibyte/sb1250.h>
  21 #include <asm/sibyte/sb1250_regs.h>
  22 #include <asm/sibyte/sb1250_int.h>
  23 #include <asm/sibyte/sb1250_scd.h>
  24
  25 #define SB1250_HPT_NUM          3
  26 #define SB1250_HPT_VALUE        M_SCD_TIMER_CNT /* max value */
  27
  28 /*
  29  * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
  30  * again.
  31  */
  32 static inline cycle_t sb1250_hpt_get_cycles(void)
  33 {
  34         unsigned int count;
  35         void __iomem *addr;
  36
  37         addr = IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT));
  38         count = G_SCD_TIMER_CNT(__raw_readq(addr));
  39
  40         return SB1250_HPT_VALUE - count;
  41 }
  42
  43 static cycle_t sb1250_hpt_read(struct clocksource *cs)
  44 {
  45         return sb1250_hpt_get_cycles();
  46 }
  47
  48 struct clocksource bcm1250_clocksource = {
  49         .name   = "bcm1250-counter-3",
  50         .rating = 200,
  51         .read   = sb1250_hpt_read,
  52         .mask   = CLOCKSOURCE_MASK(23),
  53         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
  54 };
  55
  56 void __init sb1250_clocksource_init(void)
  57 {
  58         struct clocksource *cs = &bcm1250_clocksource;
  59
  60         /* Setup hpt using timer #3 but do not enable irq for it */
  61         __raw_writeq(0,
  62                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
  63                                                  R_SCD_TIMER_CFG)));
  64         __raw_writeq(SB1250_HPT_VALUE,
  65                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
  66                                                  R_SCD_TIMER_INIT)));
  67         __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
  68                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
  69                                                  R_SCD_TIMER_CFG)));
  70
  71         clocksource_register_hz(cs, V_SCD_TIMER_FREQ);
  72 }