2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * written by Carsten Langgaard, carstenl@mips.com
14 #define USE_ALTERNATE_RESUME_IMPL 1
17 #include "r4k_switch.S"
20 * task_struct *resume(task_struct *prev, task_struct *next,
21 * struct thread_info *next_ti, int usedfpu)
27 LONG_S t1, THREAD_STATUS(a0)
28 cpu_save_nonscratch a0
29 LONG_S ra, THREAD_REG31(a0)
32 * check if we need to save FPU registers
37 PTR_L t3, TASK_THREAD_INFO(a0)
41 * clear saved user stack CU1 bit
50 fpu_save_double a0 t0 t1 # c0_status passed in t0
55 /* check if we need to save COP2 registers */
59 /* Disable COP2 in the stored process state */
64 /* Enable COP2 so we can save it */
74 /* Disable COP2 now that we are done */
81 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
82 /* Check if we need to store CVMSEG state */
83 mfc0 t0, $11,7 /* CvmMemCtl */
84 bbit0 t0, 6, 3f /* Is user access enabled? */
86 /* Store the CVMSEG state */
87 /* Extract the size of CVMSEG */
89 /* Multiply * (cache line size/sizeof(long)/2) */
91 li t1, -32768 /* Base address of CVMSEG */
92 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
96 LONG_L t8, 0(t1) /* Load from CVMSEG */
97 subu t0, 1 /* Decrement loop var */
98 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
99 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
100 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
101 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
102 bnez t0, 2b /* Loop until we've copied it all */
103 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
106 /* Disable access to CVMSEG */
107 mfc0 t0, $11,7 /* CvmMemCtl */
108 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
109 mtc0 t0, $11,7 /* CvmMemCtl */
113 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
114 PTR_LA t8, __stack_chk_guard
115 LONG_L t9, TASK_STACK_CANARY(a1)
120 * The order of restoring the registers takes care of the race
121 * updating $28, $29 and kernelsp without disabling ints.
124 cpu_restore_nonscratch a1
126 PTR_ADDU t0, $28, _THREAD_SIZE - 32
127 set_saved_sp t0, t1, t2
129 mfc0 t1, CP0_STATUS /* Do we really need this? */
132 LONG_L a2, THREAD_STATUS(a1)
142 * void octeon_cop2_save(struct octeon_cop2_state *a0)
145 LEAF(octeon_cop2_save)
147 dmfc0 t9, $9,7 /* CvmCtl register. */
149 /* Save the COP2 CRC state */
153 sd t0, OCTEON_CP2_CRC_IV(a0)
154 sd t1, OCTEON_CP2_CRC_LENGTH(a0)
155 sd t2, OCTEON_CP2_CRC_POLY(a0)
156 /* Skip next instructions if CvmCtl[NODFA_CP2] set */
159 /* Save the LLM state */
162 sd t0, OCTEON_CP2_LLM_DAT(a0)
163 sd t1, OCTEON_CP2_LLM_DAT+8(a0)
165 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
167 /* Save the COP2 crypto state */
168 /* this part is mostly common to both pass 1 and later revisions */
173 sd t0, OCTEON_CP2_3DES_IV(a0)
175 sd t1, OCTEON_CP2_3DES_KEY(a0)
176 dmfc2 t1, 0x0111 /* only necessary for pass 1 */
177 sd t2, OCTEON_CP2_3DES_KEY+8(a0)
179 sd t3, OCTEON_CP2_3DES_KEY+16(a0)
181 sd t0, OCTEON_CP2_3DES_RESULT(a0)
183 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
185 sd t2, OCTEON_CP2_AES_IV(a0)
187 sd t3, OCTEON_CP2_AES_IV+8(a0)
189 sd t0, OCTEON_CP2_AES_KEY(a0)
191 sd t1, OCTEON_CP2_AES_KEY+8(a0)
193 sd t2, OCTEON_CP2_AES_KEY+16(a0)
195 sd t3, OCTEON_CP2_AES_KEY+24(a0)
196 mfc0 t3, $15,0 /* Get the processor ID register */
197 sd t0, OCTEON_CP2_AES_KEYLEN(a0)
198 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
199 sd t1, OCTEON_CP2_AES_RESULT(a0)
200 sd t2, OCTEON_CP2_AES_RESULT+8(a0)
201 /* Skip to the Pass1 version of the remainder of the COP2 state */
204 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
209 sd t1, OCTEON_CP2_HSH_DATW(a0)
211 sd t2, OCTEON_CP2_HSH_DATW+8(a0)
213 sd t3, OCTEON_CP2_HSH_DATW+16(a0)
215 sd t0, OCTEON_CP2_HSH_DATW+24(a0)
217 sd t1, OCTEON_CP2_HSH_DATW+32(a0)
219 sd t2, OCTEON_CP2_HSH_DATW+40(a0)
221 sd t3, OCTEON_CP2_HSH_DATW+48(a0)
223 sd t0, OCTEON_CP2_HSH_DATW+56(a0)
225 sd t1, OCTEON_CP2_HSH_DATW+64(a0)
227 sd t2, OCTEON_CP2_HSH_DATW+72(a0)
229 sd t3, OCTEON_CP2_HSH_DATW+80(a0)
231 sd t0, OCTEON_CP2_HSH_DATW+88(a0)
233 sd t1, OCTEON_CP2_HSH_DATW+96(a0)
235 sd t2, OCTEON_CP2_HSH_DATW+104(a0)
237 sd t3, OCTEON_CP2_HSH_DATW+112(a0)
239 sd t0, OCTEON_CP2_HSH_IVW(a0)
241 sd t1, OCTEON_CP2_HSH_IVW+8(a0)
243 sd t2, OCTEON_CP2_HSH_IVW+16(a0)
245 sd t3, OCTEON_CP2_HSH_IVW+24(a0)
247 sd t0, OCTEON_CP2_HSH_IVW+32(a0)
249 sd t1, OCTEON_CP2_HSH_IVW+40(a0)
251 sd t2, OCTEON_CP2_HSH_IVW+48(a0)
253 sd t3, OCTEON_CP2_HSH_IVW+56(a0)
255 sd t0, OCTEON_CP2_GFM_MULT(a0)
257 sd t1, OCTEON_CP2_GFM_MULT+8(a0)
258 sd t2, OCTEON_CP2_GFM_POLY(a0)
259 sd t3, OCTEON_CP2_GFM_RESULT(a0)
260 sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
263 2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
268 sd t3, OCTEON_CP2_HSH_DATW(a0)
270 sd t0, OCTEON_CP2_HSH_DATW+8(a0)
272 sd t1, OCTEON_CP2_HSH_DATW+16(a0)
274 sd t2, OCTEON_CP2_HSH_DATW+24(a0)
276 sd t3, OCTEON_CP2_HSH_DATW+32(a0)
278 sd t0, OCTEON_CP2_HSH_DATW+40(a0)
280 sd t1, OCTEON_CP2_HSH_DATW+48(a0)
281 sd t2, OCTEON_CP2_HSH_IVW(a0)
282 sd t3, OCTEON_CP2_HSH_IVW+8(a0)
283 sd t0, OCTEON_CP2_HSH_IVW+16(a0)
285 3: /* pass 1 or CvmCtl[NOCRYPTO] set */
287 END(octeon_cop2_save)
290 * void octeon_cop2_restore(struct octeon_cop2_state *a0)
295 LEAF(octeon_cop2_restore)
296 /* First cache line was prefetched before the call */
298 dmfc0 t9, $9,7 /* CvmCtl register. */
301 ld t0, OCTEON_CP2_CRC_IV(a0)
303 ld t1, OCTEON_CP2_CRC_LENGTH(a0)
304 ld t2, OCTEON_CP2_CRC_POLY(a0)
306 /* Restore the COP2 CRC state */
309 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
312 /* Restore the LLM state */
313 ld t0, OCTEON_CP2_LLM_DAT(a0)
314 ld t1, OCTEON_CP2_LLM_DAT+8(a0)
319 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
322 /* Restore the COP2 crypto state common to pass 1 and pass 2 */
323 ld t0, OCTEON_CP2_3DES_IV(a0)
324 ld t1, OCTEON_CP2_3DES_KEY(a0)
325 ld t2, OCTEON_CP2_3DES_KEY+8(a0)
327 ld t0, OCTEON_CP2_3DES_KEY+16(a0)
329 ld t1, OCTEON_CP2_3DES_RESULT(a0)
331 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
333 ld t0, OCTEON_CP2_AES_IV(a0)
335 ld t1, OCTEON_CP2_AES_IV+8(a0)
336 dmtc2 t2, 0x010A /* only really needed for pass 1 */
337 ld t2, OCTEON_CP2_AES_KEY(a0)
339 ld t0, OCTEON_CP2_AES_KEY+8(a0)
341 ld t1, OCTEON_CP2_AES_KEY+16(a0)
343 ld t2, OCTEON_CP2_AES_KEY+24(a0)
345 ld t0, OCTEON_CP2_AES_KEYLEN(a0)
347 ld t1, OCTEON_CP2_AES_RESULT(a0)
349 ld t2, OCTEON_CP2_AES_RESULT+8(a0)
350 mfc0 t3, $15,0 /* Get the processor ID register */
352 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
354 bne t0, t3, 3f /* Skip the next stuff for non-pass1 */
357 /* this code is specific for pass 1 */
358 ld t0, OCTEON_CP2_HSH_DATW(a0)
359 ld t1, OCTEON_CP2_HSH_DATW+8(a0)
360 ld t2, OCTEON_CP2_HSH_DATW+16(a0)
362 ld t0, OCTEON_CP2_HSH_DATW+24(a0)
364 ld t1, OCTEON_CP2_HSH_DATW+32(a0)
366 ld t2, OCTEON_CP2_HSH_DATW+40(a0)
368 ld t0, OCTEON_CP2_HSH_DATW+48(a0)
370 ld t1, OCTEON_CP2_HSH_IVW(a0)
372 ld t2, OCTEON_CP2_HSH_IVW+8(a0)
374 ld t0, OCTEON_CP2_HSH_IVW+16(a0)
377 b done_restore /* unconditional branch */
380 3: /* this is post-pass1 code */
381 ld t2, OCTEON_CP2_HSH_DATW(a0)
382 ld t0, OCTEON_CP2_HSH_DATW+8(a0)
383 ld t1, OCTEON_CP2_HSH_DATW+16(a0)
385 ld t2, OCTEON_CP2_HSH_DATW+24(a0)
387 ld t0, OCTEON_CP2_HSH_DATW+32(a0)
389 ld t1, OCTEON_CP2_HSH_DATW+40(a0)
391 ld t2, OCTEON_CP2_HSH_DATW+48(a0)
393 ld t0, OCTEON_CP2_HSH_DATW+56(a0)
395 ld t1, OCTEON_CP2_HSH_DATW+64(a0)
397 ld t2, OCTEON_CP2_HSH_DATW+72(a0)
399 ld t0, OCTEON_CP2_HSH_DATW+80(a0)
401 ld t1, OCTEON_CP2_HSH_DATW+88(a0)
403 ld t2, OCTEON_CP2_HSH_DATW+96(a0)
405 ld t0, OCTEON_CP2_HSH_DATW+104(a0)
407 ld t1, OCTEON_CP2_HSH_DATW+112(a0)
409 ld t2, OCTEON_CP2_HSH_IVW(a0)
411 ld t0, OCTEON_CP2_HSH_IVW+8(a0)
413 ld t1, OCTEON_CP2_HSH_IVW+16(a0)
415 ld t2, OCTEON_CP2_HSH_IVW+24(a0)
417 ld t0, OCTEON_CP2_HSH_IVW+32(a0)
419 ld t1, OCTEON_CP2_HSH_IVW+40(a0)
421 ld t2, OCTEON_CP2_HSH_IVW+48(a0)
423 ld t0, OCTEON_CP2_HSH_IVW+56(a0)
425 ld t1, OCTEON_CP2_GFM_MULT(a0)
427 ld t2, OCTEON_CP2_GFM_MULT+8(a0)
429 ld t0, OCTEON_CP2_GFM_POLY(a0)
431 ld t1, OCTEON_CP2_GFM_RESULT(a0)
433 ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
441 END(octeon_cop2_restore)
445 * void octeon_mult_save()
446 * sp is assumed to point to a struct pt_regs
448 * NOTE: This is called in SAVE_TEMP in stackframe.h. It can
449 * safely modify v1,k0, k1,$10-$15, and $24. It will
450 * be overwritten with a processor specific version of the code.
455 LEAF(octeon_mult_save)
459 octeon_mult_save_end:
460 EXPORT(octeon_mult_save_end)
461 END(octeon_mult_save)
463 LEAF(octeon_mult_save2)
464 /* Save the multiplier state OCTEON II and earlier*/
467 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
469 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
472 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
474 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
476 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
478 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
479 octeon_mult_save2_end:
480 EXPORT(octeon_mult_save2_end)
481 END(octeon_mult_save2)
483 LEAF(octeon_mult_save3)
484 /* Save the multiplier state OCTEON III */
485 v3mulu $10, $0, $0 /* read P0 */
486 v3mulu $11, $0, $0 /* read P1 */
487 v3mulu $12, $0, $0 /* read P2 */
488 sd $10, PT_MTP+(0*8)(sp) /* store P0 */
489 v3mulu $10, $0, $0 /* read P3 */
490 sd $11, PT_MTP+(1*8)(sp) /* store P1 */
491 v3mulu $11, $0, $0 /* read P4 */
492 sd $12, PT_MTP+(2*8)(sp) /* store P2 */
494 v3mulu $12, $0, $0 /* read P5 */
495 sd $10, PT_MTP+(3*8)(sp) /* store P3 */
496 v3mulu $13, $13, $0 /* P4-P0 = MPL5-MPL1, $13 = MPL0 */
497 sd $11, PT_MTP+(4*8)(sp) /* store P4 */
498 v3mulu $10, $0, $0 /* read MPL1 */
499 sd $12, PT_MTP+(5*8)(sp) /* store P5 */
500 v3mulu $11, $0, $0 /* read MPL2 */
501 sd $13, PT_MPL+(0*8)(sp) /* store MPL0 */
502 v3mulu $12, $0, $0 /* read MPL3 */
503 sd $10, PT_MPL+(1*8)(sp) /* store MPL1 */
504 v3mulu $10, $0, $0 /* read MPL4 */
505 sd $11, PT_MPL+(2*8)(sp) /* store MPL2 */
506 v3mulu $11, $0, $0 /* read MPL5 */
507 sd $12, PT_MPL+(3*8)(sp) /* store MPL3 */
508 sd $10, PT_MPL+(4*8)(sp) /* store MPL4 */
510 sd $11, PT_MPL+(5*8)(sp) /* store MPL5 */
511 octeon_mult_save3_end:
512 EXPORT(octeon_mult_save3_end)
513 END(octeon_mult_save3)
517 * void octeon_mult_restore()
518 * sp is assumed to point to a struct pt_regs
520 * NOTE: This is called in RESTORE_TEMP in stackframe.h.
525 LEAF(octeon_mult_restore)
529 octeon_mult_restore_end:
530 EXPORT(octeon_mult_restore_end)
531 END(octeon_mult_restore)
533 LEAF(octeon_mult_restore2)
534 ld v0, PT_MPL(sp) /* MPL0 */
535 ld v1, PT_MPL+8(sp) /* MPL1 */
536 ld k0, PT_MPL+16(sp) /* MPL2 */
537 /* Restore the multiplier state */
538 ld k1, PT_MTP+16(sp) /* P2 */
540 ld v0, PT_MTP+8(sp) /* P1 */
542 ld v1, PT_MTP(sp) /* P0 */
548 octeon_mult_restore2_end:
549 EXPORT(octeon_mult_restore2_end)
550 END(octeon_mult_restore2)
552 LEAF(octeon_mult_restore3)
553 ld $12, PT_MPL+(0*8)(sp) /* read MPL0 */
554 ld $13, PT_MPL+(3*8)(sp) /* read MPL3 */
555 ld $10, PT_MPL+(1*8)(sp) /* read MPL1 */
556 ld $11, PT_MPL+(4*8)(sp) /* read MPL4 */
558 /* mtm0 $12, $13 restore MPL0 and MPL3 */
559 ld $12, PT_MPL+(2*8)(sp) /* read MPL2 */
561 /* mtm1 $10, $11 restore MPL1 and MPL4 */
562 ld $13, PT_MPL+(5*8)(sp) /* read MPL5 */
563 ld $10, PT_MTP+(0*8)(sp) /* read P0 */
564 ld $11, PT_MTP+(3*8)(sp) /* read P3 */
566 /* mtm2 $12, $13 restore MPL2 and MPL5 */
567 ld $12, PT_MTP+(1*8)(sp) /* read P1 */
569 /* mtp0 $10, $11 restore P0 and P3 */
570 ld $13, PT_MTP+(4*8)(sp) /* read P4 */
571 ld $10, PT_MTP+(2*8)(sp) /* read P2 */
572 ld $11, PT_MTP+(5*8)(sp) /* read P5 */
574 /* mtp1 $12, $13 restore P1 and P4 */
577 /* mtp2 $10, $11 restore P2 and P5 */
579 octeon_mult_restore3_end:
580 EXPORT(octeon_mult_restore3_end)
581 END(octeon_mult_restore3)