2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * written by Carsten Langgaard, carstenl@mips.com
14 #define USE_ALTERNATE_RESUME_IMPL 1
17 #include "r4k_switch.S"
20 * task_struct *resume(task_struct *prev, task_struct *next,
21 * struct thread_info *next_ti, int usedfpu)
27 LONG_S t1, THREAD_STATUS(a0)
28 cpu_save_nonscratch a0
29 LONG_S ra, THREAD_REG31(a0)
32 * check if we need to save FPU registers
37 PTR_L t3, TASK_THREAD_INFO(a0)
41 * clear saved user stack CU1 bit
50 fpu_save_double a0 t0 t1 # c0_status passed in t0
55 /* check if we need to save COP2 registers */
59 /* Disable COP2 in the stored process state */
64 /* Enable COP2 so we can save it */
74 /* Disable COP2 now that we are done */
81 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
82 /* Check if we need to store CVMSEG state */
83 mfc0 t0, $11,7 /* CvmMemCtl */
84 bbit0 t0, 6, 3f /* Is user access enabled? */
86 /* Store the CVMSEG state */
87 /* Extract the size of CVMSEG */
89 /* Multiply * (cache line size/sizeof(long)/2) */
91 li t1, -32768 /* Base address of CVMSEG */
92 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
96 LONG_L t8, 0(t1) /* Load from CVMSEG */
97 subu t0, 1 /* Decrement loop var */
98 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
99 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
100 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
101 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
102 bnez t0, 2b /* Loop until we've copied it all */
103 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
106 /* Disable access to CVMSEG */
107 mfc0 t0, $11,7 /* CvmMemCtl */
108 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
109 mtc0 t0, $11,7 /* CvmMemCtl */
113 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
114 PTR_LA t8, __stack_chk_guard
115 LONG_L t9, TASK_STACK_CANARY(a1)
120 * The order of restoring the registers takes care of the race
121 * updating $28, $29 and kernelsp without disabling ints.
124 cpu_restore_nonscratch a1
126 PTR_ADDU t0, $28, _THREAD_SIZE - 32
127 set_saved_sp t0, t1, t2
129 mfc0 t1, CP0_STATUS /* Do we really need this? */
132 LONG_L a2, THREAD_STATUS(a1)
142 * void octeon_cop2_save(struct octeon_cop2_state *a0)
147 LEAF(octeon_cop2_save)
149 dmfc0 t9, $9,7 /* CvmCtl register. */
151 /* Save the COP2 CRC state */
155 sd t0, OCTEON_CP2_CRC_IV(a0)
156 sd t1, OCTEON_CP2_CRC_LENGTH(a0)
157 /* Skip next instructions if CvmCtl[NODFA_CP2] set */
159 sd t2, OCTEON_CP2_CRC_POLY(a0)
161 /* Save the LLM state */
164 sd t0, OCTEON_CP2_LLM_DAT(a0)
166 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
167 sd t1, OCTEON_CP2_LLM_DAT+8(a0)
169 /* Save the COP2 crypto state */
170 /* this part is mostly common to both pass 1 and later revisions */
175 sd t0, OCTEON_CP2_3DES_IV(a0)
177 sd t1, OCTEON_CP2_3DES_KEY(a0)
178 dmfc2 t1, 0x0111 /* only necessary for pass 1 */
179 sd t2, OCTEON_CP2_3DES_KEY+8(a0)
181 sd t3, OCTEON_CP2_3DES_KEY+16(a0)
183 sd t0, OCTEON_CP2_3DES_RESULT(a0)
185 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
187 sd t2, OCTEON_CP2_AES_IV(a0)
189 sd t3, OCTEON_CP2_AES_IV+8(a0)
191 sd t0, OCTEON_CP2_AES_KEY(a0)
193 sd t1, OCTEON_CP2_AES_KEY+8(a0)
195 sd t2, OCTEON_CP2_AES_KEY+16(a0)
197 sd t3, OCTEON_CP2_AES_KEY+24(a0)
198 mfc0 v0, $15,0 /* Get the processor ID register */
199 sd t0, OCTEON_CP2_AES_KEYLEN(a0)
200 li v1, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
201 sd t1, OCTEON_CP2_AES_RESULT(a0)
202 /* Skip to the Pass1 version of the remainder of the COP2 state */
204 sd t2, OCTEON_CP2_AES_RESULT+8(a0)
206 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
209 ori v1, v1, 0x9500 /* lowest OCTEON III PrId*/
211 subu v1, v0, v1 /* prid - lowest OCTEON III PrId */
213 sd t1, OCTEON_CP2_HSH_DATW(a0)
215 sd t2, OCTEON_CP2_HSH_DATW+8(a0)
217 sd t3, OCTEON_CP2_HSH_DATW+16(a0)
219 sd t0, OCTEON_CP2_HSH_DATW+24(a0)
221 sd t1, OCTEON_CP2_HSH_DATW+32(a0)
223 sd t2, OCTEON_CP2_HSH_DATW+40(a0)
225 sd t3, OCTEON_CP2_HSH_DATW+48(a0)
227 sd t0, OCTEON_CP2_HSH_DATW+56(a0)
229 sd t1, OCTEON_CP2_HSH_DATW+64(a0)
231 sd t2, OCTEON_CP2_HSH_DATW+72(a0)
233 sd t3, OCTEON_CP2_HSH_DATW+80(a0)
235 sd t0, OCTEON_CP2_HSH_DATW+88(a0)
237 sd t1, OCTEON_CP2_HSH_DATW+96(a0)
239 sd t2, OCTEON_CP2_HSH_DATW+104(a0)
241 sd t3, OCTEON_CP2_HSH_DATW+112(a0)
243 sd t0, OCTEON_CP2_HSH_IVW(a0)
245 sd t1, OCTEON_CP2_HSH_IVW+8(a0)
247 sd t2, OCTEON_CP2_HSH_IVW+16(a0)
249 sd t3, OCTEON_CP2_HSH_IVW+24(a0)
251 sd t0, OCTEON_CP2_HSH_IVW+32(a0)
253 sd t1, OCTEON_CP2_HSH_IVW+40(a0)
255 sd t2, OCTEON_CP2_HSH_IVW+48(a0)
257 sd t3, OCTEON_CP2_HSH_IVW+56(a0)
259 sd t0, OCTEON_CP2_GFM_MULT(a0)
261 sd t1, OCTEON_CP2_GFM_MULT+8(a0)
262 sd t2, OCTEON_CP2_GFM_POLY(a0)
263 sd t3, OCTEON_CP2_GFM_RESULT(a0)
265 sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
266 /* OCTEON III things*/
269 sd t0, OCTEON_CP2_SHA3(a0)
270 sd t1, OCTEON_CP2_SHA3+8(a0)
275 2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
280 sd t3, OCTEON_CP2_HSH_DATW(a0)
282 sd t0, OCTEON_CP2_HSH_DATW+8(a0)
284 sd t1, OCTEON_CP2_HSH_DATW+16(a0)
286 sd t2, OCTEON_CP2_HSH_DATW+24(a0)
288 sd t3, OCTEON_CP2_HSH_DATW+32(a0)
290 sd t0, OCTEON_CP2_HSH_DATW+40(a0)
292 sd t1, OCTEON_CP2_HSH_DATW+48(a0)
293 sd t2, OCTEON_CP2_HSH_IVW(a0)
294 sd t3, OCTEON_CP2_HSH_IVW+8(a0)
295 sd t0, OCTEON_CP2_HSH_IVW+16(a0)
297 3: /* pass 1 or CvmCtl[NOCRYPTO] set */
300 END(octeon_cop2_save)
304 * void octeon_cop2_restore(struct octeon_cop2_state *a0)
309 LEAF(octeon_cop2_restore)
310 /* First cache line was prefetched before the call */
312 dmfc0 t9, $9,7 /* CvmCtl register. */
315 ld t0, OCTEON_CP2_CRC_IV(a0)
317 ld t1, OCTEON_CP2_CRC_LENGTH(a0)
318 ld t2, OCTEON_CP2_CRC_POLY(a0)
320 /* Restore the COP2 CRC state */
323 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
326 /* Restore the LLM state */
327 ld t0, OCTEON_CP2_LLM_DAT(a0)
328 ld t1, OCTEON_CP2_LLM_DAT+8(a0)
333 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
336 /* Restore the COP2 crypto state common to pass 1 and pass 2 */
337 ld t0, OCTEON_CP2_3DES_IV(a0)
338 ld t1, OCTEON_CP2_3DES_KEY(a0)
339 ld t2, OCTEON_CP2_3DES_KEY+8(a0)
341 ld t0, OCTEON_CP2_3DES_KEY+16(a0)
343 ld t1, OCTEON_CP2_3DES_RESULT(a0)
345 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
347 ld t0, OCTEON_CP2_AES_IV(a0)
349 ld t1, OCTEON_CP2_AES_IV+8(a0)
350 dmtc2 t2, 0x010A /* only really needed for pass 1 */
351 ld t2, OCTEON_CP2_AES_KEY(a0)
353 ld t0, OCTEON_CP2_AES_KEY+8(a0)
355 ld t1, OCTEON_CP2_AES_KEY+16(a0)
357 ld t2, OCTEON_CP2_AES_KEY+24(a0)
359 ld t0, OCTEON_CP2_AES_KEYLEN(a0)
361 ld t1, OCTEON_CP2_AES_RESULT(a0)
363 ld t2, OCTEON_CP2_AES_RESULT+8(a0)
364 mfc0 t3, $15,0 /* Get the processor ID register */
366 li v0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
368 bne v0, t3, 3f /* Skip the next stuff for non-pass1 */
371 /* this code is specific for pass 1 */
372 ld t0, OCTEON_CP2_HSH_DATW(a0)
373 ld t1, OCTEON_CP2_HSH_DATW+8(a0)
374 ld t2, OCTEON_CP2_HSH_DATW+16(a0)
376 ld t0, OCTEON_CP2_HSH_DATW+24(a0)
378 ld t1, OCTEON_CP2_HSH_DATW+32(a0)
380 ld t2, OCTEON_CP2_HSH_DATW+40(a0)
382 ld t0, OCTEON_CP2_HSH_DATW+48(a0)
384 ld t1, OCTEON_CP2_HSH_IVW(a0)
386 ld t2, OCTEON_CP2_HSH_IVW+8(a0)
388 ld t0, OCTEON_CP2_HSH_IVW+16(a0)
391 b done_restore /* unconditional branch */
394 3: /* this is post-pass1 code */
395 ld t2, OCTEON_CP2_HSH_DATW(a0)
396 ori v0, v0, 0x9500 /* lowest OCTEON III PrId*/
397 ld t0, OCTEON_CP2_HSH_DATW+8(a0)
398 ld t1, OCTEON_CP2_HSH_DATW+16(a0)
400 ld t2, OCTEON_CP2_HSH_DATW+24(a0)
402 ld t0, OCTEON_CP2_HSH_DATW+32(a0)
404 ld t1, OCTEON_CP2_HSH_DATW+40(a0)
406 ld t2, OCTEON_CP2_HSH_DATW+48(a0)
408 ld t0, OCTEON_CP2_HSH_DATW+56(a0)
410 ld t1, OCTEON_CP2_HSH_DATW+64(a0)
412 ld t2, OCTEON_CP2_HSH_DATW+72(a0)
414 ld t0, OCTEON_CP2_HSH_DATW+80(a0)
416 ld t1, OCTEON_CP2_HSH_DATW+88(a0)
418 ld t2, OCTEON_CP2_HSH_DATW+96(a0)
420 ld t0, OCTEON_CP2_HSH_DATW+104(a0)
422 ld t1, OCTEON_CP2_HSH_DATW+112(a0)
424 ld t2, OCTEON_CP2_HSH_IVW(a0)
426 ld t0, OCTEON_CP2_HSH_IVW+8(a0)
428 ld t1, OCTEON_CP2_HSH_IVW+16(a0)
430 ld t2, OCTEON_CP2_HSH_IVW+24(a0)
432 ld t0, OCTEON_CP2_HSH_IVW+32(a0)
434 ld t1, OCTEON_CP2_HSH_IVW+40(a0)
436 ld t2, OCTEON_CP2_HSH_IVW+48(a0)
438 ld t0, OCTEON_CP2_HSH_IVW+56(a0)
440 ld t1, OCTEON_CP2_GFM_MULT(a0)
442 ld t2, OCTEON_CP2_GFM_MULT+8(a0)
444 ld t0, OCTEON_CP2_GFM_POLY(a0)
446 ld t1, OCTEON_CP2_GFM_RESULT(a0)
448 ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
450 subu v0, t3, v0 /* prid - lowest OCTEON III PrId */
452 bltz v0, done_restore
454 /* OCTEON III things*/
455 ld t0, OCTEON_CP2_SHA3(a0)
456 ld t1, OCTEON_CP2_SHA3+8(a0)
462 END(octeon_cop2_restore)
466 * void octeon_mult_save()
467 * sp is assumed to point to a struct pt_regs
469 * NOTE: This is called in SAVE_TEMP in stackframe.h. It can
470 * safely modify v1,k0, k1,$10-$15, and $24. It will
471 * be overwritten with a processor specific version of the code.
476 LEAF(octeon_mult_save)
480 octeon_mult_save_end:
481 EXPORT(octeon_mult_save_end)
482 END(octeon_mult_save)
484 LEAF(octeon_mult_save2)
485 /* Save the multiplier state OCTEON II and earlier*/
488 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
490 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
493 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
495 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
497 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
499 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
500 octeon_mult_save2_end:
501 EXPORT(octeon_mult_save2_end)
502 END(octeon_mult_save2)
504 LEAF(octeon_mult_save3)
505 /* Save the multiplier state OCTEON III */
506 v3mulu $10, $0, $0 /* read P0 */
507 v3mulu $11, $0, $0 /* read P1 */
508 v3mulu $12, $0, $0 /* read P2 */
509 sd $10, PT_MTP+(0*8)(sp) /* store P0 */
510 v3mulu $10, $0, $0 /* read P3 */
511 sd $11, PT_MTP+(1*8)(sp) /* store P1 */
512 v3mulu $11, $0, $0 /* read P4 */
513 sd $12, PT_MTP+(2*8)(sp) /* store P2 */
515 v3mulu $12, $0, $0 /* read P5 */
516 sd $10, PT_MTP+(3*8)(sp) /* store P3 */
517 v3mulu $13, $13, $0 /* P4-P0 = MPL5-MPL1, $13 = MPL0 */
518 sd $11, PT_MTP+(4*8)(sp) /* store P4 */
519 v3mulu $10, $0, $0 /* read MPL1 */
520 sd $12, PT_MTP+(5*8)(sp) /* store P5 */
521 v3mulu $11, $0, $0 /* read MPL2 */
522 sd $13, PT_MPL+(0*8)(sp) /* store MPL0 */
523 v3mulu $12, $0, $0 /* read MPL3 */
524 sd $10, PT_MPL+(1*8)(sp) /* store MPL1 */
525 v3mulu $10, $0, $0 /* read MPL4 */
526 sd $11, PT_MPL+(2*8)(sp) /* store MPL2 */
527 v3mulu $11, $0, $0 /* read MPL5 */
528 sd $12, PT_MPL+(3*8)(sp) /* store MPL3 */
529 sd $10, PT_MPL+(4*8)(sp) /* store MPL4 */
531 sd $11, PT_MPL+(5*8)(sp) /* store MPL5 */
532 octeon_mult_save3_end:
533 EXPORT(octeon_mult_save3_end)
534 END(octeon_mult_save3)
538 * void octeon_mult_restore()
539 * sp is assumed to point to a struct pt_regs
541 * NOTE: This is called in RESTORE_TEMP in stackframe.h.
546 LEAF(octeon_mult_restore)
550 octeon_mult_restore_end:
551 EXPORT(octeon_mult_restore_end)
552 END(octeon_mult_restore)
554 LEAF(octeon_mult_restore2)
555 ld v0, PT_MPL(sp) /* MPL0 */
556 ld v1, PT_MPL+8(sp) /* MPL1 */
557 ld k0, PT_MPL+16(sp) /* MPL2 */
558 /* Restore the multiplier state */
559 ld k1, PT_MTP+16(sp) /* P2 */
561 ld v0, PT_MTP+8(sp) /* P1 */
563 ld v1, PT_MTP(sp) /* P0 */
569 octeon_mult_restore2_end:
570 EXPORT(octeon_mult_restore2_end)
571 END(octeon_mult_restore2)
573 LEAF(octeon_mult_restore3)
574 ld $12, PT_MPL+(0*8)(sp) /* read MPL0 */
575 ld $13, PT_MPL+(3*8)(sp) /* read MPL3 */
576 ld $10, PT_MPL+(1*8)(sp) /* read MPL1 */
577 ld $11, PT_MPL+(4*8)(sp) /* read MPL4 */
579 /* mtm0 $12, $13 restore MPL0 and MPL3 */
580 ld $12, PT_MPL+(2*8)(sp) /* read MPL2 */
582 /* mtm1 $10, $11 restore MPL1 and MPL4 */
583 ld $13, PT_MPL+(5*8)(sp) /* read MPL5 */
584 ld $10, PT_MTP+(0*8)(sp) /* read P0 */
585 ld $11, PT_MTP+(3*8)(sp) /* read P3 */
587 /* mtm2 $12, $13 restore MPL2 and MPL5 */
588 ld $12, PT_MTP+(1*8)(sp) /* read P1 */
590 /* mtp0 $10, $11 restore P0 and P3 */
591 ld $13, PT_MTP+(4*8)(sp) /* read P4 */
592 ld $10, PT_MTP+(2*8)(sp) /* read P2 */
593 ld $11, PT_MTP+(5*8)(sp) /* read P5 */
595 /* mtp1 $12, $13 restore P1 and P4 */
598 /* mtp2 $10, $11 restore P2 and P5 */
600 octeon_mult_restore3_end:
601 EXPORT(octeon_mult_restore3_end)
602 END(octeon_mult_restore3)