2 * This program is free software; you can distribute it and/or modify it
3 * under the terms of the GNU General Public License (Version 2) as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15 * Copyright (C) 2007 MIPS Technologies, Inc.
16 * Chris Dearman (chris@mips.com)
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
24 #include <linux/cpumask.h>
25 #include <linux/interrupt.h>
26 #include <linux/compiler.h>
28 #include <asm/atomic.h>
29 #include <asm/cacheflush.h>
31 #include <asm/processor.h>
32 #include <asm/system.h>
33 #include <asm/hardirq.h>
34 #include <asm/mmu_context.h>
37 #include <asm/mipsregs.h>
38 #include <asm/mipsmtregs.h>
39 #include <asm/mips_mt.h>
42 * Crude manipulation of the CPU masks to control which
43 * which CPU's are brought online during initialisation
45 * Beware... this needs to be called after CPU discovery
46 * but before CPU bringup
48 static int __init allowcpus(char *str)
50 cpumask_t cpu_allow_map;
54 cpus_clear(cpu_allow_map);
55 if (cpulist_parse(str, &cpu_allow_map) == 0) {
56 cpu_set(0, cpu_allow_map);
57 cpus_and(cpu_possible_map, cpu_possible_map, cpu_allow_map);
58 len = cpulist_scnprintf(buf, sizeof(buf)-1, &cpu_possible_map);
60 pr_debug("Allowable CPUs: %s\n", buf);
65 __setup("allowcpus=", allowcpus);
67 static void ipi_call_function(unsigned int cpu)
69 unsigned int action = 0;
71 pr_debug("CPU%d: %s cpu %d status %08x\n",
72 smp_processor_id(), __func__, cpu, read_c0_status());
76 action = GIC_IPI_EXT_INTR_CALLFNC_VPE0;
79 action = GIC_IPI_EXT_INTR_CALLFNC_VPE1;
82 action = GIC_IPI_EXT_INTR_CALLFNC_VPE2;
85 action = GIC_IPI_EXT_INTR_CALLFNC_VPE3;
92 static void ipi_resched(unsigned int cpu)
94 unsigned int action = 0;
96 pr_debug("CPU%d: %s cpu %d status %08x\n",
97 smp_processor_id(), __func__, cpu, read_c0_status());
101 action = GIC_IPI_EXT_INTR_RESCHED_VPE0;
104 action = GIC_IPI_EXT_INTR_RESCHED_VPE1;
107 action = GIC_IPI_EXT_INTR_RESCHED_VPE2;
110 action = GIC_IPI_EXT_INTR_RESCHED_VPE3;
113 gic_send_ipi(action);
117 * FIXME: This isn't restricted to CMP
118 * The SMVP kernel could use GIC interrupts if available
120 void cmp_send_ipi_single(int cpu, unsigned int action)
124 local_irq_save(flags);
127 case SMP_CALL_FUNCTION:
128 ipi_call_function(cpu);
131 case SMP_RESCHEDULE_YOURSELF:
136 local_irq_restore(flags);
139 static void cmp_send_ipi_mask(cpumask_t mask, unsigned int action)
143 for_each_cpu_mask(i, mask)
144 cmp_send_ipi_single(i, action);
147 static void cmp_init_secondary(void)
149 struct cpuinfo_mips *c = ¤t_cpu_data;
151 /* Assume GIC is present */
152 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
155 /* Enable per-cpu interrupts: platform specific */
157 c->core = (read_c0_ebase() >> 1) & 0xff;
158 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
159 c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
161 #ifdef CONFIG_MIPS_MT_SMTC
162 c->tc_id = (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC;
166 static void cmp_smp_finish(void)
168 pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
170 /* CDFIXME: remove this? */
171 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
173 #ifdef CONFIG_MIPS_MT_FPAFF
174 /* If we have an FPU, enroll ourselves in the FPU-full mask */
176 cpu_set(smp_processor_id(), mt_fpu_cpumask);
177 #endif /* CONFIG_MIPS_MT_FPAFF */
182 static void cmp_cpus_done(void)
184 pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
188 * Setup the PC, SP, and GP of a secondary processor and start it running
189 * smp_bootstrap is the place to resume from
190 * __KSTK_TOS(idle) is apparently the stack pointer
191 * (unsigned long)idle->thread_info the gp
193 static void cmp_boot_secondary(int cpu, struct task_struct *idle)
195 struct thread_info *gp = task_thread_info(idle);
196 unsigned long sp = __KSTK_TOS(idle);
197 unsigned long pc = (unsigned long)&smp_bootstrap;
198 unsigned long a0 = 0;
200 pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
205 flush_icache_range((unsigned long)gp,
206 (unsigned long)(gp + sizeof(struct thread_info)));
209 amon_cpu_start(cpu, pc, sp, gp, a0);
213 * Common setup before any secondaries are started
215 void __init cmp_smp_setup(void)
220 pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
222 #ifdef CONFIG_MIPS_MT_FPAFF
223 /* If we have an FPU, enroll ourselves in the FPU-full mask */
225 cpu_set(0, mt_fpu_cpumask);
226 #endif /* CONFIG_MIPS_MT_FPAFF */
228 for (i = 1; i < NR_CPUS; i++) {
229 if (amon_cpu_avail(i)) {
230 cpu_set(i, cpu_possible_map);
231 __cpu_number_map[i] = ++ncpu;
232 __cpu_logical_map[ncpu] = i;
236 if (cpu_has_mipsmt) {
237 unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
239 nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
240 smp_num_siblings = nvpe;
242 pr_info("Detected %i available secondary CPU(s)\n", ncpu);
245 void __init cmp_prepare_cpus(unsigned int max_cpus)
247 pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
248 smp_processor_id(), __func__, max_cpus);
251 * FIXME: some of these options are per-system, some per-core and
254 mips_mt_set_cpuoptions();
257 struct plat_smp_ops cmp_smp_ops = {
258 .send_ipi_single = cmp_send_ipi_single,
259 .send_ipi_mask = cmp_send_ipi_mask,
260 .init_secondary = cmp_init_secondary,
261 .smp_finish = cmp_smp_finish,
262 .cpus_done = cmp_cpus_done,
263 .boot_secondary = cmp_boot_secondary,
264 .smp_setup = cmp_smp_setup,
265 .prepare_cpus = cmp_prepare_cpus,