2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
14 #include <asm/addrspace.h>
15 #include <asm/cacheops.h>
17 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
18 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
27 #define INDEX_BASE CKSEG0
29 .macro f_fill64 dst, offset, val
30 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
31 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
32 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
33 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
34 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
35 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
36 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
37 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
39 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
40 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
41 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
42 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
43 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
44 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
45 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
46 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
51 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
53 LEAF(mips_init_icache)
56 /* clear tag to invalidate */
59 1: cache INDEX_STORE_TAG_I, 0(t0)
62 /* fill once, so data field parity is correct */
67 /* invalidate again - prudent but not strictly neccessary */
69 1: cache INDEX_STORE_TAG_I, 0(t0)
76 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
78 LEAF(mips_init_dcache)
84 1: cache INDEX_STORE_TAG_D, 0(t0)
87 /* load from each line (in cached space) */
94 1: cache INDEX_STORE_TAG_D, 0(t0)
101 * mips_cache_reset - low level initialisation of the primary caches
103 * This routine initialises the primary caches to ensure that they have good
104 * parity. It must be called by the ROM before any cached locations are used
105 * to prevent the possibility of data with bad parity being written to memory.
107 * To initialise the instruction cache it is essential that a source of data
108 * with good parity is available. This routine will initialise an area of
109 * memory starting at location zero to be used as a source of parity.
114 NESTED(mips_cache_reset, 0, ra)
117 #if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \
118 !defined(CONFIG_SYS_CACHELINE_SIZE)
119 /* read Config1 for use below */
120 mfc0 t5, CP0_CONFIG, 1
123 #ifdef CONFIG_SYS_CACHELINE_SIZE
124 li t9, CONFIG_SYS_CACHELINE_SIZE
125 li t8, CONFIG_SYS_CACHELINE_SIZE
127 /* Detect I-cache line size. */
128 srl t8, t5, MIPS_CONF1_IL_SHIFT
129 andi t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT)
134 1: /* Detect D-cache line size. */
135 srl t9, t5, MIPS_CONF1_DL_SHIFT
136 andi t9, t9, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
143 #ifdef CONFIG_SYS_ICACHE_SIZE
144 li t2, CONFIG_SYS_ICACHE_SIZE
146 /* Detect I-cache size. */
147 srl t6, t5, MIPS_CONF1_IS_SHIFT
148 andi t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT)
154 1: /* At this point t4 == I-cache sets. */
156 srl t6, t5, MIPS_CONF1_IA_SHIFT
157 andi t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT)
159 /* At this point t6 == I-cache ways. */
163 #ifdef CONFIG_SYS_DCACHE_SIZE
164 li t3, CONFIG_SYS_DCACHE_SIZE
166 /* Detect D-cache size. */
167 srl t6, t5, MIPS_CONF1_DS_SHIFT
168 andi t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
174 1: /* At this point t4 == I-cache sets. */
176 srl t6, t5, MIPS_CONF1_DA_SHIFT
177 andi t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
179 /* At this point t6 == I-cache ways. */
183 /* Determine the largest L1 cache size */
184 #if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
185 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
186 li v0, CONFIG_SYS_ICACHE_SIZE
188 li v0, CONFIG_SYS_DCACHE_SIZE
196 * Now clear that much memory starting from zero.
201 f_fill64 a0, -64, zero
205 * The caches are probably in an indeterminate state,
206 * so we force good parity into them by doing an
207 * invalidate, load/fill, invalidate for each line.
211 * Assume bottom of RAM will generate good parity for the cache.
215 * Initialize the I-cache first,
219 PTR_LA v1, mips_init_icache
223 * then initialize D-cache.
227 PTR_LA v1, mips_init_dcache
231 END(mips_cache_reset)
234 * dcache_status - get cache status
236 * RETURNS: 0 - cache disabled; 1 - cache enabled
241 li t1, CONF_CM_UNCACHED
242 andi t0, t0, CONF_CM_CMASK
250 * dcache_disable - disable cache
259 ori t0, t0, CONF_CM_UNCACHED
265 * dcache_enable - enable cache
272 ori t0, CONF_CM_CMASK
273 xori t0, CONF_CM_CMASK
274 ori t0, CONFIG_SYS_MIPS_CACHE_MODE