2 * Just-In-Time compiler for BPF filters on MIPS
4 * Copyright (c) 2014 Imagination Technologies Ltd.
5 * Author: Markos Chandras <markos.chandras@imgtec.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2 of the License.
12 #include <linux/bitops.h>
13 #include <linux/compiler.h>
14 #include <linux/errno.h>
15 #include <linux/filter.h>
16 #include <linux/if_vlan.h>
17 #include <linux/kconfig.h>
18 #include <linux/moduleloader.h>
19 #include <linux/netdevice.h>
20 #include <linux/string.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <asm/bitops.h>
24 #include <asm/cacheflush.h>
25 #include <asm/cpu-features.h>
32 * s0 1st scratch register
33 * s1 2nd scratch register
40 * On entry (*bpf_func)(*skb, *filter)
41 * a0 = MIPS_R_A0 = skb;
42 * a1 = MIPS_R_A1 = filter;
54 * saved reg 0 <-- r_sp
59 * <--------------------- len ------------------------>
60 * <--skb-len(r_skb_hl)-->< ----- skb->data_len ------>
61 * ----------------------------------------------------
63 * ----------------------------------------------------
66 #define RSIZE (sizeof(unsigned long))
67 #define ptr typeof(unsigned long)
69 /* ABI specific return values */
70 #ifdef CONFIG_32BIT /* O32 */
71 #ifdef CONFIG_CPU_LITTLE_ENDIAN
72 #define r_err MIPS_R_V1
73 #define r_val MIPS_R_V0
74 #else /* CONFIG_CPU_LITTLE_ENDIAN */
75 #define r_err MIPS_R_V0
76 #define r_val MIPS_R_V1
79 #define r_err MIPS_R_V0
80 #define r_val MIPS_R_V0
83 #define r_ret MIPS_R_V0
86 * Use 2 scratch registers to avoid pipeline interlocks.
87 * There is no overhead during epilogue and prologue since
88 * any of the $s0-$s6 registers will only be preserved if
89 * they are going to actually be used.
91 #define r_s0 MIPS_R_S0 /* scratch reg 1 */
92 #define r_s1 MIPS_R_S1 /* scratch reg 2 */
93 #define r_off MIPS_R_S2
96 #define r_skb MIPS_R_S5
98 #define r_tmp_imm MIPS_R_T6 /* No need to preserve this */
99 #define r_tmp MIPS_R_T7 /* No need to preserve this */
100 #define r_zero MIPS_R_ZERO
101 #define r_sp MIPS_R_SP
102 #define r_ra MIPS_R_RA
104 #define SCRATCH_OFF(k) (4 * (k))
107 #define SEEN_CALL (1 << BPF_MEMWORDS)
108 #define SEEN_SREG_SFT (BPF_MEMWORDS + 1)
109 #define SEEN_SREG_BASE (1 << SEEN_SREG_SFT)
110 #define SEEN_SREG(x) (SEEN_SREG_BASE << (x))
111 #define SEEN_S0 SEEN_SREG(0)
112 #define SEEN_S1 SEEN_SREG(1)
113 #define SEEN_OFF SEEN_SREG(2)
114 #define SEEN_A SEEN_SREG(3)
115 #define SEEN_X SEEN_SREG(4)
116 #define SEEN_SKB SEEN_SREG(5)
117 #define SEEN_MEM SEEN_SREG(6)
119 /* Arguments used by JIT */
120 #define ARGS_USED_BY_JIT 2 /* only applicable to 64-bit */
122 #define SBIT(x) (1 << (x)) /* Signed version of BIT() */
125 * struct jit_ctx - JIT context
126 * @skf: The sk_filter
127 * @prologue_bytes: Number of bytes for prologue
128 * @idx: Instruction index
130 * @offsets: Instruction offsets
131 * @target: Memory location for the compiled filter
134 const struct sk_filter *skf;
135 unsigned int prologue_bytes;
143 static inline int optimize_div(u32 *k)
145 /* power of 2 divides can be implemented with right shift */
146 if (!(*k & (*k-1))) {
154 static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx);
156 /* Simply emit the instruction if the JIT memory space has been allocated */
157 #define emit_instr(ctx, func, ...) \
159 if ((ctx)->target != NULL) { \
160 u32 *p = &(ctx)->target[ctx->idx]; \
161 uasm_i_##func(&p, ##__VA_ARGS__); \
166 /* Determine if immediate is within the 16-bit signed range */
167 static inline bool is_range16(s32 imm)
169 return !(imm >= SBIT(15) || imm < -SBIT(15));
172 static inline void emit_addu(unsigned int dst, unsigned int src1,
173 unsigned int src2, struct jit_ctx *ctx)
175 emit_instr(ctx, addu, dst, src1, src2);
178 static inline void emit_nop(struct jit_ctx *ctx)
180 emit_instr(ctx, nop);
183 /* Load a u32 immediate to a register */
184 static inline void emit_load_imm(unsigned int dst, u32 imm, struct jit_ctx *ctx)
186 if (ctx->target != NULL) {
187 /* addiu can only handle s16 */
188 if (!is_range16(imm)) {
189 u32 *p = &ctx->target[ctx->idx];
190 uasm_i_lui(&p, r_tmp_imm, (s32)imm >> 16);
191 p = &ctx->target[ctx->idx + 1];
192 uasm_i_ori(&p, dst, r_tmp_imm, imm & 0xffff);
194 u32 *p = &ctx->target[ctx->idx];
195 uasm_i_addiu(&p, dst, r_zero, imm);
200 if (!is_range16(imm))
204 static inline void emit_or(unsigned int dst, unsigned int src1,
205 unsigned int src2, struct jit_ctx *ctx)
207 emit_instr(ctx, or, dst, src1, src2);
210 static inline void emit_ori(unsigned int dst, unsigned src, u32 imm,
213 if (imm >= BIT(16)) {
214 emit_load_imm(r_tmp, imm, ctx);
215 emit_or(dst, src, r_tmp, ctx);
217 emit_instr(ctx, ori, dst, src, imm);
222 static inline void emit_daddu(unsigned int dst, unsigned int src1,
223 unsigned int src2, struct jit_ctx *ctx)
225 emit_instr(ctx, daddu, dst, src1, src2);
228 static inline void emit_daddiu(unsigned int dst, unsigned int src,
229 int imm, struct jit_ctx *ctx)
232 * Only used for stack, so the imm is relatively small
233 * and it fits in 15-bits
235 emit_instr(ctx, daddiu, dst, src, imm);
238 static inline void emit_addiu(unsigned int dst, unsigned int src,
239 u32 imm, struct jit_ctx *ctx)
241 if (!is_range16(imm)) {
242 emit_load_imm(r_tmp, imm, ctx);
243 emit_addu(dst, r_tmp, src, ctx);
245 emit_instr(ctx, addiu, dst, src, imm);
249 static inline void emit_and(unsigned int dst, unsigned int src1,
250 unsigned int src2, struct jit_ctx *ctx)
252 emit_instr(ctx, and, dst, src1, src2);
255 static inline void emit_andi(unsigned int dst, unsigned int src,
256 u32 imm, struct jit_ctx *ctx)
258 /* If imm does not fit in u16 then load it to register */
259 if (imm >= BIT(16)) {
260 emit_load_imm(r_tmp, imm, ctx);
261 emit_and(dst, src, r_tmp, ctx);
263 emit_instr(ctx, andi, dst, src, imm);
267 static inline void emit_xor(unsigned int dst, unsigned int src1,
268 unsigned int src2, struct jit_ctx *ctx)
270 emit_instr(ctx, xor, dst, src1, src2);
273 static inline void emit_xori(ptr dst, ptr src, u32 imm, struct jit_ctx *ctx)
275 /* If imm does not fit in u16 then load it to register */
276 if (imm >= BIT(16)) {
277 emit_load_imm(r_tmp, imm, ctx);
278 emit_xor(dst, src, r_tmp, ctx);
280 emit_instr(ctx, xori, dst, src, imm);
284 static inline void emit_stack_offset(int offset, struct jit_ctx *ctx)
286 if (config_enabled(CONFIG_64BIT))
287 emit_instr(ctx, daddiu, r_sp, r_sp, offset);
289 emit_instr(ctx, addiu, r_sp, r_sp, offset);
293 static inline void emit_subu(unsigned int dst, unsigned int src1,
294 unsigned int src2, struct jit_ctx *ctx)
296 emit_instr(ctx, subu, dst, src1, src2);
299 static inline void emit_neg(unsigned int reg, struct jit_ctx *ctx)
301 emit_subu(reg, r_zero, reg, ctx);
304 static inline void emit_sllv(unsigned int dst, unsigned int src,
305 unsigned int sa, struct jit_ctx *ctx)
307 emit_instr(ctx, sllv, dst, src, sa);
310 static inline void emit_sll(unsigned int dst, unsigned int src,
311 unsigned int sa, struct jit_ctx *ctx)
313 /* sa is 5-bits long */
315 /* Shifting >= 32 results in zero */
316 emit_jit_reg_move(dst, r_zero, ctx);
318 emit_instr(ctx, sll, dst, src, sa);
321 static inline void emit_srlv(unsigned int dst, unsigned int src,
322 unsigned int sa, struct jit_ctx *ctx)
324 emit_instr(ctx, srlv, dst, src, sa);
327 static inline void emit_srl(unsigned int dst, unsigned int src,
328 unsigned int sa, struct jit_ctx *ctx)
330 /* sa is 5-bits long */
332 /* Shifting >= 32 results in zero */
333 emit_jit_reg_move(dst, r_zero, ctx);
335 emit_instr(ctx, srl, dst, src, sa);
338 static inline void emit_slt(unsigned int dst, unsigned int src1,
339 unsigned int src2, struct jit_ctx *ctx)
341 emit_instr(ctx, slt, dst, src1, src2);
344 static inline void emit_sltu(unsigned int dst, unsigned int src1,
345 unsigned int src2, struct jit_ctx *ctx)
347 emit_instr(ctx, sltu, dst, src1, src2);
350 static inline void emit_sltiu(unsigned dst, unsigned int src,
351 unsigned int imm, struct jit_ctx *ctx)
353 /* 16 bit immediate */
354 if (!is_range16((s32)imm)) {
355 emit_load_imm(r_tmp, imm, ctx);
356 emit_sltu(dst, src, r_tmp, ctx);
358 emit_instr(ctx, sltiu, dst, src, imm);
363 /* Store register on the stack */
364 static inline void emit_store_stack_reg(ptr reg, ptr base,
368 if (config_enabled(CONFIG_64BIT))
369 emit_instr(ctx, sd, reg, offset, base);
371 emit_instr(ctx, sw, reg, offset, base);
374 static inline void emit_store(ptr reg, ptr base, unsigned int offset,
377 emit_instr(ctx, sw, reg, offset, base);
380 static inline void emit_load_stack_reg(ptr reg, ptr base,
384 if (config_enabled(CONFIG_64BIT))
385 emit_instr(ctx, ld, reg, offset, base);
387 emit_instr(ctx, lw, reg, offset, base);
390 static inline void emit_load(unsigned int reg, unsigned int base,
391 unsigned int offset, struct jit_ctx *ctx)
393 emit_instr(ctx, lw, reg, offset, base);
396 static inline void emit_load_byte(unsigned int reg, unsigned int base,
397 unsigned int offset, struct jit_ctx *ctx)
399 emit_instr(ctx, lb, reg, offset, base);
402 static inline void emit_half_load(unsigned int reg, unsigned int base,
403 unsigned int offset, struct jit_ctx *ctx)
405 emit_instr(ctx, lh, reg, offset, base);
408 static inline void emit_mul(unsigned int dst, unsigned int src1,
409 unsigned int src2, struct jit_ctx *ctx)
411 emit_instr(ctx, mul, dst, src1, src2);
414 static inline void emit_div(unsigned int dst, unsigned int src,
417 if (ctx->target != NULL) {
418 u32 *p = &ctx->target[ctx->idx];
419 uasm_i_divu(&p, dst, src);
420 p = &ctx->target[ctx->idx + 1];
421 uasm_i_mflo(&p, dst);
423 ctx->idx += 2; /* 2 insts */
426 static inline void emit_mod(unsigned int dst, unsigned int src,
429 if (ctx->target != NULL) {
430 u32 *p = &ctx->target[ctx->idx];
431 uasm_i_divu(&p, dst, src);
432 p = &ctx->target[ctx->idx + 1];
433 uasm_i_mflo(&p, dst);
435 ctx->idx += 2; /* 2 insts */
438 static inline void emit_dsll(unsigned int dst, unsigned int src,
439 unsigned int sa, struct jit_ctx *ctx)
441 emit_instr(ctx, dsll, dst, src, sa);
444 static inline void emit_dsrl32(unsigned int dst, unsigned int src,
445 unsigned int sa, struct jit_ctx *ctx)
447 emit_instr(ctx, dsrl32, dst, src, sa);
450 static inline void emit_wsbh(unsigned int dst, unsigned int src,
453 emit_instr(ctx, wsbh, dst, src);
456 /* load a function pointer to register */
457 static inline void emit_load_func(unsigned int reg, ptr imm,
460 if (config_enabled(CONFIG_64BIT)) {
461 /* At this point imm is always 64-bit */
462 emit_load_imm(r_tmp, (u64)imm >> 32, ctx);
463 emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */
464 emit_ori(r_tmp, r_tmp_imm, (imm >> 16) & 0xffff, ctx);
465 emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */
466 emit_ori(reg, r_tmp_imm, imm & 0xffff, ctx);
468 emit_load_imm(reg, imm, ctx);
472 /* Move to real MIPS register */
473 static inline void emit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx)
475 if (config_enabled(CONFIG_64BIT))
476 emit_daddu(dst, src, r_zero, ctx);
478 emit_addu(dst, src, r_zero, ctx);
481 /* Move to JIT (32-bit) register */
482 static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx)
484 emit_addu(dst, src, r_zero, ctx);
487 /* Compute the immediate value for PC-relative branches. */
488 static inline u32 b_imm(unsigned int tgt, struct jit_ctx *ctx)
490 if (ctx->target == NULL)
494 * We want a pc-relative branch. We only do forward branches
495 * so tgt is always after pc. tgt is the instruction offset
496 * we want to jump to.
499 * I: target_offset <- sign_extend(offset)
500 * I+1: PC += target_offset (delay slot)
502 * ctx->idx currently points to the branch instruction
503 * but the offset is added to the delay slot so we need
506 return ctx->offsets[tgt] -
507 (ctx->idx * 4 - ctx->prologue_bytes) - 4;
510 static inline void emit_bcond(int cond, unsigned int reg1, unsigned int reg2,
511 unsigned int imm, struct jit_ctx *ctx)
513 if (ctx->target != NULL) {
514 u32 *p = &ctx->target[ctx->idx];
518 uasm_i_beq(&p, reg1, reg2, imm);
521 uasm_i_bne(&p, reg1, reg2, imm);
527 pr_warn("%s: Unhandled branch conditional: %d\n",
534 static inline void emit_b(unsigned int imm, struct jit_ctx *ctx)
536 emit_bcond(MIPS_COND_ALL, r_zero, r_zero, imm, ctx);
539 static inline void emit_jalr(unsigned int link, unsigned int reg,
542 emit_instr(ctx, jalr, link, reg);
545 static inline void emit_jr(unsigned int reg, struct jit_ctx *ctx)
547 emit_instr(ctx, jr, reg);
550 static inline u16 align_sp(unsigned int num)
552 /* Double word alignment for 32-bit, quadword for 64-bit */
553 unsigned int align = config_enabled(CONFIG_64BIT) ? 16 : 8;
554 num = (num + (align - 1)) & -align;
558 static bool is_load_to_a(u16 inst)
561 case BPF_LD | BPF_W | BPF_LEN:
562 case BPF_LD | BPF_W | BPF_ABS:
563 case BPF_LD | BPF_H | BPF_ABS:
564 case BPF_LD | BPF_B | BPF_ABS:
571 static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset)
573 int i = 0, real_off = 0;
574 u32 sflags, tmp_flags;
576 /* Adjust the stack pointer */
577 emit_stack_offset(-align_sp(offset), ctx);
579 if (ctx->flags & SEEN_CALL) {
580 /* Argument save area */
581 if (config_enabled(CONFIG_64BIT))
582 /* Bottom of current frame */
583 real_off = align_sp(offset) - RSIZE;
585 /* Top of previous frame */
586 real_off = align_sp(offset) + RSIZE;
587 emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
588 emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
593 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
594 /* sflags is essentially a bitmap */
596 if ((sflags >> i) & 0x1) {
597 emit_store_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
605 /* save return address */
606 if (ctx->flags & SEEN_CALL) {
607 emit_store_stack_reg(r_ra, r_sp, real_off, ctx);
611 /* Setup r_M leaving the alignment gap if necessary */
612 if (ctx->flags & SEEN_MEM) {
613 if (real_off % (RSIZE * 2))
615 emit_addiu(r_M, r_sp, real_off, ctx);
619 static void restore_bpf_jit_regs(struct jit_ctx *ctx,
623 u32 sflags, tmp_flags;
625 if (ctx->flags & SEEN_CALL) {
626 if (config_enabled(CONFIG_64BIT))
627 /* Bottom of current frame */
628 real_off = align_sp(offset) - RSIZE;
630 /* Top of previous frame */
631 real_off = align_sp(offset) + RSIZE;
632 emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
633 emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
638 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
639 /* sflags is a bitmap */
642 if ((sflags >> i) & 0x1) {
643 emit_load_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
651 /* restore return address */
652 if (ctx->flags & SEEN_CALL)
653 emit_load_stack_reg(r_ra, r_sp, real_off, ctx);
655 /* Restore the sp and discard the scrach memory */
656 emit_stack_offset(align_sp(offset), ctx);
659 static unsigned int get_stack_depth(struct jit_ctx *ctx)
664 /* How may s* regs do we need to preserved? */
665 sp_off += hweight32(ctx->flags >> SEEN_SREG_SFT) * RSIZE;
667 if (ctx->flags & SEEN_MEM)
668 sp_off += 4 * BPF_MEMWORDS; /* BPF_MEMWORDS are 32-bit */
670 if (ctx->flags & SEEN_CALL)
672 * The JIT code make calls to external functions using 2
673 * arguments. Therefore, for o32 we don't need to allocate
674 * space because we don't care if the argumetns are lost
675 * across calls. We do need however to preserve incoming
676 * arguments but the space is already allocated for us by
677 * the caller. On the other hand, for n64, we need to allocate
678 * this space ourselves. We need to preserve $ra as well.
680 sp_off += config_enabled(CONFIG_64BIT) ?
681 (ARGS_USED_BY_JIT + 1) * RSIZE : RSIZE;
684 * Subtract the bytes for the last registers since we only care about
685 * the location on the stack pointer.
687 return sp_off - RSIZE;
690 static void build_prologue(struct jit_ctx *ctx)
692 u16 first_inst = ctx->skf->insns[0].code;
695 /* Calculate the total offset for the stack pointer */
696 sp_off = get_stack_depth(ctx);
697 save_bpf_jit_regs(ctx, sp_off);
699 if (ctx->flags & SEEN_SKB)
700 emit_reg_move(r_skb, MIPS_R_A0, ctx);
702 if (ctx->flags & SEEN_X)
703 emit_jit_reg_move(r_X, r_zero, ctx);
705 /* Do not leak kernel data to userspace */
706 if ((first_inst != (BPF_RET | BPF_K)) && !(is_load_to_a(first_inst)))
707 emit_jit_reg_move(r_A, r_zero, ctx);
710 static void build_epilogue(struct jit_ctx *ctx)
714 /* Calculate the total offset for the stack pointer */
716 sp_off = get_stack_depth(ctx);
717 restore_bpf_jit_regs(ctx, sp_off);
724 static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
729 err = skb_copy_bits(skb, offset, &ret, 1);
731 return (u64)err << 32 | ret;
734 static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
739 err = skb_copy_bits(skb, offset, &ret, 2);
741 return (u64)err << 32 | ntohs(ret);
744 static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
749 err = skb_copy_bits(skb, offset, &ret, 4);
751 return (u64)err << 32 | ntohl(ret);
754 #define PKT_TYPE_MAX 7
755 static int pkt_type_offset(void)
757 struct sk_buff skb_probe = {
760 char *ct = (char *)&skb_probe;
763 for (off = 0; off < sizeof(struct sk_buff); off++) {
764 if (ct[off] == PKT_TYPE_MAX)
767 pr_err_once("Please fix pkt_type_offset(), as pkt_type couldn't be found\n");
771 static int build_body(struct jit_ctx *ctx)
773 void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
774 const struct sk_filter *prog = ctx->skf;
775 const struct sock_filter *inst;
776 unsigned int i, off, load_order, condt;
777 u32 k, b_off __maybe_unused;
779 for (i = 0; i < prog->len; i++) {
782 inst = &(prog->insns[i]);
783 pr_debug("%s: code->0x%02x, jt->0x%x, jf->0x%x, k->0x%x\n",
784 __func__, inst->code, inst->jt, inst->jf, inst->k);
786 code = bpf_anc_helper(inst);
788 if (ctx->target == NULL)
789 ctx->offsets[i] = ctx->idx * 4;
792 case BPF_LD | BPF_IMM:
793 /* A <- k ==> li r_A, k */
794 ctx->flags |= SEEN_A;
795 emit_load_imm(r_A, k, ctx);
797 case BPF_LD | BPF_W | BPF_LEN:
798 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
799 /* A <- len ==> lw r_A, offset(skb) */
800 ctx->flags |= SEEN_SKB | SEEN_A;
801 off = offsetof(struct sk_buff, len);
802 emit_load(r_A, r_skb, off, ctx);
804 case BPF_LD | BPF_MEM:
805 /* A <- M[k] ==> lw r_A, offset(M) */
806 ctx->flags |= SEEN_MEM | SEEN_A;
807 emit_load(r_A, r_M, SCRATCH_OFF(k), ctx);
809 case BPF_LD | BPF_W | BPF_ABS:
813 case BPF_LD | BPF_H | BPF_ABS:
817 case BPF_LD | BPF_B | BPF_ABS:
821 /* the interpreter will deal with the negative K */
825 emit_load_imm(r_off, k, ctx);
828 * We may got here from the indirect loads so
829 * return if offset is negative.
831 emit_slt(r_s0, r_off, r_zero, ctx);
832 emit_bcond(MIPS_COND_NE, r_s0, r_zero,
833 b_imm(prog->len, ctx), ctx);
834 emit_reg_move(r_ret, r_zero, ctx);
836 ctx->flags |= SEEN_CALL | SEEN_OFF | SEEN_S0 |
839 emit_load_func(r_s0, (ptr)load_func[load_order],
841 emit_reg_move(MIPS_R_A0, r_skb, ctx);
842 emit_jalr(MIPS_R_RA, r_s0, ctx);
843 /* Load second argument to delay slot */
844 emit_reg_move(MIPS_R_A1, r_off, ctx);
845 /* Check the error value */
846 if (config_enabled(CONFIG_64BIT)) {
847 /* Get error code from the top 32-bits */
848 emit_dsrl32(r_s0, r_val, 0, ctx);
849 /* Branch to 3 instructions ahead */
850 emit_bcond(MIPS_COND_NE, r_s0, r_zero, 3 << 2,
853 /* Branch to 3 instructions ahead */
854 emit_bcond(MIPS_COND_NE, r_err, r_zero, 3 << 2,
859 emit_b(b_imm(i + 1, ctx), ctx);
860 emit_jit_reg_move(r_A, r_val, ctx);
861 /* Return with error */
862 emit_b(b_imm(prog->len, ctx), ctx);
863 emit_reg_move(r_ret, r_zero, ctx);
865 case BPF_LD | BPF_W | BPF_IND:
866 /* A <- P[X + k:4] */
869 case BPF_LD | BPF_H | BPF_IND:
870 /* A <- P[X + k:2] */
873 case BPF_LD | BPF_B | BPF_IND:
874 /* A <- P[X + k:1] */
877 ctx->flags |= SEEN_OFF | SEEN_X;
878 emit_addiu(r_off, r_X, k, ctx);
880 case BPF_LDX | BPF_IMM:
882 ctx->flags |= SEEN_X;
883 emit_load_imm(r_X, k, ctx);
885 case BPF_LDX | BPF_MEM:
887 ctx->flags |= SEEN_X | SEEN_MEM;
888 emit_load(r_X, r_M, SCRATCH_OFF(k), ctx);
890 case BPF_LDX | BPF_W | BPF_LEN:
892 ctx->flags |= SEEN_X | SEEN_SKB;
893 off = offsetof(struct sk_buff, len);
894 emit_load(r_X, r_skb, off, ctx);
896 case BPF_LDX | BPF_B | BPF_MSH:
897 /* the interpreter will deal with the negative K */
901 /* X <- 4 * (P[k:1] & 0xf) */
902 ctx->flags |= SEEN_X | SEEN_CALL | SEEN_S0 | SEEN_SKB;
903 /* Load offset to a1 */
904 emit_load_func(r_s0, (ptr)jit_get_skb_b, ctx);
906 * This may emit two instructions so it may not fit
907 * in the delay slot. So use a0 in the delay slot.
909 emit_load_imm(MIPS_R_A1, k, ctx);
910 emit_jalr(MIPS_R_RA, r_s0, ctx);
911 emit_reg_move(MIPS_R_A0, r_skb, ctx); /* delay slot */
912 /* Check the error value */
913 if (config_enabled(CONFIG_64BIT)) {
914 /* Top 32-bits of $v0 on 64-bit */
915 emit_dsrl32(r_s0, r_val, 0, ctx);
916 emit_bcond(MIPS_COND_NE, r_s0, r_zero,
919 emit_bcond(MIPS_COND_NE, r_err, r_zero,
922 /* No need for delay slot */
924 /* X <- P[1:K] & 0xf */
925 emit_andi(r_X, r_val, 0xf, ctx);
927 emit_b(b_imm(i + 1, ctx), ctx);
928 emit_sll(r_X, r_X, 2, ctx); /* delay slot */
929 /* Return with error */
930 emit_b(b_imm(prog->len, ctx), ctx);
931 emit_load_imm(r_ret, 0, ctx); /* delay slot */
935 ctx->flags |= SEEN_MEM | SEEN_A;
936 emit_store(r_A, r_M, SCRATCH_OFF(k), ctx);
940 ctx->flags |= SEEN_MEM | SEEN_X;
941 emit_store(r_X, r_M, SCRATCH_OFF(k), ctx);
943 case BPF_ALU | BPF_ADD | BPF_K:
945 ctx->flags |= SEEN_A;
946 emit_addiu(r_A, r_A, k, ctx);
948 case BPF_ALU | BPF_ADD | BPF_X:
950 ctx->flags |= SEEN_A | SEEN_X;
951 emit_addu(r_A, r_A, r_X, ctx);
953 case BPF_ALU | BPF_SUB | BPF_K:
955 ctx->flags |= SEEN_A;
956 emit_addiu(r_A, r_A, -k, ctx);
958 case BPF_ALU | BPF_SUB | BPF_X:
960 ctx->flags |= SEEN_A | SEEN_X;
961 emit_subu(r_A, r_A, r_X, ctx);
963 case BPF_ALU | BPF_MUL | BPF_K:
965 /* Load K to scratch register before MUL */
966 ctx->flags |= SEEN_A | SEEN_S0;
967 emit_load_imm(r_s0, k, ctx);
968 emit_mul(r_A, r_A, r_s0, ctx);
970 case BPF_ALU | BPF_MUL | BPF_X:
972 ctx->flags |= SEEN_A | SEEN_X;
973 emit_mul(r_A, r_A, r_X, ctx);
975 case BPF_ALU | BPF_DIV | BPF_K:
979 if (optimize_div(&k)) {
980 ctx->flags |= SEEN_A;
981 emit_srl(r_A, r_A, k, ctx);
984 ctx->flags |= SEEN_A | SEEN_S0;
985 emit_load_imm(r_s0, k, ctx);
986 emit_div(r_A, r_s0, ctx);
988 case BPF_ALU | BPF_MOD | BPF_K:
990 if (k == 1 || optimize_div(&k)) {
991 ctx->flags |= SEEN_A;
992 emit_jit_reg_move(r_A, r_zero, ctx);
994 ctx->flags |= SEEN_A | SEEN_S0;
995 emit_load_imm(r_s0, k, ctx);
996 emit_mod(r_A, r_s0, ctx);
999 case BPF_ALU | BPF_DIV | BPF_X:
1001 ctx->flags |= SEEN_X | SEEN_A;
1002 /* Check if r_X is zero */
1003 emit_bcond(MIPS_COND_EQ, r_X, r_zero,
1004 b_imm(prog->len, ctx), ctx);
1005 emit_load_imm(r_val, 0, ctx); /* delay slot */
1006 emit_div(r_A, r_X, ctx);
1008 case BPF_ALU | BPF_MOD | BPF_X:
1010 ctx->flags |= SEEN_X | SEEN_A;
1011 /* Check if r_X is zero */
1012 emit_bcond(MIPS_COND_EQ, r_X, r_zero,
1013 b_imm(prog->len, ctx), ctx);
1014 emit_load_imm(r_val, 0, ctx); /* delay slot */
1015 emit_mod(r_A, r_X, ctx);
1017 case BPF_ALU | BPF_OR | BPF_K:
1019 ctx->flags |= SEEN_A;
1020 emit_ori(r_A, r_A, k, ctx);
1022 case BPF_ALU | BPF_OR | BPF_X:
1024 ctx->flags |= SEEN_A;
1025 emit_ori(r_A, r_A, r_X, ctx);
1027 case BPF_ALU | BPF_XOR | BPF_K:
1029 ctx->flags |= SEEN_A;
1030 emit_xori(r_A, r_A, k, ctx);
1032 case BPF_ANC | SKF_AD_ALU_XOR_X:
1033 case BPF_ALU | BPF_XOR | BPF_X:
1035 ctx->flags |= SEEN_A;
1036 emit_xor(r_A, r_A, r_X, ctx);
1038 case BPF_ALU | BPF_AND | BPF_K:
1040 ctx->flags |= SEEN_A;
1041 emit_andi(r_A, r_A, k, ctx);
1043 case BPF_ALU | BPF_AND | BPF_X:
1045 ctx->flags |= SEEN_A | SEEN_X;
1046 emit_and(r_A, r_A, r_X, ctx);
1048 case BPF_ALU | BPF_LSH | BPF_K:
1050 ctx->flags |= SEEN_A;
1051 emit_sll(r_A, r_A, k, ctx);
1053 case BPF_ALU | BPF_LSH | BPF_X:
1055 ctx->flags |= SEEN_A | SEEN_X;
1056 emit_sllv(r_A, r_A, r_X, ctx);
1058 case BPF_ALU | BPF_RSH | BPF_K:
1060 ctx->flags |= SEEN_A;
1061 emit_srl(r_A, r_A, k, ctx);
1063 case BPF_ALU | BPF_RSH | BPF_X:
1064 ctx->flags |= SEEN_A | SEEN_X;
1065 emit_srlv(r_A, r_A, r_X, ctx);
1067 case BPF_ALU | BPF_NEG:
1069 ctx->flags |= SEEN_A;
1072 case BPF_JMP | BPF_JA:
1074 emit_b(b_imm(i + k + 1, ctx), ctx);
1077 case BPF_JMP | BPF_JEQ | BPF_K:
1078 /* pc += ( A == K ) ? pc->jt : pc->jf */
1079 condt = MIPS_COND_EQ | MIPS_COND_K;
1081 case BPF_JMP | BPF_JEQ | BPF_X:
1082 ctx->flags |= SEEN_X;
1083 /* pc += ( A == X ) ? pc->jt : pc->jf */
1084 condt = MIPS_COND_EQ | MIPS_COND_X;
1086 case BPF_JMP | BPF_JGE | BPF_K:
1087 /* pc += ( A >= K ) ? pc->jt : pc->jf */
1088 condt = MIPS_COND_GE | MIPS_COND_K;
1090 case BPF_JMP | BPF_JGE | BPF_X:
1091 ctx->flags |= SEEN_X;
1092 /* pc += ( A >= X ) ? pc->jt : pc->jf */
1093 condt = MIPS_COND_GE | MIPS_COND_X;
1095 case BPF_JMP | BPF_JGT | BPF_K:
1096 /* pc += ( A > K ) ? pc->jt : pc->jf */
1097 condt = MIPS_COND_GT | MIPS_COND_K;
1099 case BPF_JMP | BPF_JGT | BPF_X:
1100 ctx->flags |= SEEN_X;
1101 /* pc += ( A > X ) ? pc->jt : pc->jf */
1102 condt = MIPS_COND_GT | MIPS_COND_X;
1104 /* Greater or Equal */
1105 if ((condt & MIPS_COND_GE) ||
1106 (condt & MIPS_COND_GT)) {
1107 if (condt & MIPS_COND_K) { /* K */
1108 ctx->flags |= SEEN_S0 | SEEN_A;
1109 emit_sltiu(r_s0, r_A, k, ctx);
1111 ctx->flags |= SEEN_S0 | SEEN_A |
1113 emit_sltu(r_s0, r_A, r_X, ctx);
1115 /* A < (K|X) ? r_scrach = 1 */
1116 b_off = b_imm(i + inst->jf + 1, ctx);
1117 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off,
1120 /* A > (K|X) ? scratch = 0 */
1121 if (condt & MIPS_COND_GT) {
1122 /* Checking for equality */
1123 ctx->flags |= SEEN_S0 | SEEN_A | SEEN_X;
1124 if (condt & MIPS_COND_K)
1125 emit_load_imm(r_s0, k, ctx);
1127 emit_jit_reg_move(r_s0, r_X,
1129 b_off = b_imm(i + inst->jf + 1, ctx);
1130 emit_bcond(MIPS_COND_EQ, r_A, r_s0,
1133 /* Finally, A > K|X */
1134 b_off = b_imm(i + inst->jt + 1, ctx);
1138 /* A >= (K|X) so jump */
1139 b_off = b_imm(i + inst->jt + 1, ctx);
1145 if (condt & MIPS_COND_K) { /* K */
1146 ctx->flags |= SEEN_S0 | SEEN_A;
1147 emit_load_imm(r_s0, k, ctx);
1149 b_off = b_imm(i + inst->jt + 1, ctx);
1150 emit_bcond(MIPS_COND_EQ, r_A, r_s0,
1154 b_off = b_imm(i + inst->jf + 1,
1156 emit_bcond(MIPS_COND_NE, r_A, r_s0,
1161 ctx->flags |= SEEN_A | SEEN_X;
1162 b_off = b_imm(i + inst->jt + 1,
1164 emit_bcond(MIPS_COND_EQ, r_A, r_X,
1168 b_off = b_imm(i + inst->jf + 1, ctx);
1169 emit_bcond(MIPS_COND_NE, r_A, r_X,
1175 case BPF_JMP | BPF_JSET | BPF_K:
1176 ctx->flags |= SEEN_S0 | SEEN_S1 | SEEN_A;
1177 /* pc += (A & K) ? pc -> jt : pc -> jf */
1178 emit_load_imm(r_s1, k, ctx);
1179 emit_and(r_s0, r_A, r_s1, ctx);
1181 b_off = b_imm(i + inst->jt + 1, ctx);
1182 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx);
1185 b_off = b_imm(i + inst->jf + 1, ctx);
1189 case BPF_JMP | BPF_JSET | BPF_X:
1190 ctx->flags |= SEEN_S0 | SEEN_X | SEEN_A;
1191 /* pc += (A & X) ? pc -> jt : pc -> jf */
1192 emit_and(r_s0, r_A, r_X, ctx);
1194 b_off = b_imm(i + inst->jt + 1, ctx);
1195 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx);
1198 b_off = b_imm(i + inst->jf + 1, ctx);
1202 case BPF_RET | BPF_A:
1203 ctx->flags |= SEEN_A;
1204 if (i != prog->len - 1)
1206 * If this is not the last instruction
1207 * then jump to the epilogue
1209 emit_b(b_imm(prog->len, ctx), ctx);
1210 emit_reg_move(r_ret, r_A, ctx); /* delay slot */
1212 case BPF_RET | BPF_K:
1214 * It can emit two instructions so it does not fit on
1217 emit_load_imm(r_ret, k, ctx);
1218 if (i != prog->len - 1) {
1220 * If this is not the last instruction
1221 * then jump to the epilogue
1223 emit_b(b_imm(prog->len, ctx), ctx);
1227 case BPF_MISC | BPF_TAX:
1229 ctx->flags |= SEEN_X | SEEN_A;
1230 emit_jit_reg_move(r_X, r_A, ctx);
1232 case BPF_MISC | BPF_TXA:
1234 ctx->flags |= SEEN_A | SEEN_X;
1235 emit_jit_reg_move(r_A, r_X, ctx);
1238 case BPF_ANC | SKF_AD_PROTOCOL:
1239 /* A = ntohs(skb->protocol */
1240 ctx->flags |= SEEN_SKB | SEEN_OFF | SEEN_A;
1241 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1243 off = offsetof(struct sk_buff, protocol);
1244 emit_half_load(r_A, r_skb, off, ctx);
1245 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1246 /* This needs little endian fixup */
1247 if (cpu_has_mips_r2) {
1248 /* R2 and later have the wsbh instruction */
1249 emit_wsbh(r_A, r_A, ctx);
1251 /* Get first byte */
1252 emit_andi(r_tmp_imm, r_A, 0xff, ctx);
1254 emit_sll(r_tmp, r_tmp_imm, 8, ctx);
1255 /* Get second byte */
1256 emit_srl(r_tmp_imm, r_A, 8, ctx);
1257 emit_andi(r_tmp_imm, r_tmp_imm, 0xff, ctx);
1258 /* Put everyting together in r_A */
1259 emit_or(r_A, r_tmp, r_tmp_imm, ctx);
1263 case BPF_ANC | SKF_AD_CPU:
1264 ctx->flags |= SEEN_A | SEEN_OFF;
1265 /* A = current_thread_info()->cpu */
1266 BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info,
1268 off = offsetof(struct thread_info, cpu);
1269 /* $28/gp points to the thread_info struct */
1270 emit_load(r_A, 28, off, ctx);
1272 case BPF_ANC | SKF_AD_IFINDEX:
1273 /* A = skb->dev->ifindex */
1274 ctx->flags |= SEEN_SKB | SEEN_A | SEEN_S0;
1275 off = offsetof(struct sk_buff, dev);
1276 emit_load(r_s0, r_skb, off, ctx);
1277 /* error (0) in the delay slot */
1278 emit_bcond(MIPS_COND_EQ, r_s0, r_zero,
1279 b_imm(prog->len, ctx), ctx);
1280 emit_reg_move(r_ret, r_zero, ctx);
1281 BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
1283 off = offsetof(struct net_device, ifindex);
1284 emit_load(r_A, r_s0, off, ctx);
1286 case BPF_ANC | SKF_AD_MARK:
1287 ctx->flags |= SEEN_SKB | SEEN_A;
1288 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
1289 off = offsetof(struct sk_buff, mark);
1290 emit_load(r_A, r_skb, off, ctx);
1292 case BPF_ANC | SKF_AD_RXHASH:
1293 ctx->flags |= SEEN_SKB | SEEN_A;
1294 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
1295 off = offsetof(struct sk_buff, hash);
1296 emit_load(r_A, r_skb, off, ctx);
1298 case BPF_ANC | SKF_AD_VLAN_TAG:
1299 case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT:
1300 ctx->flags |= SEEN_SKB | SEEN_S0 | SEEN_A;
1301 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1303 off = offsetof(struct sk_buff, vlan_tci);
1304 emit_half_load(r_s0, r_skb, off, ctx);
1305 if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) {
1306 emit_andi(r_A, r_s0, (u16)~VLAN_TAG_PRESENT, ctx);
1308 emit_andi(r_A, r_s0, VLAN_TAG_PRESENT, ctx);
1309 /* return 1 if present */
1310 emit_sltu(r_A, r_zero, r_A, ctx);
1313 case BPF_ANC | SKF_AD_PKTTYPE:
1314 ctx->flags |= SEEN_SKB;
1316 off = pkt_type_offset();
1320 emit_load_byte(r_tmp, r_skb, off, ctx);
1321 /* Keep only the last 3 bits */
1322 emit_andi(r_A, r_tmp, PKT_TYPE_MAX, ctx);
1324 case BPF_ANC | SKF_AD_QUEUE:
1325 ctx->flags |= SEEN_SKB | SEEN_A;
1326 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1327 queue_mapping) != 2);
1328 BUILD_BUG_ON(offsetof(struct sk_buff,
1329 queue_mapping) > 0xff);
1330 off = offsetof(struct sk_buff, queue_mapping);
1331 emit_half_load(r_A, r_skb, off, ctx);
1334 pr_debug("%s: Unhandled opcode: 0x%02x\n", __FILE__,
1340 /* compute offsets only during the first pass */
1341 if (ctx->target == NULL)
1342 ctx->offsets[i] = ctx->idx * 4;
1347 int bpf_jit_enable __read_mostly;
1349 void bpf_jit_compile(struct sk_filter *fp)
1352 unsigned int alloc_size, tmp_idx;
1354 if (!bpf_jit_enable)
1357 memset(&ctx, 0, sizeof(ctx));
1359 ctx.offsets = kcalloc(fp->len, sizeof(*ctx.offsets), GFP_KERNEL);
1360 if (ctx.offsets == NULL)
1365 if (build_body(&ctx))
1369 build_prologue(&ctx);
1370 ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
1371 /* just to complete the ctx.idx count */
1372 build_epilogue(&ctx);
1374 alloc_size = 4 * ctx.idx;
1375 ctx.target = module_alloc(alloc_size);
1376 if (ctx.target == NULL)
1380 memset(ctx.target, 0, alloc_size);
1384 /* Generate the actual JIT code */
1385 build_prologue(&ctx);
1387 build_epilogue(&ctx);
1389 /* Update the icache */
1390 flush_icache_range((ptr)ctx.target, (ptr)(ctx.target + ctx.idx));
1392 if (bpf_jit_enable > 1)
1394 bpf_jit_dump(fp->len, alloc_size, 2, ctx.target);
1396 fp->bpf_func = (void *)ctx.target;
1403 void bpf_jit_free(struct sk_filter *fp)
1406 module_free(NULL, fp->bpf_func);