2 * T2081 Silicon/SoC Device Tree Source (post include)
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36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
43 compatible = "fsl,ifc", "simple-bus";
44 interrupts = <25 2 0 0>;
47 /* controller at 0x240000 */
49 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
53 bus-range = <0x0 0xff>;
54 interrupts = <20 2 0 0>;
55 fsl,iommu-parent = <&pamu0>;
58 #interrupt-cells = <1>;
62 interrupts = <20 2 0 0>;
63 interrupt-map-mask = <0xf800 0 0 7>;
66 0000 0 0 1 &mpic 40 1 0 0
67 0000 0 0 2 &mpic 1 1 0 0
68 0000 0 0 3 &mpic 2 1 0 0
69 0000 0 0 4 &mpic 3 1 0 0
74 /* controller at 0x250000 */
76 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
81 interrupts = <21 2 0 0>;
82 fsl,iommu-parent = <&pamu0>;
85 #interrupt-cells = <1>;
89 interrupts = <21 2 0 0>;
90 interrupt-map-mask = <0xf800 0 0 7>;
93 0000 0 0 1 &mpic 41 1 0 0
94 0000 0 0 2 &mpic 5 1 0 0
95 0000 0 0 3 &mpic 6 1 0 0
96 0000 0 0 4 &mpic 7 1 0 0
101 /* controller at 0x260000 */
103 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
106 #address-cells = <3>;
107 bus-range = <0x0 0xff>;
108 interrupts = <22 2 0 0>;
109 fsl,iommu-parent = <&pamu0>;
112 #interrupt-cells = <1>;
114 #address-cells = <3>;
116 interrupts = <22 2 0 0>;
117 interrupt-map-mask = <0xf800 0 0 7>;
120 0000 0 0 1 &mpic 42 1 0 0
121 0000 0 0 2 &mpic 9 1 0 0
122 0000 0 0 3 &mpic 10 1 0 0
123 0000 0 0 4 &mpic 11 1 0 0
128 /* controller at 0x270000 */
130 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
133 #address-cells = <3>;
134 bus-range = <0x0 0xff>;
135 interrupts = <23 2 0 0>;
136 fsl,iommu-parent = <&pamu0>;
139 #interrupt-cells = <1>;
141 #address-cells = <3>;
143 interrupts = <23 2 0 0>;
144 interrupt-map-mask = <0xf800 0 0 7>;
147 0000 0 0 1 &mpic 43 1 0 0
148 0000 0 0 2 &mpic 0 1 0 0
149 0000 0 0 3 &mpic 4 1 0 0
150 0000 0 0 4 &mpic 8 1 0 0
156 #address-cells = <1>;
158 compatible = "fsl,dcsr", "simple-bus";
161 compatible = "fsl,t2080-dcsr-epu", "fsl,dcsr-epu";
162 interrupts = <52 2 0 0
170 compatible = "fsl,t2080-dcsr-cnpc", "fsl,dcsr-cnpc";
171 reg = <0x1000 0x1000 0x1002000 0x10000>;
174 compatible = "fsl,dcsr-nxc";
175 reg = <0x2000 0x1000>;
178 compatible = "fsl,dcsr-corenet";
179 reg = <0x8000 0x1000 0x1A000 0x1000>;
182 compatible = "fsl,t2080-dcsr-ocn", "fsl,dcsr-ocn";
183 reg = <0x11000 0x1000>;
186 compatible = "fsl,dcsr-ddr";
187 dev-handle = <&ddr1>;
188 reg = <0x12000 0x1000>;
191 compatible = "fsl,t2080-dcsr-nal", "fsl,dcsr-nal";
192 reg = <0x18000 0x1000>;
195 compatible = "fsl,t2080-dcsr-rcpm", "fsl,dcsr-rcpm";
196 reg = <0x22000 0x1000>;
199 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
200 reg = <0x30000 0x1000 0x1022000 0x10000>;
203 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
204 reg = <0x31000 0x1000 0x1042000 0x10000>;
207 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
208 reg = <0x32000 0x1000 0x1062000 0x10000>;
210 dcsr-cpu-sb-proxy@100000 {
211 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
212 cpu-handle = <&cpu0>;
213 reg = <0x100000 0x1000 0x101000 0x1000>;
215 dcsr-cpu-sb-proxy@108000 {
216 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
217 cpu-handle = <&cpu1>;
218 reg = <0x108000 0x1000 0x109000 0x1000>;
220 dcsr-cpu-sb-proxy@110000 {
221 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
222 cpu-handle = <&cpu2>;
223 reg = <0x110000 0x1000 0x111000 0x1000>;
225 dcsr-cpu-sb-proxy@118000 {
226 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
227 cpu-handle = <&cpu3>;
228 reg = <0x118000 0x1000 0x119000 0x1000>;
233 #address-cells = <0x1>;
235 compatible = "simple-bus";
238 compatible = "fsl,bman-portal";
239 reg = <0x0 0x4000>, <0x1000000 0x1000>;
240 interrupts = <105 2 0 0>;
243 compatible = "fsl,bman-portal";
244 reg = <0x4000 0x4000>, <0x1001000 0x1000>;
245 interrupts = <107 2 0 0>;
248 compatible = "fsl,bman-portal";
249 reg = <0x8000 0x4000>, <0x1002000 0x1000>;
250 interrupts = <109 2 0 0>;
253 compatible = "fsl,bman-portal";
254 reg = <0xc000 0x4000>, <0x1003000 0x1000>;
255 interrupts = <111 2 0 0>;
258 compatible = "fsl,bman-portal";
259 reg = <0x10000 0x4000>, <0x1004000 0x1000>;
260 interrupts = <113 2 0 0>;
263 compatible = "fsl,bman-portal";
264 reg = <0x14000 0x4000>, <0x1005000 0x1000>;
265 interrupts = <115 2 0 0>;
268 compatible = "fsl,bman-portal";
269 reg = <0x18000 0x4000>, <0x1006000 0x1000>;
270 interrupts = <117 2 0 0>;
273 compatible = "fsl,bman-portal";
274 reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
275 interrupts = <119 2 0 0>;
278 compatible = "fsl,bman-portal";
279 reg = <0x20000 0x4000>, <0x1008000 0x1000>;
280 interrupts = <121 2 0 0>;
283 compatible = "fsl,bman-portal";
284 reg = <0x24000 0x4000>, <0x1009000 0x1000>;
285 interrupts = <123 2 0 0>;
288 compatible = "fsl,bman-portal";
289 reg = <0x28000 0x4000>, <0x100a000 0x1000>;
290 interrupts = <125 2 0 0>;
293 compatible = "fsl,bman-portal";
294 reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
295 interrupts = <127 2 0 0>;
298 compatible = "fsl,bman-portal";
299 reg = <0x30000 0x4000>, <0x100c000 0x1000>;
300 interrupts = <129 2 0 0>;
303 compatible = "fsl,bman-portal";
304 reg = <0x34000 0x4000>, <0x100d000 0x1000>;
305 interrupts = <131 2 0 0>;
308 compatible = "fsl,bman-portal";
309 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
310 interrupts = <133 2 0 0>;
313 compatible = "fsl,bman-portal";
314 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
315 interrupts = <135 2 0 0>;
318 compatible = "fsl,bman-portal";
319 reg = <0x40000 0x4000>, <0x1010000 0x1000>;
320 interrupts = <137 2 0 0>;
323 compatible = "fsl,bman-portal";
324 reg = <0x44000 0x4000>, <0x1011000 0x1000>;
325 interrupts = <139 2 0 0>;
330 #address-cells = <1>;
333 compatible = "simple-bus";
336 compatible = "fsl,soc-sram-error";
337 interrupts = <16 2 1 29>;
341 compatible = "fsl,corenet-law";
346 ddr1: memory-controller@8000 {
347 compatible = "fsl,qoriq-memory-controller-v4.7",
348 "fsl,qoriq-memory-controller";
349 reg = <0x8000 0x1000>;
350 interrupts = <16 2 1 23>;
353 cpc: l3-cache-controller@10000 {
354 compatible = "fsl,t2080-l3-cache-controller", "cache";
355 reg = <0x10000 0x1000
358 interrupts = <16 2 1 27
364 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
365 reg = <0x18000 0x1000>;
366 interrupts = <16 2 1 31>;
367 fsl,ccf-num-csdids = <32>;
368 fsl,ccf-num-snoopids = <32>;
372 compatible = "fsl,pamu-v1.0", "fsl,pamu";
373 reg = <0x20000 0x3000>;
374 fsl,portid-mapping = <0x8000>;
375 ranges = <0 0x20000 0x3000>;
376 #address-cells = <1>;
384 fsl,primary-cache-geometry = <32 1>;
385 fsl,secondary-cache-geometry = <128 2>;
389 reg = <0x1000 0x1000>;
390 fsl,primary-cache-geometry = <32 1>;
391 fsl,secondary-cache-geometry = <128 2>;
395 reg = <0x2000 0x1000>;
396 fsl,primary-cache-geometry = <32 1>;
397 fsl,secondary-cache-geometry = <128 2>;
401 /include/ "qoriq-mpic4.3.dtsi"
403 guts: global-utilities@e0000 {
404 compatible = "fsl,t2080-device-config", "fsl,qoriq-device-config-2.0";
405 reg = <0xe0000 0xe00>;
407 fsl,liodn-bits = <12>;
410 /include/ "qoriq-clockgen2.dtsi"
411 global-utilities@e1000 {
412 compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
417 compatible = "fsl,qoriq-core-mux-2.0";
418 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
419 <&pll1 0>, <&pll1 1>, <&pll1 2>;
420 clock-names = "pll0", "pll0-div2", "pll0-div4",
421 "pll1", "pll1-div2", "pll1-div4";
422 clock-output-names = "cmux0";
428 compatible = "fsl,qoriq-core-mux-2.0";
429 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
430 <&pll1 0>, <&pll1 1>, <&pll1 2>;
431 clock-names = "pll0", "pll0-div2", "pll0-div4",
432 "pll1", "pll1-div2", "pll1-div4";
433 clock-output-names = "cmux1";
437 rcpm: global-utilities@e2000 {
438 compatible = "fsl,t2080-rcpm", "fsl,qoriq-rcpm-2.0";
439 reg = <0xe2000 0x1000>;
443 compatible = "fsl,t2080-sfp";
444 reg = <0xe8000 0x1000>;
447 serdes: serdes@ea000 {
448 compatible = "fsl,t2080-serdes";
449 reg = <0xea000 0x4000>;
452 /include/ "elo3-dma-0.dtsi"
454 fsl,iommu-parent = <&pamu0>;
455 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
457 /include/ "elo3-dma-1.dtsi"
459 fsl,iommu-parent = <&pamu0>;
460 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
462 /include/ "elo3-dma-2.dtsi"
464 fsl,iommu-parent = <&pamu0>;
465 fsl,liodn-reg = <&guts 0x588>; /* DMA3LIODNR */
468 /include/ "qoriq-espi-0.dtsi"
470 fsl,espi-num-chipselects = <4>;
473 /include/ "qoriq-esdhc-0.dtsi"
475 compatible = "fsl,t2080-esdhc", "fsl,esdhc";
476 fsl,iommu-parent = <&pamu1>;
477 fsl,liodn-reg = <&guts 0x530>; /* SDMMCLIODNR */
480 /include/ "qoriq-i2c-0.dtsi"
481 /include/ "qoriq-i2c-1.dtsi"
482 /include/ "qoriq-duart-0.dtsi"
483 /include/ "qoriq-duart-1.dtsi"
484 /include/ "qoriq-gpio-0.dtsi"
485 /include/ "qoriq-gpio-1.dtsi"
486 /include/ "qoriq-gpio-2.dtsi"
487 /include/ "qoriq-gpio-3.dtsi"
488 /include/ "qoriq-usb2-mph-0.dtsi"
490 compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
491 fsl,iommu-parent = <&pamu1>;
492 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
496 /include/ "qoriq-usb2-dr-0.dtsi"
498 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
499 fsl,iommu-parent = <&pamu1>;
500 fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */
504 /include/ "qoriq-sec5.2-0.dtsi"
505 /include/ "qoriq-bman1.dtsi"
507 L2_1: l2-cache-controller@c20000 {
508 /* Cluster 0 L2 cache */
509 compatible = "fsl,t2080-l2-cache-controller";
510 reg = <0xc20000 0x40000>;
511 next-level-cache = <&cpc>;