2 * MPC8548 CDS Device Tree Source
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
16 compatible = "MPC8548CDS", "MPC85xxCDS";
41 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <0x8000>; // L1, 32K
45 timebase-frequency = <0>; // 33 MHz, from uboot
46 bus-frequency = <0>; // 166 MHz
47 clock-frequency = <0>; // 825 MHz, from uboot
48 next-level-cache = <&L2>;
53 device_type = "memory";
54 reg = <0x0 0x8000000>; // 128M at 0x0
61 ranges = <0x0 0xe0000000 0x100000>;
62 reg = <0xe0000000 0x1000>; // CCSRBAR
65 memory-controller@2000 {
66 compatible = "fsl,8548-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
72 L2: l2-cache-controller@20000 {
73 compatible = "fsl,8548-l2-cache-controller";
74 reg = <0x20000 0x1000>;
75 cache-line-size = <32>; // 32 bytes
76 cache-size = <0x80000>; // L2, 512K
77 interrupt-parent = <&mpic>;
85 compatible = "fsl-i2c";
88 interrupt-parent = <&mpic>;
96 compatible = "fsl-i2c";
99 interrupt-parent = <&mpic>;
104 #address-cells = <1>;
106 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
108 ranges = <0x0 0x21100 0x200>;
111 compatible = "fsl,mpc8548-dma-channel",
112 "fsl,eloplus-dma-channel";
115 interrupt-parent = <&mpic>;
119 compatible = "fsl,mpc8548-dma-channel",
120 "fsl,eloplus-dma-channel";
123 interrupt-parent = <&mpic>;
127 compatible = "fsl,mpc8548-dma-channel",
128 "fsl,eloplus-dma-channel";
131 interrupt-parent = <&mpic>;
135 compatible = "fsl,mpc8548-dma-channel",
136 "fsl,eloplus-dma-channel";
139 interrupt-parent = <&mpic>;
145 #address-cells = <1>;
147 compatible = "fsl,gianfar-mdio";
148 reg = <0x24520 0x20>;
150 phy0: ethernet-phy@0 {
151 interrupt-parent = <&mpic>;
154 device_type = "ethernet-phy";
156 phy1: ethernet-phy@1 {
157 interrupt-parent = <&mpic>;
160 device_type = "ethernet-phy";
162 phy2: ethernet-phy@2 {
163 interrupt-parent = <&mpic>;
166 device_type = "ethernet-phy";
168 phy3: ethernet-phy@3 {
169 interrupt-parent = <&mpic>;
172 device_type = "ethernet-phy";
176 enet0: ethernet@24000 {
178 device_type = "network";
180 compatible = "gianfar";
181 reg = <0x24000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <29 2 30 2 34 2>;
184 interrupt-parent = <&mpic>;
185 phy-handle = <&phy0>;
188 enet1: ethernet@25000 {
190 device_type = "network";
192 compatible = "gianfar";
193 reg = <0x25000 0x1000>;
194 local-mac-address = [ 00 00 00 00 00 00 ];
195 interrupts = <35 2 36 2 40 2>;
196 interrupt-parent = <&mpic>;
197 phy-handle = <&phy1>;
200 /* eTSEC 3/4 are currently broken
201 enet2: ethernet@26000 {
203 device_type = "network";
205 compatible = "gianfar";
206 reg = <0x26000 0x1000>;
207 local-mac-address = [ 00 00 00 00 00 00 ];
208 interrupts = <31 2 32 2 33 2>;
209 interrupt-parent = <&mpic>;
210 phy-handle = <&phy2>;
213 enet3: ethernet@27000 {
215 device_type = "network";
217 compatible = "gianfar";
218 reg = <0x27000 0x1000>;
219 local-mac-address = [ 00 00 00 00 00 00 ];
220 interrupts = <37 2 38 2 39 2>;
221 interrupt-parent = <&mpic>;
222 phy-handle = <&phy3>;
226 serial0: serial@4500 {
228 device_type = "serial";
229 compatible = "ns16550";
230 reg = <0x4500 0x100>; // reg base, size
231 clock-frequency = <0>; // should we fill in in uboot?
233 interrupt-parent = <&mpic>;
236 serial1: serial@4600 {
238 device_type = "serial";
239 compatible = "ns16550";
240 reg = <0x4600 0x100>; // reg base, size
241 clock-frequency = <0>; // should we fill in in uboot?
243 interrupt-parent = <&mpic>;
246 global-utilities@e0000 { //global utilities reg
247 compatible = "fsl,mpc8548-guts";
248 reg = <0xe0000 0x1000>;
253 interrupt-controller;
254 #address-cells = <0>;
255 #interrupt-cells = <2>;
256 reg = <0x40000 0x40000>;
257 compatible = "chrp,open-pic";
258 device_type = "open-pic";
264 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
266 /* IDSEL 0x4 (PCIX Slot 2) */
267 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
268 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
269 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
270 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
272 /* IDSEL 0x5 (PCIX Slot 3) */
273 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
274 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
275 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
276 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
278 /* IDSEL 0x6 (PCIX Slot 4) */
279 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
280 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
281 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
282 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
284 /* IDSEL 0x8 (PCIX Slot 5) */
285 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
286 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
287 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
288 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
290 /* IDSEL 0xC (Tsi310 bridge) */
291 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
292 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
293 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
294 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
296 /* IDSEL 0x14 (Slot 2) */
297 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
298 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
299 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
300 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
302 /* IDSEL 0x15 (Slot 3) */
303 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
304 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
305 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
306 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
308 /* IDSEL 0x16 (Slot 4) */
309 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
310 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
311 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
312 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
314 /* IDSEL 0x18 (Slot 5) */
315 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
316 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
317 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
318 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
320 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
321 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
322 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
323 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
324 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
326 interrupt-parent = <&mpic>;
329 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
330 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
331 clock-frequency = <66666666>;
332 #interrupt-cells = <1>;
334 #address-cells = <3>;
335 reg = <0xe0008000 0x1000>;
336 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
340 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
343 /* IDSEL 0x00 (PrPMC Site) */
344 0000 0x0 0x0 0x1 &mpic 0x0 0x1
345 0000 0x0 0x0 0x2 &mpic 0x1 0x1
346 0000 0x0 0x0 0x3 &mpic 0x2 0x1
347 0000 0x0 0x0 0x4 &mpic 0x3 0x1
349 /* IDSEL 0x04 (VIA chip) */
350 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
351 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
352 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
353 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
355 /* IDSEL 0x05 (8139) */
356 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
358 /* IDSEL 0x06 (Slot 6) */
359 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
360 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
361 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
362 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
364 /* IDESL 0x07 (Slot 7) */
365 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
366 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
367 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
368 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
370 reg = <0xe000 0x0 0x0 0x0 0x0>;
371 #interrupt-cells = <1>;
373 #address-cells = <3>;
374 ranges = <0x2000000 0x0 0x80000000
375 0x2000000 0x0 0x80000000
380 clock-frequency = <33333333>;
384 #interrupt-cells = <2>;
386 #address-cells = <2>;
387 reg = <0x2000 0x0 0x0 0x0 0x0>;
388 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
389 interrupt-parent = <&i8259>;
391 i8259: interrupt-controller@20 {
392 interrupt-controller;
393 device_type = "interrupt-controller";
397 #address-cells = <0>;
398 #interrupt-cells = <2>;
399 compatible = "chrp,iic";
401 interrupt-parent = <&mpic>;
405 compatible = "pnpPNP,b00";
406 reg = <0x1 0x70 0x2>;
414 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
418 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
419 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
420 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
421 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
423 interrupt-parent = <&mpic>;
426 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
427 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
428 clock-frequency = <66666666>;
429 #interrupt-cells = <1>;
431 #address-cells = <3>;
432 reg = <0xe0009000 0x1000>;
433 compatible = "fsl,mpc8540-pci";
437 pci2: pcie@e000a000 {
439 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
442 /* IDSEL 0x0 (PEX) */
443 00000 0x0 0x0 0x1 &mpic 0x0 0x1
444 00000 0x0 0x0 0x2 &mpic 0x1 0x1
445 00000 0x0 0x0 0x3 &mpic 0x2 0x1
446 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
448 interrupt-parent = <&mpic>;
451 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
452 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
453 clock-frequency = <33333333>;
454 #interrupt-cells = <1>;
456 #address-cells = <3>;
457 reg = <0xe000a000 0x1000>;
458 compatible = "fsl,mpc8548-pcie";
461 reg = <0x0 0x0 0x0 0x0 0x0>;
463 #address-cells = <3>;
465 ranges = <0x2000000 0x0 0xa0000000
466 0x2000000 0x0 0xa0000000