arch/powerpc/boot/dts/mpc8548cds.dtsi

   1 /*
   2  * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
   3  *
   4  * Copyright 2012 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &board_lbc {
  36         nor@0,0 {
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 compatible = "cfi-flash";
  40                 reg = <0x0 0x0 0x01000000>;
  41                 bank-width = <2>;
  42                 device-width = <2>;
  43
  44                 partition@0 {
  45                         reg = <0x0 0x0b00000>;
  46                         label = "ramdisk-nor";
  47                 };
  48
  49                 partition@300000 {
  50                         reg = <0x0b00000 0x0400000>;
  51                         label = "kernel-nor";
  52                 };
  53
  54                 partition@700000 {
  55                         reg = <0x0f00000 0x060000>;
  56                         label = "dtb-nor";
  57                 };
  58
  59                 partition@760000 {
  60                         reg = <0x0f60000 0x020000>;
  61                         label = "env-nor";
  62                         read-only;
  63                 };
  64
  65                 partition@780000 {
  66                         reg = <0x0f80000 0x080000>;
  67                         label = "u-boot-nor";
  68                         read-only;
  69                 };
  70         };
  71
  72         board-control@1,0 {
  73                 compatible = "fsl,mpc8548cds-fpga";
  74                 reg = <0x1 0x0 0x1000>;
  75         };
  76 };
  77
  78 &board_soc {
  79         i2c@3000 {
  80                 eeprom@50 {
  81                         compatible = "atmel,24c64";
  82                         reg = <0x50>;
  83                 };
  84
  85                 eeprom@56 {
  86                         compatible = "atmel,24c64";
  87                         reg = <0x56>;
  88                 };
  89
  90                 eeprom@57 {
  91                         compatible = "atmel,24c64";
  92                         reg = <0x57>;
  93                 };
  94         };
  95
  96         i2c@3100 {
  97                 eeprom@50 {
  98                         compatible = "atmel,24c64";
  99                         reg = <0x50>;
 100                 };
 101         };
 102
 103         enet0: ethernet@24000 {
 104                 tbi-handle = <&tbi0>;
 105                 phy-handle = <&phy0>;
 106         };
 107
 108         mdio@24520 {
 109                 phy0: ethernet-phy@0 {
 110                         interrupts = <5 1 0 0>;
 111                         reg = <0x0>;
 112                         device_type = "ethernet-phy";
 113                 };
 114                 phy1: ethernet-phy@1 {
 115                         interrupts = <5 1 0 0>;
 116                         reg = <0x1>;
 117                         device_type = "ethernet-phy";
 118                 };
 119                 phy2: ethernet-phy@2 {
 120                         interrupts = <5 1 0 0>;
 121                         reg = <0x2>;
 122                         device_type = "ethernet-phy";
 123                 };
 124                 phy3: ethernet-phy@3 {
 125                         interrupts = <5 1 0 0>;
 126                         reg = <0x3>;
 127                         device_type = "ethernet-phy";
 128                 };
 129                 tbi0: tbi-phy@11 {
 130                         reg = <0x11>;
 131                         device_type = "tbi-phy";
 132                 };
 133         };
 134
 135         enet1: ethernet@25000 {
 136                 tbi-handle = <&tbi1>;
 137                 phy-handle = <&phy1>;
 138         };
 139
 140         mdio@25520 {
 141                 tbi1: tbi-phy@11 {
 142                         reg = <0x11>;
 143                         device_type = "tbi-phy";
 144                 };
 145         };
 146
 147         enet2: ethernet@26000 {
 148                 tbi-handle = <&tbi2>;
 149                 phy-handle = <&phy2>;
 150         };
 151
 152         mdio@26520 {
 153                 tbi2: tbi-phy@11 {
 154                         reg = <0x11>;
 155                         device_type = "tbi-phy";
 156                 };
 157         };
 158
 159         enet3: ethernet@27000 {
 160                 tbi-handle = <&tbi3>;
 161                 phy-handle = <&phy3>;
 162         };
 163
 164         mdio@27520 {
 165                 tbi3: tbi-phy@11 {
 166                         reg = <0x11>;
 167                         device_type = "tbi-phy";
 168                 };
 169         };
 170 };
 171
 172 &board_pci0 {
 173         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 174         interrupt-map = <
 175                 /* IDSEL 0x4 (PCIX Slot 2) */
 176                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 177                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 178                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 179                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 180
 181                 /* IDSEL 0x5 (PCIX Slot 3) */
 182                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
 183                 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
 184                 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
 185                 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
 186
 187                 /* IDSEL 0x6 (PCIX Slot 4) */
 188                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 189                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 190                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
 191                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 192
 193                 /* IDSEL 0x8 (PCIX Slot 5) */
 194                 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 195                 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 196                 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 197                 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 198
 199                 /* IDSEL 0xC (Tsi310 bridge) */
 200                 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 201                 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 202                 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 203                 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 204
 205                 /* IDSEL 0x14 (Slot 2) */
 206                 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 207                 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 208                 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 209                 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 210
 211                 /* IDSEL 0x15 (Slot 3) */
 212                 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
 213                 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
 214                 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
 215                 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
 216
 217                 /* IDSEL 0x16 (Slot 4) */
 218                 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 219                 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 220                 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
 221                 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 222
 223                 /* IDSEL 0x18 (Slot 5) */
 224                 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 225                 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 226                 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 227                 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 228
 229                 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 230                 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 231                 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 232                 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 233                 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
 234
 235         pci_bridge@1c {
 236                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 237                 interrupt-map = <
 238
 239                         /* IDSEL 0x00 (PrPMC Site) */
 240                         0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 241                         0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 242                         0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 243                         0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 244
 245                         /* IDSEL 0x04 (VIA chip) */
 246                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 247                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 248                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 249                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 250
 251                         /* IDSEL 0x05 (8139) */
 252                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
 253
 254                         /* IDSEL 0x06 (Slot 6) */
 255                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 256                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 257                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
 258                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 259
 260                         /* IDESL 0x07 (Slot 7) */
 261                         0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 262                         0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
 263                         0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 264                         0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
 265
 266                 reg = <0xe000 0x0 0x0 0x0 0x0>;
 267                 #interrupt-cells = <1>;
 268                 #size-cells = <2>;
 269                 #address-cells = <3>;
 270                 ranges = <0x2000000 0x0 0x80000000
 271                           0x2000000 0x0 0x80000000
 272                           0x0 0x20000000
 273                           0x1000000 0x0 0x0
 274                           0x1000000 0x0 0x0
 275                           0x0 0x80000>;
 276                 clock-frequency = <33333333>;
 277
 278                 isa@4 {
 279                         device_type = "isa";
 280                         #interrupt-cells = <2>;
 281                         #size-cells = <1>;
 282                         #address-cells = <2>;
 283                         reg = <0x2000 0x0 0x0 0x0 0x0>;
 284                         ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
 285                         interrupt-parent = <&i8259>;
 286
 287                         i8259: interrupt-controller@20 {
 288                                 interrupt-controller;
 289                                 device_type = "interrupt-controller";
 290                                 reg = <0x1 0x20 0x2
 291                                        0x1 0xa0 0x2
 292                                        0x1 0x4d0 0x2>;
 293                                 #address-cells = <0>;
 294                                 #interrupt-cells = <2>;
 295                                 compatible = "chrp,iic";
 296                                 interrupts = <0 1 0 0>;
 297                                 interrupt-parent = <&mpic>;
 298                         };
 299
 300                         rtc@70 {
 301                                 compatible = "pnpPNP,b00";
 302                                 reg = <0x1 0x70 0x2>;
 303                         };
 304                 };
 305         };
 306 };