arch/powerpc/boot/dts/mpc8569mds.dts

   1 /*
   2  * MPC8569E MDS Device Tree Source
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /include/ "fsl/mpc8569si-pre.dtsi"
  13
  14 / {
  15         model = "MPC8569EMDS";
  16         compatible = "fsl,MPC8569EMDS";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19         interrupt-parent = <&mpic>;
  20
  21         aliases {
  22                 ethernet2 = &enet2;
  23                 ethernet3 = &enet3;
  24                 ethernet5 = &enet5;
  25                 ethernet7 = &enet7;
  26                 rapidio0 = &rio;
  27         };
  28
  29         memory {
  30                 device_type = "memory";
  31         };
  32
  33         lbc: localbus@e0005000 {
  34                 reg = <0x0 0xe0005000 0x0 0x1000>;
  35
  36                 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
  37                           0x1 0x0 0x0 0xf8000000 0x00008000
  38                           0x2 0x0 0x0 0xf0000000 0x04000000
  39                           0x3 0x0 0x0 0xfc000000 0x00008000
  40                           0x4 0x0 0x0 0xf8008000 0x00008000
  41                           0x5 0x0 0x0 0xf8010000 0x00008000>;
  42
  43                 nor@0,0 {
  44                         #address-cells = <1>;
  45                         #size-cells = <1>;
  46                         compatible = "cfi-flash";
  47                         reg = <0x0 0x0 0x02000000>;
  48                         bank-width = <1>;
  49                         device-width = <1>;
  50                         partition@0 {
  51                                 label = "ramdisk";
  52                                 reg = <0x00000000 0x01c00000>;
  53                         };
  54                         partition@1c00000 {
  55                                 label = "kernel";
  56                                 reg = <0x01c00000 0x002e0000>;
  57                         };
  58                         partiton@1ee0000 {
  59                                 label = "dtb";
  60                                 reg = <0x01ee0000 0x00020000>;
  61                         };
  62                         partition@1f00000 {
  63                                 label = "firmware";
  64                                 reg = <0x01f00000 0x00080000>;
  65                                 read-only;
  66                         };
  67                         partition@1f80000 {
  68                                 label = "u-boot";
  69                                 reg = <0x01f80000 0x00080000>;
  70                                 read-only;
  71                         };
  72                 };
  73
  74                 bcsr@1,0 {
  75                         #address-cells = <1>;
  76                         #size-cells = <1>;
  77                         compatible = "fsl,mpc8569mds-bcsr";
  78                         reg = <1 0 0x8000>;
  79                         ranges = <0 1 0 0x8000>;
  80
  81                         bcsr17: gpio-controller@11 {
  82                                 #gpio-cells = <2>;
  83                                 compatible = "fsl,mpc8569mds-bcsr-gpio";
  84                                 reg = <0x11 0x1>;
  85                                 gpio-controller;
  86                         };
  87                 };
  88
  89                 nand@3,0 {
  90                         compatible = "fsl,mpc8569-fcm-nand",
  91                                      "fsl,elbc-fcm-nand";
  92                         reg = <3 0 0x8000>;
  93                 };
  94
  95                 pib@4,0 {
  96                         compatible = "fsl,mpc8569mds-pib";
  97                         reg = <4 0 0x8000>;
  98                 };
  99
 100                 pib@5,0 {
 101                         compatible = "fsl,mpc8569mds-pib";
 102                         reg = <5 0 0x8000>;
 103                 };
 104         };
 105
 106         soc: soc@e0000000 {
 107                 ranges = <0x0 0x0 0xe0000000 0x100000>;
 108
 109                 i2c-sleep-nexus {
 110                         i2c@3000 {
 111                                 rtc@68 {
 112                                         compatible = "dallas,ds1374";
 113                                         reg = <0x68>;
 114                                         interrupts = <3 1 0 0>;
 115                                 };
 116                         };
 117                 };
 118
 119                 sdhc@2e000 {
 120                         status = "disabled";
 121                         sdhci,1-bit-only;
 122                         bus-width = <1>;
 123                 };
 124
 125                 par_io@e0100 {
 126                         num-ports = <7>;
 127
 128                         qe_pio_e: gpio-controller@80 {
 129                                 #gpio-cells = <2>;
 130                                 compatible = "fsl,mpc8569-qe-pario-bank",
 131                                              "fsl,mpc8323-qe-pario-bank";
 132                                 reg = <0x80 0x18>;
 133                                 gpio-controller;
 134                         };
 135
 136                         qe_pio_f: gpio-controller@a0 {
 137                                 #gpio-cells = <2>;
 138                                 compatible = "fsl,mpc8569-qe-pario-bank",
 139                                              "fsl,mpc8323-qe-pario-bank";
 140                                 reg = <0xa0 0x18>;
 141                                 gpio-controller;
 142                         };
 143
 144                         pio1: ucc_pin@01 {
 145                                 pio-map = <
 146                         /* port  pin  dir  open_drain  assignment  has_irq */
 147                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 148                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 149                                         0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
 150                                         0x0  0x0  0x1  0x0  0x3  0x0    /* ENET1_TXD0_SER1_TXD0 */
 151                                         0x0  0x1  0x1  0x0  0x3  0x0    /* ENET1_TXD1_SER1_TXD1 */
 152                                         0x0  0x2  0x1  0x0  0x1  0x0    /* ENET1_TXD2_SER1_TXD2 */
 153                                         0x0  0x3  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
 154                                         0x0  0x6  0x2  0x0  0x3  0x0    /* ENET1_RXD0_SER1_RXD0 */
 155                                         0x0  0x7  0x2  0x0  0x1  0x0    /* ENET1_RXD1_SER1_RXD1 */
 156                                         0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
 157                                         0x0  0x9  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
 158                                         0x0  0x4  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
 159                                         0x0  0xc  0x2  0x0  0x3  0x0    /* ENET1_RX_DV_SER1_CTS_B */
 160                                         0x2  0x8  0x2  0x0  0x1  0x0    /* ENET1_GRXCLK */
 161                                         0x2  0x14 0x1  0x0  0x2  0x0>;  /* ENET1_GTXCLK */
 162                         };
 163
 164                         pio2: ucc_pin@02 {
 165                                 pio-map = <
 166                         /* port  pin  dir  open_drain  assignment  has_irq */
 167                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 168                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 169                                         0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
 170                                         0x0  0xe  0x1  0x0  0x2  0x0    /* ENET2_TXD0_SER2_TXD0 */
 171                                         0x0  0xf  0x1  0x0  0x2  0x0    /* ENET2_TXD1_SER2_TXD1 */
 172                                         0x0  0x10 0x1  0x0  0x1  0x0    /* ENET2_TXD2_SER2_TXD2 */
 173                                         0x0  0x11 0x1  0x0  0x1  0x0    /* ENET2_TXD3_SER2_TXD3 */
 174                                         0x0  0x14 0x2  0x0  0x2  0x0    /* ENET2_RXD0_SER2_RXD0 */
 175                                         0x0  0x15 0x2  0x0  0x1  0x0    /* ENET2_RXD1_SER2_RXD1 */
 176                                         0x0  0x16 0x2  0x0  0x1  0x0    /* ENET2_RXD2_SER2_RXD2 */
 177                                         0x0  0x17 0x2  0x0  0x1  0x0    /* ENET2_RXD3_SER2_RXD3 */
 178                                         0x0  0x12 0x1  0x0  0x2  0x0    /* ENET2_TX_EN_SER2_RTS_B */
 179                                         0x0  0x1a 0x2  0x0  0x3  0x0    /* ENET2_RX_DV_SER2_CTS_B */
 180                                         0x2  0x3  0x2  0x0  0x1  0x0    /* ENET2_GRXCLK */
 181                                         0x2  0x2 0x1  0x0  0x2  0x0>;   /* ENET2_GTXCLK */
 182                         };
 183
 184                         pio3: ucc_pin@03 {
 185                                 pio-map = <
 186                         /* port  pin  dir  open_drain  assignment  has_irq */
 187                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 188                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 189                                         0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
 190                                         0x0  0x1d 0x1  0x0  0x2  0x0    /* ENET3_TXD0_SER3_TXD0 */
 191                                         0x0  0x1e 0x1  0x0  0x3  0x0    /* ENET3_TXD1_SER3_TXD1 */
 192                                         0x0  0x1f 0x1  0x0  0x2  0x0    /* ENET3_TXD2_SER3_TXD2 */
 193                                         0x1  0x0  0x1  0x0  0x3  0x0    /* ENET3_TXD3_SER3_TXD3 */
 194                                         0x1  0x3  0x2  0x0  0x3  0x0    /* ENET3_RXD0_SER3_RXD0 */
 195                                         0x1  0x4  0x2  0x0  0x1  0x0    /* ENET3_RXD1_SER3_RXD1 */
 196                                         0x1  0x5  0x2  0x0  0x2  0x0    /* ENET3_RXD2_SER3_RXD2 */
 197                                         0x1  0x6  0x2  0x0  0x3  0x0    /* ENET3_RXD3_SER3_RXD3 */
 198                                         0x1  0x1  0x1  0x0  0x1  0x0    /* ENET3_TX_EN_SER3_RTS_B */
 199                                         0x1  0x9  0x2  0x0  0x3  0x0    /* ENET3_RX_DV_SER3_CTS_B */
 200                                         0x2  0x9  0x2  0x0  0x2  0x0    /* ENET3_GRXCLK */
 201                                         0x2  0x19 0x1  0x0  0x2  0x0>;  /* ENET3_GTXCLK */
 202                         };
 203
 204                         pio4: ucc_pin@04 {
 205                                 pio-map = <
 206                         /* port  pin  dir  open_drain  assignment  has_irq */
 207                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 208                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 209                                         0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
 210                                         0x1  0xc  0x1  0x0  0x2  0x0    /* ENET4_TXD0_SER4_TXD0 */
 211                                         0x1  0xd  0x1  0x0  0x2  0x0    /* ENET4_TXD1_SER4_TXD1 */
 212                                         0x1  0xe  0x1  0x0  0x1  0x0    /* ENET4_TXD2_SER4_TXD2 */
 213                                         0x1  0xf  0x1  0x0  0x2  0x0    /* ENET4_TXD3_SER4_TXD3 */
 214                                         0x1  0x12 0x2  0x0  0x2  0x0    /* ENET4_RXD0_SER4_RXD0 */
 215                                         0x1  0x13 0x2  0x0  0x1  0x0    /* ENET4_RXD1_SER4_RXD1 */
 216                                         0x1  0x14 0x2  0x0  0x1  0x0    /* ENET4_RXD2_SER4_RXD2 */
 217                                         0x1  0x15 0x2  0x0  0x2  0x0    /* ENET4_RXD3_SER4_RXD3 */
 218                                         0x1  0x10 0x1  0x0  0x2  0x0    /* ENET4_TX_EN_SER4_RTS_B */
 219                                         0x1  0x18 0x2  0x0  0x3  0x0    /* ENET4_RX_DV_SER4_CTS_B */
 220                                         0x2  0x11 0x2  0x0  0x2  0x0    /* ENET4_GRXCLK */
 221                                         0x2  0x18 0x1  0x0  0x2  0x0>;  /* ENET4_GTXCLK */
 222                         };
 223                 };
 224         };
 225
 226         qe: qe@e0080000 {
 227                 ranges = <0x0 0x0 0xe0080000 0x40000>;
 228                 reg = <0x0 0xe0080000 0x0 0x480>;
 229
 230                 spi@4c0 {
 231                         gpios = <&qe_pio_e 30 0>;
 232                         mode = "cpu-qe";
 233
 234                         serial-flash@0 {
 235                                 compatible = "stm,m25p40";
 236                                 reg = <0>;
 237                                 spi-max-frequency = <25000000>;
 238                         };
 239                 };
 240
 241                 spi@500 {
 242                         mode = "cpu";
 243                 };
 244
 245                 usb@6c0 {
 246                         fsl,fullspeed-clock = "clk5";
 247                         fsl,lowspeed-clock = "brg10";
 248                         gpios = <&qe_pio_f 3 0   /* USBOE */
 249                                  &qe_pio_f 4 0   /* USBTP */
 250                                  &qe_pio_f 5 0   /* USBTN */
 251                                  &qe_pio_f 6 0   /* USBRP */
 252                                  &qe_pio_f 8 0   /* USBRN */
 253                                  &bcsr17   1 0   /* SPEED */
 254                                  &bcsr17   2 0>; /* POWER */
 255                 };
 256
 257                 enet0: ucc@2000 {
 258                         device_type = "network";
 259                         compatible = "ucc_geth";
 260                         local-mac-address = [ 00 00 00 00 00 00 ];
 261                         rx-clock-name = "none";
 262                         tx-clock-name = "clk12";
 263                         pio-handle = <&pio1>;
 264                         tbi-handle = <&tbi1>;
 265                         phy-handle = <&qe_phy0>;
 266                         phy-connection-type = "rgmii-id";
 267                 };
 268
 269                 mdio@2120 {
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                         reg = <0x2120 0x18>;
 273                         compatible = "fsl,ucc-mdio";
 274
 275                         qe_phy0: ethernet-phy@07 {
 276                                 interrupt-parent = <&mpic>;
 277                                 interrupts = <1 1 0 0>;
 278                                 reg = <0x7>;
 279                                 device_type = "ethernet-phy";
 280                         };
 281                         qe_phy1: ethernet-phy@01 {
 282                                 interrupt-parent = <&mpic>;
 283                                 interrupts = <2 1 0 0>;
 284                                 reg = <0x1>;
 285                                 device_type = "ethernet-phy";
 286                         };
 287                         qe_phy2: ethernet-phy@02 {
 288                                 interrupt-parent = <&mpic>;
 289                                 interrupts = <3 1 0 0>;
 290                                 reg = <0x2>;
 291                                 device_type = "ethernet-phy";
 292                         };
 293                         qe_phy3: ethernet-phy@03 {
 294                                 interrupt-parent = <&mpic>;
 295                                 interrupts = <4 1 0 0>;
 296                                 reg = <0x3>;
 297                                 device_type = "ethernet-phy";
 298                         };
 299                         qe_phy5: ethernet-phy@04 {
 300                                 reg = <0x04>;
 301                                 device_type = "ethernet-phy";
 302                         };
 303                         qe_phy7: ethernet-phy@06 {
 304                                 reg = <0x6>;
 305                                 device_type = "ethernet-phy";
 306                         };
 307                         tbi1: tbi-phy@11 {
 308                                 reg = <0x11>;
 309                                 device_type = "tbi-phy";
 310                         };
 311                 };
 312                 mdio@3520 {
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315                         reg = <0x3520 0x18>;
 316                         compatible = "fsl,ucc-mdio";
 317
 318                         tbi6: tbi-phy@15 {
 319                         reg = <0x15>;
 320                         device_type = "tbi-phy";
 321                         };
 322                 };
 323                 mdio@3720 {
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                         reg = <0x3720 0x38>;
 327                         compatible = "fsl,ucc-mdio";
 328                         tbi8: tbi-phy@17 {
 329                                 reg = <0x17>;
 330                                 device_type = "tbi-phy";
 331                         };
 332                 };
 333
 334                 enet2: ucc@2200 {
 335                         device_type = "network";
 336                         compatible = "ucc_geth";
 337                         local-mac-address = [ 00 00 00 00 00 00 ];
 338                         rx-clock-name = "none";
 339                         tx-clock-name = "clk12";
 340                         pio-handle = <&pio3>;
 341                         tbi-handle = <&tbi3>;
 342                         phy-handle = <&qe_phy2>;
 343                         phy-connection-type = "rgmii-id";
 344                 };
 345
 346                 mdio@2320 {
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         reg = <0x2320 0x18>;
 350                         compatible = "fsl,ucc-mdio";
 351                         tbi3: tbi-phy@11 {
 352                                 reg = <0x11>;
 353                                 device_type = "tbi-phy";
 354                         };
 355                 };
 356
 357                 enet1: ucc@3000 {
 358                         device_type = "network";
 359                         compatible = "ucc_geth";
 360                         local-mac-address = [ 00 00 00 00 00 00 ];
 361                         rx-clock-name = "none";
 362                         tx-clock-name = "clk17";
 363                         pio-handle = <&pio2>;
 364                         tbi-handle = <&tbi2>;
 365                         phy-handle = <&qe_phy1>;
 366                         phy-connection-type = "rgmii-id";
 367                 };
 368
 369                 mdio@3120 {
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         reg = <0x3120 0x18>;
 373                         compatible = "fsl,ucc-mdio";
 374                         tbi2: tbi-phy@11 {
 375                                 reg = <0x11>;
 376                                 device_type = "tbi-phy";
 377                         };
 378                 };
 379
 380                 enet3: ucc@3200 {
 381                         device_type = "network";
 382                         compatible = "ucc_geth";
 383                         local-mac-address = [ 00 00 00 00 00 00 ];
 384                         rx-clock-name = "none";
 385                         tx-clock-name = "clk17";
 386                         pio-handle = <&pio4>;
 387                         tbi-handle = <&tbi4>;
 388                         phy-handle = <&qe_phy3>;
 389                         phy-connection-type = "rgmii-id";
 390                 };
 391
 392                 mdio@3320 {
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         reg = <0x3320 0x18>;
 396                         compatible = "fsl,ucc-mdio";
 397                         tbi4: tbi-phy@11 {
 398                                 reg = <0x11>;
 399                                 device_type = "tbi-phy";
 400                         };
 401                 };
 402
 403                 enet5: ucc@3400 {
 404                         device_type = "network";
 405                         compatible = "ucc_geth";
 406                         local-mac-address = [ 00 00 00 00 00 00 ];
 407                         rx-clock-name = "none";
 408                         tx-clock-name = "none";
 409                         tbi-handle = <&tbi6>;
 410                         phy-handle = <&qe_phy5>;
 411                         phy-connection-type = "sgmii";
 412                 };
 413
 414                 enet7: ucc@3600 {
 415                         device_type = "network";
 416                         compatible = "ucc_geth";
 417                         local-mac-address = [ 00 00 00 00 00 00 ];
 418                         rx-clock-name = "none";
 419                         tx-clock-name = "none";
 420                         tbi-handle = <&tbi8>;
 421                         phy-handle = <&qe_phy7>;
 422                         phy-connection-type = "sgmii";
 423                 };
 424         };
 425
 426         /* PCI Express */
 427         pci1: pcie@e000a000 {
 428                 reg = <0x0 0xe000a000 0x0 0x1000>;
 429                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
 430                           0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
 431                 pcie@0 {
 432                         ranges = <0x2000000 0x0 0xa0000000
 433                                   0x2000000 0x0 0xa0000000
 434                                   0x0 0x10000000
 435
 436                                   0x1000000 0x0 0x0
 437                                   0x1000000 0x0 0x0
 438                                   0x0 0x800000>;
 439                 };
 440         };
 441
 442         rio: rapidio@e00c00000 {
 443                 reg = <0x0 0xe00c0000 0x0 0x20000>;
 444                 port1 {
 445                         ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
 446                 };
 447                 port2 {
 448                         status = "disabled";
 449                 };
 450         };
 451 };
 452
 453 /include/ "fsl/mpc8569si-post.dtsi"