2 * P2020DS Device Tree Source stub (no addresses or top-level ranges)
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39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
55 reg = <0x03e00000 0x00200000>;
60 reg = <0x04000000 0x00400000>;
65 reg = <0x04400000 0x03b00000>;
69 reg = <0x07f00000 0x00080000>;
74 reg = <0x07f80000 0x00080000>;
82 compatible = "fsl,elbc-fcm-nand";
83 reg = <0x2 0x0 0x40000>;
86 reg = <0x0 0x02000000>;
91 reg = <0x02000000 0x10000000>;
95 reg = <0x12000000 0x08000000>;
100 reg = <0x1a000000 0x04000000>;
104 reg = <0x1e000000 0x01000000>;
109 reg = <0x1f000000 0x21000000>;
114 compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
115 reg = <0x3 0x0 0x30>;
119 compatible = "fsl,elbc-fcm-nand";
120 reg = <0x4 0x0 0x40000>;
124 compatible = "fsl,elbc-fcm-nand";
125 reg = <0x5 0x0 0x40000>;
129 compatible = "fsl,elbc-fcm-nand";
130 reg = <0x6 0x0 0x40000>;
140 phy0: ethernet-phy@0 {
141 interrupts = <3 1 0 0>;
144 phy1: ethernet-phy@1 {
145 interrupts = <3 1 0 0>;
148 phy2: ethernet-phy@2 {
149 interrupts = <3 1 0 0>;
154 device_type = "tbi-phy";
162 device_type = "tbi-phy";
169 device_type = "tbi-phy";
175 fsl,tclk-period = <5>;
176 fsl,tmr-prsc = <200>;
177 fsl,tmr-add = <0xCCCCCCCD>;
178 fsl,tmr-fiper1 = <0x3B9AC9FB>;
179 fsl,tmr-fiper2 = <0x0001869B>;
180 fsl,max-adj = <249999999>;
183 enet0: ethernet@24000 {
184 tbi-handle = <&tbi0>;
185 phy-handle = <&phy0>;
186 phy-connection-type = "rgmii-id";
189 enet1: ethernet@25000 {
190 tbi-handle = <&tbi1>;
191 phy-handle = <&phy1>;
192 phy-connection-type = "rgmii-id";
196 enet2: ethernet@26000 {
197 tbi-handle = <&tbi2>;
198 phy-handle = <&phy2>;
199 phy-connection-type = "rgmii-id";
205 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
208 // IDSEL 0x11 func 0 - PCI slot 1
209 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
210 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
212 // IDSEL 0x11 func 1 - PCI slot 1
213 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
214 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
216 // IDSEL 0x11 func 2 - PCI slot 1
217 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
218 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
220 // IDSEL 0x11 func 3 - PCI slot 1
221 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
222 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
224 // IDSEL 0x11 func 4 - PCI slot 1
225 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
226 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
228 // IDSEL 0x11 func 5 - PCI slot 1
229 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
230 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
232 // IDSEL 0x11 func 6 - PCI slot 1
233 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
234 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
236 // IDSEL 0x11 func 7 - PCI slot 1
237 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
238 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
241 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
244 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
245 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
247 // IDSEL 0x1f IDE/SATA
248 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
249 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
253 reg = <0x0 0x0 0x0 0x0 0x0>;
255 #address-cells = <3>;
256 ranges = <0x2000000 0x0 0xa0000000
257 0x2000000 0x0 0xa0000000
265 #interrupt-cells = <2>;
267 #address-cells = <2>;
268 reg = <0xf000 0x0 0x0 0x0 0x0>;
269 ranges = <0x1 0x0 0x1000000 0x0 0x0
271 interrupt-parent = <&i8259>;
273 i8259: interrupt-controller@20 {
277 interrupt-controller;
278 device_type = "interrupt-controller";
279 #address-cells = <0>;
280 #interrupt-cells = <2>;
281 compatible = "chrp,iic";
282 interrupts = <4 1 0 0>;
283 interrupt-parent = <&mpic>;
288 #address-cells = <1>;
289 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
290 interrupts = <1 3 12 3>;
296 compatible = "pnpPNP,303";
301 compatible = "pnpPNP,f03";
306 compatible = "pnpPNP,b00";
307 reg = <0x1 0x70 0x2>;
311 reg = <0x1 0x400 0x80>;