arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 /*
  11  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  12  * Based on code from spd_sdram.c
  13  * Author: James Yang [at freescale.com]
  14  */
  15
  16 #include <common.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 #ifdef CONFIG_MPC85xx
  22         #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
  23 #elif defined(CONFIG_MPC86xx)
  24         #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
  25 #else
  26         #error "Undefined _DDR_ADDR"
  27 #endif
  28
  29 u32 fsl_ddr_get_version(void)
  30 {
  31         ccsr_ddr_t *ddr;
  32         u32 ver_major_minor_errata;
  33
  34         ddr = (void *)_DDR_ADDR;
  35         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  36         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  37
  38         return ver_major_minor_errata;
  39 }
  40
  41 unsigned int picos_to_mclk(unsigned int picos);
  42
  43 /*
  44  * Determine Rtt value.
  45  *
  46  * This should likely be either board or controller specific.
  47  *
  48  * Rtt(nominal) - DDR2:
  49  *      0 = Rtt disabled
  50  *      1 = 75 ohm
  51  *      2 = 150 ohm
  52  *      3 = 50 ohm
  53  * Rtt(nominal) - DDR3:
  54  *      0 = Rtt disabled
  55  *      1 = 60 ohm
  56  *      2 = 120 ohm
  57  *      3 = 40 ohm
  58  *      4 = 20 ohm
  59  *      5 = 30 ohm
  60  *
  61  * FIXME: Apparently 8641 needs a value of 2
  62  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  63  *
  64  * FIXME: There was some effort down this line earlier:
  65  *
  66  *      unsigned int i;
  67  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  68  *              if (popts->dimmslot[i].num_valid_cs
  69  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  70  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  71  *                      rtt = 2;
  72  *                      break;
  73  *              }
  74  *      }
  75  */
  76 static inline int fsl_ddr_get_rtt(void)
  77 {
  78         int rtt;
  79
  80 #if defined(CONFIG_FSL_DDR1)
  81         rtt = 0;
  82 #elif defined(CONFIG_FSL_DDR2)
  83         rtt = 3;
  84 #else
  85         rtt = 0;
  86 #endif
  87
  88         return rtt;
  89 }
  90
  91 /*
  92  * compute the CAS write latency according to DDR3 spec
  93  * CWL = 5 if tCK >= 2.5ns
  94  *       6 if 2.5ns > tCK >= 1.875ns
  95  *       7 if 1.875ns > tCK >= 1.5ns
  96  *       8 if 1.5ns > tCK >= 1.25ns
  97  */
  98 static inline unsigned int compute_cas_write_latency(void)
  99 {
 100         unsigned int cwl;
 101         const unsigned int mclk_ps = get_memory_clk_period_ps();
 102
 103         if (mclk_ps >= 2500)
 104                 cwl = 5;
 105         else if (mclk_ps >= 1875)
 106                 cwl = 6;
 107         else if (mclk_ps >= 1500)
 108                 cwl = 7;
 109         else if (mclk_ps >= 1250)
 110                 cwl = 8;
 111         else
 112                 cwl = 8;
 113         return cwl;
 114 }
 115
 116 /* Chip Select Configuration (CSn_CONFIG) */
 117 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 118                                const memctl_options_t *popts,
 119                                const dimm_params_t *dimm_params)
 120 {
 121         unsigned int cs_n_en = 0; /* Chip Select enable */
 122         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 123         unsigned int intlv_ctl = 0; /* Interleaving control */
 124         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 125         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 126         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 127         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 128         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 129         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 130         int go_config = 0;
 131
 132         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 133         switch (i) {
 134         case 0:
 135                 if (dimm_params[dimm_number].n_ranks > 0) {
 136                         go_config = 1;
 137                         /* These fields only available in CS0_CONFIG */
 138                         intlv_en = popts->memctl_interleaving;
 139                         intlv_ctl = popts->memctl_interleaving_mode;
 140                 }
 141                 break;
 142         case 1:
 143                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 144                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 145                         go_config = 1;
 146                 break;
 147         case 2:
 148                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 149                    (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
 150                         go_config = 1;
 151                 break;
 152         case 3:
 153                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 154                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 155                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 156                         go_config = 1;
 157                 break;
 158         default:
 159                 break;
 160         }
 161         if (go_config) {
 162                 unsigned int n_banks_per_sdram_device;
 163                 cs_n_en = 1;
 164                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 165                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 166                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 167                 n_banks_per_sdram_device
 168                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 169                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 170                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 171                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 172         }
 173         ddr->cs[i].config = (0
 174                 | ((cs_n_en & 0x1) << 31)
 175                 | ((intlv_en & 0x3) << 29)
 176                 | ((intlv_ctl & 0xf) << 24)
 177                 | ((ap_n_en & 0x1) << 23)
 178
 179                 /* XXX: some implementation only have 1 bit starting at left */
 180                 | ((odt_rd_cfg & 0x7) << 20)
 181
 182                 /* XXX: Some implementation only have 1 bit starting at left */
 183                 | ((odt_wr_cfg & 0x7) << 16)
 184
 185                 | ((ba_bits_cs_n & 0x3) << 14)
 186                 | ((row_bits_cs_n & 0x7) << 8)
 187                 | ((col_bits_cs_n & 0x7) << 0)
 188                 );
 189         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 190 }
 191
 192 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 193 /* FIXME: 8572 */
 194 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 195 {
 196         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 197
 198         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 199         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 200 }
 201
 202 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 203
 204 #if !defined(CONFIG_FSL_DDR1)
 205 /*
 206  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 207  *
 208  * Avoid writing for DDR I.  The new PQ38 DDR controller
 209  * dreams up non-zero default values to be backwards compatible.
 210  */
 211 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 212                                 const memctl_options_t *popts)
 213 {
 214         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 215         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 216         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 217         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 218         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 219
 220         /* Active powerdown exit timing (tXARD and tXARDS). */
 221         unsigned char act_pd_exit_mclk;
 222         /* Precharge powerdown exit timing (tXP). */
 223         unsigned char pre_pd_exit_mclk;
 224         /* ODT powerdown exit timing (tAXPD). */
 225         unsigned char taxpd_mclk;
 226         /* Mode register set cycle time (tMRD). */
 227         unsigned char tmrd_mclk;
 228
 229 #ifdef CONFIG_FSL_DDR3
 230         /*
 231          * (tXARD and tXARDS). Empirical?
 232          * The DDR3 spec has not tXARD,
 233          * we use the tXP instead of it.
 234          * tXP=max(3nCK, 7.5ns) for DDR3.
 235          * spec has not the tAXPD, we use
 236          * tAXPD=1, need design to confirm.
 237          */
 238         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 239         unsigned int data_rate = fsl_ddr_get_mem_data_rate();
 240         tmrd_mclk = 4;
 241         /* set the turnaround time */
 242         trwt_mclk = 1;
 243         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 244                 twrt_mclk = 1;
 245
 246         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 247                 act_pd_exit_mclk = 1;
 248                 pre_pd_exit_mclk = 1;
 249                 taxpd_mclk = 1;
 250         } else {
 251                 /* act_pd_exit_mclk = tXARD, see above */
 252                 act_pd_exit_mclk = picos_to_mclk(tXP);
 253                 /* Mode register MR0[A12] is '1' - fast exit */
 254                 pre_pd_exit_mclk = act_pd_exit_mclk;
 255                 taxpd_mclk = 1;
 256         }
 257 #else /* CONFIG_FSL_DDR2 */
 258         /*
 259          * (tXARD and tXARDS). Empirical?
 260          * tXARD = 2 for DDR2
 261          * tXP=2
 262          * tAXPD=8
 263          */
 264         act_pd_exit_mclk = 2;
 265         pre_pd_exit_mclk = 2;
 266         taxpd_mclk = 8;
 267         tmrd_mclk = 2;
 268 #endif
 269
 270         ddr->timing_cfg_0 = (0
 271                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 272                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 273                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 274                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 275                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 276                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 277                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 278                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 279                 );
 280         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 281 }
 282 #endif  /* defined(CONFIG_FSL_DDR2) */
 283
 284 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 285 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 286                                const common_timing_params_t *common_dimm,
 287                                unsigned int cas_latency)
 288 {
 289         /* Extended Activate to precharge interval (tRAS) */
 290         unsigned int ext_acttopre = 0;
 291         unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
 292         unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
 293         unsigned int cntl_adj = 0; /* Control Adjust */
 294
 295         /* If the tRAS > 19 MCLK, we use the ext mode */
 296         if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
 297                 ext_acttopre = 1;
 298
 299         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 300
 301         /* If the CAS latency more than 8, use the ext mode */
 302         if (cas_latency > 8)
 303                 ext_caslat = 1;
 304
 305         ddr->timing_cfg_3 = (0
 306                 | ((ext_acttopre & 0x1) << 24)
 307                 | ((ext_refrec & 0xF) << 16)
 308                 | ((ext_caslat & 0x1) << 12)
 309                 | ((cntl_adj & 0x7) << 0)
 310                 );
 311         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 312 }
 313
 314 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 315 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 316                                const memctl_options_t *popts,
 317                                const common_timing_params_t *common_dimm,
 318                                unsigned int cas_latency)
 319 {
 320         /* Precharge-to-activate interval (tRP) */
 321         unsigned char pretoact_mclk;
 322         /* Activate to precharge interval (tRAS) */
 323         unsigned char acttopre_mclk;
 324         /*  Activate to read/write interval (tRCD) */
 325         unsigned char acttorw_mclk;
 326         /* CASLAT */
 327         unsigned char caslat_ctrl;
 328         /*  Refresh recovery time (tRFC) ; trfc_low */
 329         unsigned char refrec_ctrl;
 330         /* Last data to precharge minimum interval (tWR) */
 331         unsigned char wrrec_mclk;
 332         /* Activate-to-activate interval (tRRD) */
 333         unsigned char acttoact_mclk;
 334         /* Last write data pair to read command issue interval (tWTR) */
 335         unsigned char wrtord_mclk;
 336
 337         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 338         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 339         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 340
 341         /*
 342          * Translate CAS Latency to a DDR controller field value:
 343          *
 344          *      CAS Lat DDR I   DDR II  Ctrl
 345          *      Clocks  SPD Bit SPD Bit Value
 346          *      ------- ------- ------- -----
 347          *      1.0     0               0001
 348          *      1.5     1               0010
 349          *      2.0     2       2       0011
 350          *      2.5     3               0100
 351          *      3.0     4       3       0101
 352          *      3.5     5               0110
 353          *      4.0             4       0111
 354          *      4.5                     1000
 355          *      5.0             5       1001
 356          */
 357 #if defined(CONFIG_FSL_DDR1)
 358         caslat_ctrl = (cas_latency + 1) & 0x07;
 359 #elif defined(CONFIG_FSL_DDR2)
 360         caslat_ctrl = 2 * cas_latency - 1;
 361 #else
 362         /*
 363          * if the CAS latency more than 8 cycle,
 364          * we need set extend bit for it at
 365          * TIMING_CFG_3[EXT_CASLAT]
 366          */
 367         if (cas_latency > 8)
 368                 cas_latency -= 8;
 369         caslat_ctrl = 2 * cas_latency - 1;
 370 #endif
 371
 372         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 373         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 374         if (popts->OTF_burst_chop_en)
 375                 wrrec_mclk += 2;
 376
 377         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 378         /*
 379          * JEDEC has min requirement for tRRD
 380          */
 381 #if defined(CONFIG_FSL_DDR3)
 382         if (acttoact_mclk < 4)
 383                 acttoact_mclk = 4;
 384 #endif
 385         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 386         /*
 387          * JEDEC has some min requirements for tWTR
 388          */
 389 #if defined(CONFIG_FSL_DDR2)
 390         if (wrtord_mclk < 2)
 391                 wrtord_mclk = 2;
 392 #elif defined(CONFIG_FSL_DDR3)
 393         if (wrtord_mclk < 4)
 394                 wrtord_mclk = 4;
 395 #endif
 396         if (popts->OTF_burst_chop_en)
 397                 wrtord_mclk += 2;
 398
 399         ddr->timing_cfg_1 = (0
 400                 | ((pretoact_mclk & 0x0F) << 28)
 401                 | ((acttopre_mclk & 0x0F) << 24)
 402                 | ((acttorw_mclk & 0xF) << 20)
 403                 | ((caslat_ctrl & 0xF) << 16)
 404                 | ((refrec_ctrl & 0xF) << 12)
 405                 | ((wrrec_mclk & 0x0F) << 8)
 406                 | ((acttoact_mclk & 0x07) << 4)
 407                 | ((wrtord_mclk & 0x07) << 0)
 408                 );
 409         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 410 }
 411
 412 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 413 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 414                                const memctl_options_t *popts,
 415                                const common_timing_params_t *common_dimm,
 416                                unsigned int cas_latency,
 417                                unsigned int additive_latency)
 418 {
 419         /* Additive latency */
 420         unsigned char add_lat_mclk;
 421         /* CAS-to-preamble override */
 422         unsigned short cpo;
 423         /* Write latency */
 424         unsigned char wr_lat;
 425         /*  Read to precharge (tRTP) */
 426         unsigned char rd_to_pre;
 427         /* Write command to write data strobe timing adjustment */
 428         unsigned char wr_data_delay;
 429         /* Minimum CKE pulse width (tCKE) */
 430         unsigned char cke_pls;
 431         /* Window for four activates (tFAW) */
 432         unsigned short four_act;
 433
 434         /* FIXME add check that this must be less than acttorw_mclk */
 435         add_lat_mclk = additive_latency;
 436         cpo = popts->cpo_override;
 437
 438 #if defined(CONFIG_FSL_DDR1)
 439         /*
 440          * This is a lie.  It should really be 1, but if it is
 441          * set to 1, bits overlap into the old controller's
 442          * otherwise unused ACSM field.  If we leave it 0, then
 443          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 444          */
 445         wr_lat = 0;
 446 #elif defined(CONFIG_FSL_DDR2)
 447         wr_lat = cas_latency - 1;
 448 #else
 449         wr_lat = compute_cas_write_latency();
 450 #endif
 451
 452         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 453         /*
 454          * JEDEC has some min requirements for tRTP
 455          */
 456 #if defined(CONFIG_FSL_DDR2)
 457         if (rd_to_pre  < 2)
 458                 rd_to_pre  = 2;
 459 #elif defined(CONFIG_FSL_DDR3)
 460         if (rd_to_pre < 4)
 461                 rd_to_pre = 4;
 462 #endif
 463         if (additive_latency)
 464                 rd_to_pre += additive_latency;
 465         if (popts->OTF_burst_chop_en)
 466                 rd_to_pre += 2; /* according to UM */
 467
 468         wr_data_delay = popts->write_data_delay;
 469         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 470         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 471
 472         ddr->timing_cfg_2 = (0
 473                 | ((add_lat_mclk & 0xf) << 28)
 474                 | ((cpo & 0x1f) << 23)
 475                 | ((wr_lat & 0xf) << 19)
 476                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 477                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 478                 | ((cke_pls & 0x7) << 6)
 479                 | ((four_act & 0x3f) << 0)
 480                 );
 481         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 482 }
 483
 484 /* DDR SDRAM Register Control Word */
 485 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 486                                const memctl_options_t *popts,
 487                                const common_timing_params_t *common_dimm)
 488 {
 489         if (common_dimm->all_DIMMs_registered
 490                 && !common_dimm->all_DIMMs_unbuffered) {
 491                 if (popts->rcw_override) {
 492                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 493                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 494                 } else {
 495                         ddr->ddr_sdram_rcw_1 =
 496                                 common_dimm->rcw[0] << 28 | \
 497                                 common_dimm->rcw[1] << 24 | \
 498                                 common_dimm->rcw[2] << 20 | \
 499                                 common_dimm->rcw[3] << 16 | \
 500                                 common_dimm->rcw[4] << 12 | \
 501                                 common_dimm->rcw[5] << 8 | \
 502                                 common_dimm->rcw[6] << 4 | \
 503                                 common_dimm->rcw[7];
 504                         ddr->ddr_sdram_rcw_2 =
 505                                 common_dimm->rcw[8] << 28 | \
 506                                 common_dimm->rcw[9] << 24 | \
 507                                 common_dimm->rcw[10] << 20 | \
 508                                 common_dimm->rcw[11] << 16 | \
 509                                 common_dimm->rcw[12] << 12 | \
 510                                 common_dimm->rcw[13] << 8 | \
 511                                 common_dimm->rcw[14] << 4 | \
 512                                 common_dimm->rcw[15];
 513                 }
 514                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 515                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 516         }
 517 }
 518
 519 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 520 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 521                                const memctl_options_t *popts,
 522                                const common_timing_params_t *common_dimm)
 523 {
 524         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 525         unsigned int sren;              /* Self refresh enable (during sleep) */
 526         unsigned int ecc_en;            /* ECC enable. */
 527         unsigned int rd_en;             /* Registered DIMM enable */
 528         unsigned int sdram_type;        /* Type of SDRAM */
 529         unsigned int dyn_pwr;           /* Dynamic power management mode */
 530         unsigned int dbw;               /* DRAM dta bus width */
 531         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 532         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 533         unsigned int threeT_en;         /* Enable 3T timing */
 534         unsigned int twoT_en;           /* Enable 2T timing */
 535         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 536         unsigned int x32_en = 0;        /* x32 enable */
 537         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 538         unsigned int hse;               /* Global half strength override */
 539         unsigned int mem_halt = 0;      /* memory controller halt */
 540         unsigned int bi = 0;            /* Bypass initialization */
 541
 542         mem_en = 1;
 543         sren = popts->self_refresh_in_sleep;
 544         if (common_dimm->all_DIMMs_ECC_capable) {
 545                 /* Allow setting of ECC only if all DIMMs are ECC. */
 546                 ecc_en = popts->ECC_mode;
 547         } else {
 548                 ecc_en = 0;
 549         }
 550
 551         if (common_dimm->all_DIMMs_registered
 552                 && !common_dimm->all_DIMMs_unbuffered) {
 553                 rd_en = 1;
 554                 twoT_en = 0;
 555         } else {
 556                 rd_en = 0;
 557                 twoT_en = popts->twoT_en;
 558         }
 559
 560         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 561
 562         dyn_pwr = popts->dynamic_power;
 563         dbw = popts->data_bus_width;
 564         /* 8-beat burst enable DDR-III case
 565          * we must clear it when use the on-the-fly mode,
 566          * must set it when use the 32-bits bus mode.
 567          */
 568         if (sdram_type == SDRAM_TYPE_DDR3) {
 569                 if (popts->burst_length == DDR_BL8)
 570                         eight_be = 1;
 571                 if (popts->burst_length == DDR_OTF)
 572                         eight_be = 0;
 573                 if (dbw == 0x1)
 574                         eight_be = 1;
 575         }
 576
 577         threeT_en = popts->threeT_en;
 578         ba_intlv_ctl = popts->ba_intlv_ctl;
 579         hse = popts->half_strength_driver_enable;
 580
 581         ddr->ddr_sdram_cfg = (0
 582                         | ((mem_en & 0x1) << 31)
 583                         | ((sren & 0x1) << 30)
 584                         | ((ecc_en & 0x1) << 29)
 585                         | ((rd_en & 0x1) << 28)
 586                         | ((sdram_type & 0x7) << 24)
 587                         | ((dyn_pwr & 0x1) << 21)
 588                         | ((dbw & 0x3) << 19)
 589                         | ((eight_be & 0x1) << 18)
 590                         | ((ncap & 0x1) << 17)
 591                         | ((threeT_en & 0x1) << 16)
 592                         | ((twoT_en & 0x1) << 15)
 593                         | ((ba_intlv_ctl & 0x7F) << 8)
 594                         | ((x32_en & 0x1) << 5)
 595                         | ((pchb8 & 0x1) << 4)
 596                         | ((hse & 0x1) << 3)
 597                         | ((mem_halt & 0x1) << 1)
 598                         | ((bi & 0x1) << 0)
 599                         );
 600         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 601 }
 602
 603 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 604 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 605                                const memctl_options_t *popts,
 606                                const unsigned int unq_mrs_en)
 607 {
 608         unsigned int frc_sr = 0;        /* Force self refresh */
 609         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 610         unsigned int dll_rst_dis;       /* DLL reset disable */
 611         unsigned int dqs_cfg;           /* DQS configuration */
 612         unsigned int odt_cfg;           /* ODT configuration */
 613         unsigned int num_pr;            /* Number of posted refreshes */
 614         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 615         unsigned int ap_en;             /* Address Parity Enable */
 616         unsigned int d_init;            /* DRAM data initialization */
 617         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 618         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 619         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 620
 621         dll_rst_dis = 1;        /* Make this configurable */
 622         dqs_cfg = popts->DQS_config;
 623         if (popts->cs_local_opts[0].odt_rd_cfg
 624             || popts->cs_local_opts[0].odt_wr_cfg) {
 625                 /* FIXME */
 626                 odt_cfg = 2;
 627         } else {
 628                 odt_cfg = 0;
 629         }
 630
 631         num_pr = 1;     /* Make this configurable */
 632
 633         /*
 634          * 8572 manual says
 635          *     {TIMING_CFG_1[PRETOACT]
 636          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 637          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 638          *      << DDR_SDRAM_INTERVAL[REFINT]
 639          */
 640 #if defined(CONFIG_FSL_DDR3)
 641         obc_cfg = popts->OTF_burst_chop_en;
 642 #else
 643         obc_cfg = 0;
 644 #endif
 645
 646         if (popts->registered_dimm_en) {
 647                 rcw_en = 1;
 648                 ap_en = popts->ap_en;
 649         } else {
 650                 rcw_en = 0;
 651                 ap_en = 0;
 652         }
 653
 654 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 655         /* Use the DDR controller to auto initialize memory. */
 656         d_init = popts->ECC_init_using_memctl;
 657         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 658         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 659 #else
 660         /* Memory will be initialized via DMA, or not at all. */
 661         d_init = 0;
 662 #endif
 663
 664 #if defined(CONFIG_FSL_DDR3)
 665         md_en = popts->mirrored_dimm;
 666 #endif
 667         qd_en = popts->quad_rank_present ? 1 : 0;
 668         ddr->ddr_sdram_cfg_2 = (0
 669                 | ((frc_sr & 0x1) << 31)
 670                 | ((sr_ie & 0x1) << 30)
 671                 | ((dll_rst_dis & 0x1) << 29)
 672                 | ((dqs_cfg & 0x3) << 26)
 673                 | ((odt_cfg & 0x3) << 21)
 674                 | ((num_pr & 0xf) << 12)
 675                 | (qd_en << 9)
 676                 | (unq_mrs_en << 8)
 677                 | ((obc_cfg & 0x1) << 6)
 678                 | ((ap_en & 0x1) << 5)
 679                 | ((d_init & 0x1) << 4)
 680                 | ((rcw_en & 0x1) << 2)
 681                 | ((md_en & 0x1) << 0)
 682                 );
 683         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 684 }
 685
 686 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 687 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 688                                 const memctl_options_t *popts,
 689                                 const unsigned int unq_mrs_en)
 690 {
 691         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 692         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 693
 694 #if defined(CONFIG_FSL_DDR3)
 695         int i;
 696         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 697         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 698         unsigned int asr = 0;   /* auto self-refresh disable */
 699         unsigned int cwl = compute_cas_write_latency() - 5;
 700         unsigned int pasr = 0;  /* partial array self refresh disable */
 701
 702         if (popts->rtt_override)
 703                 rtt_wr = popts->rtt_wr_override_value;
 704         else
 705                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 706         esdmode2 = (0
 707                 | ((rtt_wr & 0x3) << 9)
 708                 | ((srt & 0x1) << 7)
 709                 | ((asr & 0x1) << 6)
 710                 | ((cwl & 0x7) << 3)
 711                 | ((pasr & 0x7) << 0));
 712 #endif
 713         ddr->ddr_sdram_mode_2 = (0
 714                                  | ((esdmode2 & 0xFFFF) << 16)
 715                                  | ((esdmode3 & 0xFFFF) << 0)
 716                                  );
 717         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 718
 719 #ifdef CONFIG_FSL_DDR3
 720         if (unq_mrs_en) {       /* unique mode registers are supported */
 721                 for (i = 1; i < 4; i++) {
 722                         if (popts->rtt_override)
 723                                 rtt_wr = popts->rtt_wr_override_value;
 724                         else
 725                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 726
 727                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 728                         esdmode2 |= (rtt_wr & 0x3) << 9;
 729                         switch (i) {
 730                         case 1:
 731                                 ddr->ddr_sdram_mode_4 = (0
 732                                         | ((esdmode2 & 0xFFFF) << 16)
 733                                         | ((esdmode3 & 0xFFFF) << 0)
 734                                         );
 735                                 break;
 736                         case 2:
 737                                 ddr->ddr_sdram_mode_6 = (0
 738                                         | ((esdmode2 & 0xFFFF) << 16)
 739                                         | ((esdmode3 & 0xFFFF) << 0)
 740                                         );
 741                                 break;
 742                         case 3:
 743                                 ddr->ddr_sdram_mode_8 = (0
 744                                         | ((esdmode2 & 0xFFFF) << 16)
 745                                         | ((esdmode3 & 0xFFFF) << 0)
 746                                         );
 747                                 break;
 748                         }
 749                 }
 750                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 751                         ddr->ddr_sdram_mode_4);
 752                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 753                         ddr->ddr_sdram_mode_6);
 754                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 755                         ddr->ddr_sdram_mode_8);
 756         }
 757 #endif
 758 }
 759
 760 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 761 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 762                                const memctl_options_t *popts,
 763                                const common_timing_params_t *common_dimm)
 764 {
 765         unsigned int refint;    /* Refresh interval */
 766         unsigned int bstopre;   /* Precharge interval */
 767
 768         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 769
 770         bstopre = popts->bstopre;
 771
 772         /* refint field used 0x3FFF in earlier controllers */
 773         ddr->ddr_sdram_interval = (0
 774                                    | ((refint & 0xFFFF) << 16)
 775                                    | ((bstopre & 0x3FFF) << 0)
 776                                    );
 777         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 778 }
 779
 780 #if defined(CONFIG_FSL_DDR3)
 781 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 782 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 783                                const memctl_options_t *popts,
 784                                const common_timing_params_t *common_dimm,
 785                                unsigned int cas_latency,
 786                                unsigned int additive_latency,
 787                                const unsigned int unq_mrs_en)
 788 {
 789         unsigned short esdmode;         /* Extended SDRAM mode */
 790         unsigned short sdmode;          /* SDRAM mode */
 791
 792         /* Mode Register - MR1 */
 793         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 794         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 795         unsigned int rtt;
 796         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 797         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 798         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 799         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 800                                                        1=Disable (Test/Debug) */
 801
 802         /* Mode Register - MR0 */
 803         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 804         unsigned int wr;        /* Write Recovery */
 805         unsigned int dll_rst;   /* DLL Reset */
 806         unsigned int mode;      /* Normal=0 or Test=1 */
 807         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 808         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 809         unsigned int bt;
 810         unsigned int bl;        /* BL: Burst Length */
 811
 812         unsigned int wr_mclk;
 813
 814         const unsigned int mclk_ps = get_memory_clk_period_ps();
 815         int i;
 816
 817         if (popts->rtt_override)
 818                 rtt = popts->rtt_override_value;
 819         else
 820                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 821
 822         if (additive_latency == (cas_latency - 1))
 823                 al = 1;
 824         if (additive_latency == (cas_latency - 2))
 825                 al = 2;
 826
 827         if (popts->quad_rank_present)
 828                 dic = 1;        /* output driver impedance 240/7 ohm */
 829
 830         /*
 831          * The esdmode value will also be used for writing
 832          * MR1 during write leveling for DDR3, although the
 833          * bits specifically related to the write leveling
 834          * scheme will be handled automatically by the DDR
 835          * controller. so we set the wrlvl_en = 0 here.
 836          */
 837         esdmode = (0
 838                 | ((qoff & 0x1) << 12)
 839                 | ((tdqs_en & 0x1) << 11)
 840                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 841                 | ((wrlvl_en & 0x1) << 7)
 842                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 843                 | ((dic & 0x2) << 4)   /* DIC field is split */
 844                 | ((al & 0x3) << 3)
 845                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 846                 | ((dic & 0x1) << 1)   /* DIC field is split */
 847                 | ((dll_en & 0x1) << 0)
 848                 );
 849
 850         /*
 851          * DLL control for precharge PD
 852          * 0=slow exit DLL off (tXPDLL)
 853          * 1=fast exit DLL on (tXP)
 854          */
 855         dll_on = 1;
 856         wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
 857         if (wr_mclk >= 12)
 858                 wr = 6;
 859         else if (wr_mclk >= 9)
 860                 wr = 5;
 861         else
 862                 wr = wr_mclk - 4;
 863         dll_rst = 0;    /* dll no reset */
 864         mode = 0;       /* normal mode */
 865
 866         /* look up table to get the cas latency bits */
 867         if (cas_latency >= 5 && cas_latency <= 11) {
 868                 unsigned char cas_latency_table[7] = {
 869                         0x2,    /* 5 clocks */
 870                         0x4,    /* 6 clocks */
 871                         0x6,    /* 7 clocks */
 872                         0x8,    /* 8 clocks */
 873                         0xa,    /* 9 clocks */
 874                         0xc,    /* 10 clocks */
 875                         0xe     /* 11 clocks */
 876                 };
 877                 caslat = cas_latency_table[cas_latency - 5];
 878         }
 879         bt = 0; /* Nibble sequential */
 880
 881         switch (popts->burst_length) {
 882         case DDR_BL8:
 883                 bl = 0;
 884                 break;
 885         case DDR_OTF:
 886                 bl = 1;
 887                 break;
 888         case DDR_BC4:
 889                 bl = 2;
 890                 break;
 891         default:
 892                 printf("Error: invalid burst length of %u specified. "
 893                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 894                         popts->burst_length);
 895                 bl = 1;
 896                 break;
 897         }
 898
 899         sdmode = (0
 900                   | ((dll_on & 0x1) << 12)
 901                   | ((wr & 0x7) << 9)
 902                   | ((dll_rst & 0x1) << 8)
 903                   | ((mode & 0x1) << 7)
 904                   | (((caslat >> 1) & 0x7) << 4)
 905                   | ((bt & 0x1) << 3)
 906                   | ((bl & 0x3) << 0)
 907                   );
 908
 909         ddr->ddr_sdram_mode = (0
 910                                | ((esdmode & 0xFFFF) << 16)
 911                                | ((sdmode & 0xFFFF) << 0)
 912                                );
 913
 914         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 915
 916         if (unq_mrs_en) {       /* unique mode registers are supported */
 917                 for (i = 1; i < 4; i++) {
 918                         if (popts->rtt_override)
 919                                 rtt = popts->rtt_override_value;
 920                         else
 921                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
 922
 923                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
 924                         esdmode |= (0
 925                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 926                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 927                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 928                                 );
 929                         switch (i) {
 930                         case 1:
 931                                 ddr->ddr_sdram_mode_3 = (0
 932                                        | ((esdmode & 0xFFFF) << 16)
 933                                        | ((sdmode & 0xFFFF) << 0)
 934                                        );
 935                                 break;
 936                         case 2:
 937                                 ddr->ddr_sdram_mode_5 = (0
 938                                        | ((esdmode & 0xFFFF) << 16)
 939                                        | ((sdmode & 0xFFFF) << 0)
 940                                        );
 941                                 break;
 942                         case 3:
 943                                 ddr->ddr_sdram_mode_7 = (0
 944                                        | ((esdmode & 0xFFFF) << 16)
 945                                        | ((sdmode & 0xFFFF) << 0)
 946                                        );
 947                                 break;
 948                         }
 949                 }
 950                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
 951                         ddr->ddr_sdram_mode_3);
 952                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 953                         ddr->ddr_sdram_mode_5);
 954                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 955                         ddr->ddr_sdram_mode_5);
 956         }
 957 }
 958
 959 #else /* !CONFIG_FSL_DDR3 */
 960
 961 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 962 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 963                                const memctl_options_t *popts,
 964                                const common_timing_params_t *common_dimm,
 965                                unsigned int cas_latency,
 966                                unsigned int additive_latency,
 967                                const unsigned int unq_mrs_en)
 968 {
 969         unsigned short esdmode;         /* Extended SDRAM mode */
 970         unsigned short sdmode;          /* SDRAM mode */
 971
 972         /*
 973          * FIXME: This ought to be pre-calculated in a
 974          * technology-specific routine,
 975          * e.g. compute_DDR2_mode_register(), and then the
 976          * sdmode and esdmode passed in as part of common_dimm.
 977          */
 978
 979         /* Extended Mode Register */
 980         unsigned int mrs = 0;           /* Mode Register Set */
 981         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
 982         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
 983         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
 984         unsigned int ocd = 0;           /* 0x0=OCD not supported,
 985                                            0x7=OCD default state */
 986         unsigned int rtt;
 987         unsigned int al;                /* Posted CAS# additive latency (AL) */
 988         unsigned int ods = 0;           /* Output Drive Strength:
 989                                                 0 = Full strength (18ohm)
 990                                                 1 = Reduced strength (4ohm) */
 991         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 992                                                        1=Disable (Test/Debug) */
 993
 994         /* Mode Register (MR) */
 995         unsigned int mr;        /* Mode Register Definition */
 996         unsigned int pd;        /* Power-Down Mode */
 997         unsigned int wr;        /* Write Recovery */
 998         unsigned int dll_res;   /* DLL Reset */
 999         unsigned int mode;      /* Normal=0 or Test=1 */
1000         unsigned int caslat = 0;/* CAS# latency */
1001         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1002         unsigned int bt;
1003         unsigned int bl;        /* BL: Burst Length */
1004
1005 #if defined(CONFIG_FSL_DDR2)
1006         const unsigned int mclk_ps = get_memory_clk_period_ps();
1007 #endif
1008
1009         rtt = fsl_ddr_get_rtt();
1010
1011         al = additive_latency;
1012
1013         esdmode = (0
1014                 | ((mrs & 0x3) << 14)
1015                 | ((outputs & 0x1) << 12)
1016                 | ((rdqs_en & 0x1) << 11)
1017                 | ((dqs_en & 0x1) << 10)
1018                 | ((ocd & 0x7) << 7)
1019                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1020                 | ((al & 0x7) << 3)
1021                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1022                 | ((ods & 0x1) << 1)
1023                 | ((dll_en & 0x1) << 0)
1024                 );
1025
1026         mr = 0;          /* FIXME: CHECKME */
1027
1028         /*
1029          * 0 = Fast Exit (Normal)
1030          * 1 = Slow Exit (Low Power)
1031          */
1032         pd = 0;
1033
1034 #if defined(CONFIG_FSL_DDR1)
1035         wr = 0;       /* Historical */
1036 #elif defined(CONFIG_FSL_DDR2)
1037         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1038 #endif
1039         dll_res = 0;
1040         mode = 0;
1041
1042 #if defined(CONFIG_FSL_DDR1)
1043         if (1 <= cas_latency && cas_latency <= 4) {
1044                 unsigned char mode_caslat_table[4] = {
1045                         0x5,    /* 1.5 clocks */
1046                         0x2,    /* 2.0 clocks */
1047                         0x6,    /* 2.5 clocks */
1048                         0x3     /* 3.0 clocks */
1049                 };
1050                 caslat = mode_caslat_table[cas_latency - 1];
1051         } else {
1052                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1053         }
1054 #elif defined(CONFIG_FSL_DDR2)
1055         caslat = cas_latency;
1056 #endif
1057         bt = 0;
1058
1059         switch (popts->burst_length) {
1060         case DDR_BL4:
1061                 bl = 2;
1062                 break;
1063         case DDR_BL8:
1064                 bl = 3;
1065                 break;
1066         default:
1067                 printf("Error: invalid burst length of %u specified. "
1068                         " Defaulting to 4 beats.\n",
1069                         popts->burst_length);
1070                 bl = 2;
1071                 break;
1072         }
1073
1074         sdmode = (0
1075                   | ((mr & 0x3) << 14)
1076                   | ((pd & 0x1) << 12)
1077                   | ((wr & 0x7) << 9)
1078                   | ((dll_res & 0x1) << 8)
1079                   | ((mode & 0x1) << 7)
1080                   | ((caslat & 0x7) << 4)
1081                   | ((bt & 0x1) << 3)
1082                   | ((bl & 0x7) << 0)
1083                   );
1084
1085         ddr->ddr_sdram_mode = (0
1086                                | ((esdmode & 0xFFFF) << 16)
1087                                | ((sdmode & 0xFFFF) << 0)
1088                                );
1089         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1090 }
1091 #endif
1092
1093 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1094 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1095 {
1096         unsigned int init_value;        /* Initialization value */
1097
1098         init_value = 0xDEADBEEF;
1099         ddr->ddr_data_init = init_value;
1100 }
1101
1102 /*
1103  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1104  * The old controller on the 8540/60 doesn't have this register.
1105  * Hope it's OK to set it (to 0) anyway.
1106  */
1107 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1108                                          const memctl_options_t *popts)
1109 {
1110         unsigned int clk_adjust;        /* Clock adjust */
1111
1112         clk_adjust = popts->clk_adjust;
1113         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1114         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1115 }
1116
1117 /* DDR Initialization Address (DDR_INIT_ADDR) */
1118 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1119 {
1120         unsigned int init_addr = 0;     /* Initialization address */
1121
1122         ddr->ddr_init_addr = init_addr;
1123 }
1124
1125 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1126 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1127 {
1128         unsigned int uia = 0;   /* Use initialization address */
1129         unsigned int init_ext_addr = 0; /* Initialization address */
1130
1131         ddr->ddr_init_ext_addr = (0
1132                                   | ((uia & 0x1) << 31)
1133                                   | (init_ext_addr & 0xF)
1134                                   );
1135 }
1136
1137 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1138 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1139                                 const memctl_options_t *popts)
1140 {
1141         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1142         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1143         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1144         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1145         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1146
1147 #if defined(CONFIG_FSL_DDR3)
1148         if (popts->burst_length == DDR_BL8) {
1149                 /* We set BL/2 for fixed BL8 */
1150                 rrt = 0;        /* BL/2 clocks */
1151                 wwt = 0;        /* BL/2 clocks */
1152         } else {
1153                 /* We need to set BL/2 + 2 to BC4 and OTF */
1154                 rrt = 2;        /* BL/2 + 2 clocks */
1155                 wwt = 2;        /* BL/2 + 2 clocks */
1156         }
1157         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1158 #endif
1159         ddr->timing_cfg_4 = (0
1160                              | ((rwt & 0xf) << 28)
1161                              | ((wrt & 0xf) << 24)
1162                              | ((rrt & 0xf) << 20)
1163                              | ((wwt & 0xf) << 16)
1164                              | (dll_lock & 0x3)
1165                              );
1166         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1167 }
1168
1169 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1170 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1171 {
1172         unsigned int rodt_on = 0;       /* Read to ODT on */
1173         unsigned int rodt_off = 0;      /* Read to ODT off */
1174         unsigned int wodt_on = 0;       /* Write to ODT on */
1175         unsigned int wodt_off = 0;      /* Write to ODT off */
1176
1177 #if defined(CONFIG_FSL_DDR3)
1178         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1179         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1180         rodt_off = 4;   /*  4 clocks */
1181         wodt_on = 1;    /*  1 clocks */
1182         wodt_off = 4;   /*  4 clocks */
1183 #endif
1184
1185         ddr->timing_cfg_5 = (0
1186                              | ((rodt_on & 0x1f) << 24)
1187                              | ((rodt_off & 0x7) << 20)
1188                              | ((wodt_on & 0x1f) << 12)
1189                              | ((wodt_off & 0x7) << 8)
1190                              );
1191         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1192 }
1193
1194 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1195 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1196 {
1197         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1198         /* Normal Operation Full Calibration Time (tZQoper) */
1199         unsigned int zqoper = 0;
1200         /* Normal Operation Short Calibration Time (tZQCS) */
1201         unsigned int zqcs = 0;
1202
1203         if (zq_en) {
1204                 zqinit = 9;     /* 512 clocks */
1205                 zqoper = 8;     /* 256 clocks */
1206                 zqcs = 6;       /* 64 clocks */
1207         }
1208
1209         ddr->ddr_zq_cntl = (0
1210                             | ((zq_en & 0x1) << 31)
1211                             | ((zqinit & 0xF) << 24)
1212                             | ((zqoper & 0xF) << 16)
1213                             | ((zqcs & 0xF) << 8)
1214                             );
1215         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1216 }
1217
1218 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1219 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1220                                 const memctl_options_t *popts)
1221 {
1222         /*
1223          * First DQS pulse rising edge after margining mode
1224          * is programmed (tWL_MRD)
1225          */
1226         unsigned int wrlvl_mrd = 0;
1227         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1228         unsigned int wrlvl_odten = 0;
1229         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1230         unsigned int wrlvl_dqsen = 0;
1231         /* WRLVL_SMPL: Write leveling sample time */
1232         unsigned int wrlvl_smpl = 0;
1233         /* WRLVL_WLR: Write leveling repeition time */
1234         unsigned int wrlvl_wlr = 0;
1235         /* WRLVL_START: Write leveling start time */
1236         unsigned int wrlvl_start = 0;
1237
1238         /* suggest enable write leveling for DDR3 due to fly-by topology */
1239         if (wrlvl_en) {
1240                 /* tWL_MRD min = 40 nCK, we set it 64 */
1241                 wrlvl_mrd = 0x6;
1242                 /* tWL_ODTEN 128 */
1243                 wrlvl_odten = 0x7;
1244                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1245                 wrlvl_dqsen = 0x5;
1246                 /*
1247                  * Write leveling sample time at least need 6 clocks
1248                  * higher than tWLO to allow enough time for progagation
1249                  * delay and sampling the prime data bits.
1250                  */
1251                 wrlvl_smpl = 0xf;
1252                 /*
1253                  * Write leveling repetition time
1254                  * at least tWLO + 6 clocks clocks
1255                  * we set it 64
1256                  */
1257                 wrlvl_wlr = 0x6;
1258                 /*
1259                  * Write leveling start time
1260                  * The value use for the DQS_ADJUST for the first sample
1261                  * when write leveling is enabled. It probably needs to be
1262                  * overriden per platform.
1263                  */
1264                 wrlvl_start = 0x8;
1265                 /*
1266                  * Override the write leveling sample and start time
1267                  * according to specific board
1268                  */
1269                 if (popts->wrlvl_override) {
1270                         wrlvl_smpl = popts->wrlvl_sample;
1271                         wrlvl_start = popts->wrlvl_start;
1272                 }
1273         }
1274
1275         ddr->ddr_wrlvl_cntl = (0
1276                                | ((wrlvl_en & 0x1) << 31)
1277                                | ((wrlvl_mrd & 0x7) << 24)
1278                                | ((wrlvl_odten & 0x7) << 20)
1279                                | ((wrlvl_dqsen & 0x7) << 16)
1280                                | ((wrlvl_smpl & 0xf) << 12)
1281                                | ((wrlvl_wlr & 0x7) << 8)
1282                                | ((wrlvl_start & 0x1F) << 0)
1283                                );
1284         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1285 }
1286
1287 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1288 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1289 {
1290         /* Self Refresh Idle Threshold */
1291         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1292 }
1293
1294 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1295 {
1296         if (popts->addr_hash) {
1297                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1298                 puts("Addess hashing enabled.\n");
1299         }
1300 }
1301
1302 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1303 {
1304         ddr->ddr_cdr1 = popts->ddr_cdr1;
1305         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1306 }
1307
1308 unsigned int
1309 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1310 {
1311         unsigned int res = 0;
1312
1313         /*
1314          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1315          * not set at the same time.
1316          */
1317         if (ddr->ddr_sdram_cfg & 0x10000000
1318             && ddr->ddr_sdram_cfg & 0x00008000) {
1319                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1320                                 " should not be set at the same time.\n");
1321                 res++;
1322         }
1323
1324         return res;
1325 }
1326
1327 unsigned int
1328 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1329                                fsl_ddr_cfg_regs_t *ddr,
1330                                const common_timing_params_t *common_dimm,
1331                                const dimm_params_t *dimm_params,
1332                                unsigned int dbw_cap_adj,
1333                                unsigned int size_only)
1334 {
1335         unsigned int i;
1336         unsigned int cas_latency;
1337         unsigned int additive_latency;
1338         unsigned int sr_it;
1339         unsigned int zq_en;
1340         unsigned int wrlvl_en;
1341         unsigned int ip_rev = 0;
1342         unsigned int unq_mrs_en = 0;
1343         int cs_en = 1;
1344
1345         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1346
1347         if (common_dimm == NULL) {
1348                 printf("Error: subset DIMM params struct null pointer\n");
1349                 return 1;
1350         }
1351
1352         /*
1353          * Process overrides first.
1354          *
1355          * FIXME: somehow add dereated caslat to this
1356          */
1357         cas_latency = (popts->cas_latency_override)
1358                 ? popts->cas_latency_override_value
1359                 : common_dimm->lowest_common_SPD_caslat;
1360
1361         additive_latency = (popts->additive_latency_override)
1362                 ? popts->additive_latency_override_value
1363                 : common_dimm->additive_latency;
1364
1365         sr_it = (popts->auto_self_refresh_en)
1366                 ? popts->sr_it
1367                 : 0;
1368         /* ZQ calibration */
1369         zq_en = (popts->zq_en) ? 1 : 0;
1370         /* write leveling */
1371         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1372
1373         /* Chip Select Memory Bounds (CSn_BNDS) */
1374         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1375                 unsigned long long ea = 0, sa = 0;
1376                 unsigned int cs_per_dimm
1377                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1378                 unsigned int dimm_number
1379                         = i / cs_per_dimm;
1380                 unsigned long long rank_density
1381                         = dimm_params[dimm_number].rank_density;
1382
1383                 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1384                         ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1385                         ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1386                         /*
1387                          * Don't set up boundaries for unused CS
1388                          * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1389                          * cs2 for cs0_cs1_cs2_cs3
1390                          * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1391                          * But we need to set the ODT_RD_CFG and
1392                          * ODT_WR_CFG for CS1_CONFIG here.
1393                          */
1394                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1395                         continue;
1396                 }
1397                 if (dimm_params[dimm_number].n_ranks == 0) {
1398                         debug("Skipping setup of CS%u "
1399                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1400                         continue;
1401                 }
1402                 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1403                         /*
1404                          * This works superbank 2CS
1405                          * There are 2 or more memory controllers configured
1406                          * identically, memory is interleaved between them,
1407                          * and each controller uses rank interleaving within
1408                          * itself. Therefore the starting and ending address
1409                          * on each controller is twice the amount present on
1410                          * each controller. If any CS is not included in the
1411                          * interleaving, the memory on that CS is not accssible
1412                          * and the total memory size is reduced. The CS is also
1413                          * disabled.
1414                          */
1415                         unsigned long long ctlr_density = 0;
1416                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1417                         case FSL_DDR_CS0_CS1:
1418                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1419                                 ctlr_density = dimm_params[0].rank_density * 2;
1420                                 if (i > 1)
1421                                         cs_en = 0;
1422                                 break;
1423                         case FSL_DDR_CS2_CS3:
1424                                 ctlr_density = dimm_params[0].rank_density;
1425                                 if (i > 0)
1426                                         cs_en = 0;
1427                                 break;
1428                         case FSL_DDR_CS0_CS1_CS2_CS3:
1429                                 /*
1430                                  * The four CS interleaving should have been verified by
1431                                  * populate_memctl_options()
1432                                  */
1433                                 ctlr_density = dimm_params[0].rank_density * 4;
1434                                 break;
1435                         default:
1436                                 break;
1437                         }
1438                         ea = (CONFIG_NUM_DDR_CONTROLLERS *
1439                                 (ctlr_density >> dbw_cap_adj)) - 1;
1440                 }
1441                 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1442                         /*
1443                          * If memory interleaving between controllers is NOT
1444                          * enabled, the starting address for each memory
1445                          * controller is distinct.  However, because rank
1446                          * interleaving is enabled, the starting and ending
1447                          * addresses of the total memory on that memory
1448                          * controller needs to be programmed into its
1449                          * respective CS0_BNDS.
1450                          */
1451                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1452                         case FSL_DDR_CS0_CS1_CS2_CS3:
1453                                 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1454                                  * needs to be set.
1455                                  */
1456                                 sa = common_dimm->base_address;
1457                                 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1458                                 break;
1459                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1460                                 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1461                                  * and CS2_CNDS need to be set.
1462                                  */
1463                                 if ((i == 2) && (dimm_number == 0)) {
1464                                         sa = dimm_params[dimm_number].base_address +
1465                                               2 * (rank_density >> dbw_cap_adj);
1466                                         ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1467                                 } else {
1468                                         sa = dimm_params[dimm_number].base_address;
1469                                         ea = sa + (2 * (rank_density >>
1470                                                 dbw_cap_adj)) - 1;
1471                                 }
1472                                 break;
1473                         case FSL_DDR_CS0_CS1:
1474                                 /* CS0+CS1 interleaving, CS0_CNDS needs
1475                                  * to be set
1476                                  */
1477                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1478                                         sa = dimm_params[dimm_number].base_address;
1479                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1480                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1481                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1482                                 } else {
1483                                         sa = 0;
1484                                         ea = 0;
1485                                 }
1486                                 if (i == 0)
1487                                         ea += (rank_density >> dbw_cap_adj);
1488                                 break;
1489                         case FSL_DDR_CS2_CS3:
1490                                 /* CS2+CS3 interleaving*/
1491                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1492                                         sa = dimm_params[dimm_number].base_address;
1493                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1494                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1495                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1496                                 } else {
1497                                         sa = 0;
1498                                         ea = 0;
1499                                 }
1500                                 if (i == 2)
1501                                         ea += (rank_density >> dbw_cap_adj);
1502                                 break;
1503                         default:  /* No bank(chip-select) interleaving */
1504                                 break;
1505                         }
1506                 }
1507                 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1508                         /*
1509                          * Only the rank on CS0 of each memory controller may
1510                          * be used if memory controller interleaving is used
1511                          * without rank interleaving within each memory
1512                          * controller.  However, the ending address programmed
1513                          * into each CS0 must be the sum of the amount of
1514                          * memory in the two CS0 ranks.
1515                          */
1516                         if (i == 0) {
1517                                 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1518                         }
1519
1520                 }
1521                 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1522                         /*
1523                          * No rank interleaving and no memory controller
1524                          * interleaving.
1525                          */
1526                         sa = dimm_params[dimm_number].base_address;
1527                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1528                         if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1529                                 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1530                                 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1531                         } else {
1532                                 sa = 0;
1533                                 ea = 0;
1534                         }
1535                 }
1536
1537                 sa >>= 24;
1538                 ea >>= 24;
1539
1540                 ddr->cs[i].bnds = (0
1541                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
1542                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
1543                         );
1544
1545                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1546                 if (cs_en) {
1547                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1548                         set_csn_config_2(i, ddr);
1549                 } else
1550                         printf("CS%d is disabled.\n", i);
1551         }
1552
1553         /*
1554          * In the case we only need to compute the ddr sdram size, we only need
1555          * to set csn registers, so return from here.
1556          */
1557         if (size_only)
1558                 return 0;
1559
1560         set_ddr_eor(ddr, popts);
1561
1562 #if !defined(CONFIG_FSL_DDR1)
1563         set_timing_cfg_0(ddr, popts);
1564 #endif
1565
1566         set_timing_cfg_3(ddr, common_dimm, cas_latency);
1567         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1568         set_timing_cfg_2(ddr, popts, common_dimm,
1569                                 cas_latency, additive_latency);
1570
1571         set_ddr_cdr1(ddr, popts);
1572         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1573         ip_rev = fsl_ddr_get_version();
1574         if (ip_rev > 0x40400)
1575                 unq_mrs_en = 1;
1576
1577         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1578         set_ddr_sdram_mode(ddr, popts, common_dimm,
1579                                 cas_latency, additive_latency, unq_mrs_en);
1580         set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1581         set_ddr_sdram_interval(ddr, popts, common_dimm);
1582         set_ddr_data_init(ddr);
1583         set_ddr_sdram_clk_cntl(ddr, popts);
1584         set_ddr_init_addr(ddr);
1585         set_ddr_init_ext_addr(ddr);
1586         set_timing_cfg_4(ddr, popts);
1587         set_timing_cfg_5(ddr, cas_latency);
1588
1589         set_ddr_zq_cntl(ddr, zq_en);
1590         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1591
1592         set_ddr_sr_cntr(ddr, sr_it);
1593
1594         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1595
1596         return check_fsl_memctl_config_regs(ddr);
1597 }