2 * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
12 #include <asm/fsl_ddr_sdram.h>
17 * Use our own stack based buffer before relocation to allow accessing longer
18 * hwconfig strings that might be in the environment before we've relocated.
19 * This is pretty fragile on both the use of stack and if the buffer is big
20 * enough. However we will get a warning from getenv_f for the later.
22 #define HWCONFIG_BUFFER_SIZE 128
24 /* Board-specific functions defined in each board's ddr.c */
25 extern void fsl_ddr_board_options(memctl_options_t *popts,
27 unsigned int ctrl_num);
30 unsigned int odt_rd_cfg;
31 unsigned int odt_wr_cfg;
32 unsigned int odt_rtt_norm;
33 unsigned int odt_rtt_wr;
36 static const dynamic_odt_t single_Q[4] = {
39 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
45 FSL_DDR_ODT_NEVER, /* tied high */
51 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
57 FSL_DDR_ODT_NEVER, /* tied high */
63 static const dynamic_odt_t single_D[4] = {
80 static const dynamic_odt_t single_S[4] = {
92 static const dynamic_odt_t dual_DD[4] = {
95 FSL_DDR_ODT_SAME_DIMM,
100 FSL_DDR_ODT_OTHER_DIMM,
101 FSL_DDR_ODT_OTHER_DIMM,
107 FSL_DDR_ODT_SAME_DIMM,
112 FSL_DDR_ODT_OTHER_DIMM,
113 FSL_DDR_ODT_OTHER_DIMM,
119 static const dynamic_odt_t dual_DS[4] = {
122 FSL_DDR_ODT_SAME_DIMM,
127 FSL_DDR_ODT_OTHER_DIMM,
128 FSL_DDR_ODT_OTHER_DIMM,
133 FSL_DDR_ODT_OTHER_DIMM,
140 static const dynamic_odt_t dual_SD[4] = {
142 FSL_DDR_ODT_OTHER_DIMM,
150 FSL_DDR_ODT_SAME_DIMM,
155 FSL_DDR_ODT_OTHER_DIMM,
156 FSL_DDR_ODT_OTHER_DIMM,
162 static const dynamic_odt_t dual_SS[4] = {
164 FSL_DDR_ODT_OTHER_DIMM,
171 FSL_DDR_ODT_OTHER_DIMM,
179 static const dynamic_odt_t dual_D0[4] = {
182 FSL_DDR_ODT_SAME_DIMM,
196 static const dynamic_odt_t dual_0D[4] = {
201 FSL_DDR_ODT_SAME_DIMM,
213 static const dynamic_odt_t dual_S0[4] = {
226 static const dynamic_odt_t dual_0S[4] = {
239 static const dynamic_odt_t odt_unknown[4] = {
266 unsigned int populate_memctl_options(int all_DIMMs_registered,
267 memctl_options_t *popts,
268 dimm_params_t *pdimm,
269 unsigned int ctrl_num)
272 char buffer[HWCONFIG_BUFFER_SIZE];
274 const dynamic_odt_t *pdodt = odt_unknown;
277 * Extract hwconfig from environment since we have not properly setup
278 * the environment but need it for ddr config params
280 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
283 /* Chip select options. */
284 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
285 switch (pdimm[0].n_ranks) {
296 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
297 switch (pdimm[0].n_ranks) {
299 switch (pdimm[1].n_ranks) {
312 switch (pdimm[1].n_ranks) {
325 switch (pdimm[1].n_ranks) {
337 /* Pick chip-select local options. */
338 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
339 #if defined(CONFIG_FSL_DDR3)
340 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
341 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
342 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
343 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
345 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
346 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
348 popts->cs_local_opts[i].auto_precharge = 0;
351 /* Pick interleaving mode. */
354 * 0 = no interleaving
355 * 1 = interleaving between 2 controllers
357 popts->memctl_interleaving = 0;
363 * 3 = superbank (only if CS interleaving is enabled)
365 popts->memctl_interleaving_mode = 0;
368 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
369 * 1: page: bit to the left of the column bits selects the memctl
370 * 2: bank: bit to the left of the bank bits selects the memctl
371 * 3: superbank: bit to the left of the chip select selects the memctl
373 * NOTE: ba_intlv (rank interleaving) is independent of memory
374 * controller interleaving; it is only within a memory controller.
375 * Must use superbank interleaving if rank interleaving is used and
376 * memory controller interleaving is enabled.
383 * 0x60 = CS0,CS1 + CS2,CS3
384 * 0x04 = CS0,CS1,CS2,CS3
386 popts->ba_intlv_ctl = 0;
388 /* Memory Organization Parameters */
389 popts->registered_dimm_en = all_DIMMs_registered;
391 /* Operational Mode Paramters */
394 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
395 #ifdef CONFIG_DDR_ECC
396 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
397 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
402 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
409 #if defined(CONFIG_FSL_DDR1)
410 popts->DQS_config = 0;
411 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
412 popts->DQS_config = 1;
415 /* Choose self-refresh during sleep. */
416 popts->self_refresh_in_sleep = 1;
418 /* Choose dynamic power management mode. */
419 popts->dynamic_power = 0;
421 /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
422 popts->data_bus_width = 0;
424 /* Choose burst length. */
425 #if defined(CONFIG_FSL_DDR3)
426 #if defined(CONFIG_E500MC)
427 popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
428 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
430 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
431 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
434 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
437 /* Choose ddr controller address mirror mode */
438 #if defined(CONFIG_FSL_DDR3)
439 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
442 /* Global Timing Parameters. */
443 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
445 /* Pick a caslat override. */
446 popts->cas_latency_override = 0;
447 popts->cas_latency_override_value = 3;
448 if (popts->cas_latency_override) {
449 debug("using caslat override value = %u\n",
450 popts->cas_latency_override_value);
453 /* Decide whether to use the computed derated latency */
454 popts->use_derated_caslat = 0;
456 /* Choose an additive latency. */
457 popts->additive_latency_override = 0;
458 popts->additive_latency_override_value = 3;
459 if (popts->additive_latency_override) {
460 debug("using additive latency override value = %u\n",
461 popts->additive_latency_override_value);
467 * Factors to consider for 2T_EN:
468 * - number of DIMMs installed
469 * - number of components, number of active ranks
470 * - how much time you want to spend playing around
473 popts->threeT_en = 0;
475 /* for RDIMM, address parity enable */
479 * BSTTOPRE precharge interval
481 * Set this to 0 for global auto precharge
483 * FIXME: Should this be configured in picoseconds?
484 * Why it should be in ps: better understanding of this
485 * relative to actual DRAM timing parameters such as tRAS.
486 * e.g. tRAS(min) = 40 ns
488 popts->bstopre = 0x100;
490 /* Minimum CKE pulse width -- tCKE(MIN) */
491 popts->tCKE_clock_pulse_width_ps
492 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
495 * Window for four activates -- tFAW
497 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
498 * FIXME: varies depending upon number of column addresses or data
499 * FIXME: width, was considering looking at pdimm->primary_sdram_width
501 #if defined(CONFIG_FSL_DDR1)
502 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
504 #elif defined(CONFIG_FSL_DDR2)
506 * x4/x8; some datasheets have 35000
507 * x16 wide columns only? Use 50000?
509 popts->tFAW_window_four_activates_ps = 37500;
511 #elif defined(CONFIG_FSL_DDR3)
512 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
516 #if defined(CONFIG_FSL_DDR3)
518 * due to ddr3 dimm is fly-by topology
519 * we suggest to enable write leveling to
520 * meet the tQDSS under different loading.
524 popts->wrlvl_override = 0;
528 * Check interleaving configuration from environment.
529 * Please refer to doc/README.fsl-ddr for the detail.
531 * If memory controller interleaving is enabled, then the data
532 * bus widths must be programmed identically for all memory controllers.
534 * XXX: Attempt to set all controllers to the same chip select
535 * interleaving mode. It will do a best effort to get the
536 * requested ranks interleaved together such that the result
537 * should be a subset of the requested configuration.
539 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
540 if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
541 if (pdimm[0].n_ranks == 0) {
542 printf("There is no rank on CS0 for controller %d. Because only"
543 " rank on CS0 and ranks chip-select interleaved with CS0"
544 " are controller interleaved, force non memory "
545 "controller interleaving\n", ctrl_num);
546 popts->memctl_interleaving = 0;
548 popts->memctl_interleaving = 1;
550 * test null first. if CONFIG_HWCONFIG is not defined
551 * hwconfig_arg_cmp returns non-zero
553 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
555 popts->memctl_interleaving = 0;
556 debug("memory controller interleaving disabled.\n");
557 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
560 popts->memctl_interleaving_mode =
561 FSL_DDR_CACHE_LINE_INTERLEAVING;
562 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
564 popts->memctl_interleaving_mode =
565 FSL_DDR_PAGE_INTERLEAVING;
566 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
568 popts->memctl_interleaving_mode =
569 FSL_DDR_BANK_INTERLEAVING;
570 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
572 popts->memctl_interleaving_mode =
573 FSL_DDR_SUPERBANK_INTERLEAVING;
575 popts->memctl_interleaving = 0;
576 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
581 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
582 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
583 /* test null first. if CONFIG_HWCONFIG is not defined,
584 * hwconfig_subarg_cmp_f returns non-zero */
585 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
587 debug("bank interleaving disabled.\n");
588 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
590 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
591 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
593 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
594 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
595 "cs0_cs1_and_cs2_cs3", buf))
596 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
597 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
598 "cs0_cs1_cs2_cs3", buf))
599 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
601 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
602 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
603 case FSL_DDR_CS0_CS1_CS2_CS3:
604 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
605 if (pdimm[0].n_ranks < 4) {
606 popts->ba_intlv_ctl = 0;
607 printf("Not enough bank(chip-select) for "
608 "CS0+CS1+CS2+CS3 on controller %d, "
609 "force non-interleaving!\n", ctrl_num);
611 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
612 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
613 popts->ba_intlv_ctl = 0;
614 printf("Not enough bank(chip-select) for "
615 "CS0+CS1+CS2+CS3 on controller %d, "
616 "force non-interleaving!\n", ctrl_num);
618 if (pdimm[0].capacity != pdimm[1].capacity) {
619 popts->ba_intlv_ctl = 0;
620 printf("Not identical DIMM size for "
621 "CS0+CS1+CS2+CS3 on controller %d, "
622 "force non-interleaving!\n", ctrl_num);
626 case FSL_DDR_CS0_CS1:
627 if (pdimm[0].n_ranks < 2) {
628 popts->ba_intlv_ctl = 0;
629 printf("Not enough bank(chip-select) for "
630 "CS0+CS1 on controller %d, "
631 "force non-interleaving!\n", ctrl_num);
634 case FSL_DDR_CS2_CS3:
635 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
636 if (pdimm[0].n_ranks < 4) {
637 popts->ba_intlv_ctl = 0;
638 printf("Not enough bank(chip-select) for CS2+CS3 "
639 "on controller %d, force non-interleaving!\n", ctrl_num);
641 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
642 if (pdimm[1].n_ranks < 2) {
643 popts->ba_intlv_ctl = 0;
644 printf("Not enough bank(chip-select) for CS2+CS3 "
645 "on controller %d, force non-interleaving!\n", ctrl_num);
649 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
650 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
651 if (pdimm[0].n_ranks < 4) {
652 popts->ba_intlv_ctl = 0;
653 printf("Not enough bank(CS) for CS0+CS1 and "
654 "CS2+CS3 on controller %d, "
655 "force non-interleaving!\n", ctrl_num);
657 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
658 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
659 popts->ba_intlv_ctl = 0;
660 printf("Not enough bank(CS) for CS0+CS1 and "
661 "CS2+CS3 on controller %d, "
662 "force non-interleaving!\n", ctrl_num);
667 popts->ba_intlv_ctl = 0;
672 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
673 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
674 popts->addr_hash = 0;
675 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
677 popts->addr_hash = 1;
680 if (pdimm[0].n_ranks == 4)
681 popts->quad_rank_present = 1;
683 fsl_ddr_board_options(popts, pdimm, ctrl_num);
688 void check_interleaving_options(fsl_ddr_info_t *pinfo)
690 int i, j, check_n_ranks, intlv_fixed = 0;
691 unsigned long long check_rank_density;
693 * Check if all controllers are configured for memory
694 * controller interleaving. Identical dimms are recommended. At least
695 * the size should be checked.
698 check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
699 check_rank_density = pinfo->dimm_params[0][0].rank_density;
700 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
701 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
702 (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
703 (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
707 if (j != CONFIG_NUM_DDR_CONTROLLERS) {
708 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
709 if (pinfo->memctl_opts[i].memctl_interleaving) {
710 pinfo->memctl_opts[i].memctl_interleaving = 0;
714 printf("Not all DIMMs are identical in size. "
715 "Memory controller interleaving disabled.\n");
719 int fsl_use_spd(void)
723 #ifdef CONFIG_DDR_SPD
724 char buffer[HWCONFIG_BUFFER_SIZE];
728 * Extract hwconfig from environment since we have not properly setup
729 * the environment but need it for ddr config params
731 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
734 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
735 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
736 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
738 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",