2 * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
12 #include <asm/fsl_ddr_sdram.h>
17 * Use our own stack based buffer before relocation to allow accessing longer
18 * hwconfig strings that might be in the environment before we've relocated.
19 * This is pretty fragile on both the use of stack and if the buffer is big
20 * enough. However we will get a warning from getenv_f for the later.
23 /* Board-specific functions defined in each board's ddr.c */
24 extern void fsl_ddr_board_options(memctl_options_t *popts,
26 unsigned int ctrl_num);
29 unsigned int odt_rd_cfg;
30 unsigned int odt_wr_cfg;
31 unsigned int odt_rtt_norm;
32 unsigned int odt_rtt_wr;
35 #ifdef CONFIG_FSL_DDR3
36 static const struct dynamic_odt single_Q[4] = {
39 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
45 FSL_DDR_ODT_NEVER, /* tied high */
51 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
57 FSL_DDR_ODT_NEVER, /* tied high */
63 static const struct dynamic_odt single_D[4] = {
80 static const struct dynamic_odt single_S[4] = {
92 static const struct dynamic_odt dual_DD[4] = {
95 FSL_DDR_ODT_SAME_DIMM,
100 FSL_DDR_ODT_OTHER_DIMM,
101 FSL_DDR_ODT_OTHER_DIMM,
107 FSL_DDR_ODT_SAME_DIMM,
112 FSL_DDR_ODT_OTHER_DIMM,
113 FSL_DDR_ODT_OTHER_DIMM,
119 static const struct dynamic_odt dual_DS[4] = {
122 FSL_DDR_ODT_SAME_DIMM,
127 FSL_DDR_ODT_OTHER_DIMM,
128 FSL_DDR_ODT_OTHER_DIMM,
133 FSL_DDR_ODT_OTHER_DIMM,
140 static const struct dynamic_odt dual_SD[4] = {
142 FSL_DDR_ODT_OTHER_DIMM,
150 FSL_DDR_ODT_SAME_DIMM,
155 FSL_DDR_ODT_OTHER_DIMM,
156 FSL_DDR_ODT_OTHER_DIMM,
162 static const struct dynamic_odt dual_SS[4] = {
164 FSL_DDR_ODT_OTHER_DIMM,
171 FSL_DDR_ODT_OTHER_DIMM,
179 static const struct dynamic_odt dual_D0[4] = {
182 FSL_DDR_ODT_SAME_DIMM,
196 static const struct dynamic_odt dual_0D[4] = {
201 FSL_DDR_ODT_SAME_DIMM,
213 static const struct dynamic_odt dual_S0[4] = {
226 static const struct dynamic_odt dual_0S[4] = {
239 static const struct dynamic_odt odt_unknown[4] = {
265 #else /* CONFIG_FSL_DDR3 */
266 static const struct dynamic_odt single_Q[4] = {
273 static const struct dynamic_odt single_D[4] = {
290 static const struct dynamic_odt single_S[4] = {
302 static const struct dynamic_odt dual_DD[4] = {
304 FSL_DDR_ODT_OTHER_DIMM,
305 FSL_DDR_ODT_OTHER_DIMM,
316 FSL_DDR_ODT_OTHER_DIMM,
317 FSL_DDR_ODT_OTHER_DIMM,
329 static const struct dynamic_odt dual_DS[4] = {
331 FSL_DDR_ODT_OTHER_DIMM,
332 FSL_DDR_ODT_OTHER_DIMM,
343 FSL_DDR_ODT_OTHER_DIMM,
344 FSL_DDR_ODT_OTHER_DIMM,
351 static const struct dynamic_odt dual_SD[4] = {
353 FSL_DDR_ODT_OTHER_DIMM,
354 FSL_DDR_ODT_OTHER_DIMM,
360 FSL_DDR_ODT_OTHER_DIMM,
361 FSL_DDR_ODT_OTHER_DIMM,
373 static const struct dynamic_odt dual_SS[4] = {
375 FSL_DDR_ODT_OTHER_DIMM,
376 FSL_DDR_ODT_OTHER_DIMM,
382 FSL_DDR_ODT_OTHER_DIMM,
383 FSL_DDR_ODT_OTHER_DIMM,
390 static const struct dynamic_odt dual_D0[4] = {
407 static const struct dynamic_odt dual_0D[4] = {
424 static const struct dynamic_odt dual_S0[4] = {
437 static const struct dynamic_odt dual_0S[4] = {
450 static const struct dynamic_odt odt_unknown[4] = {
477 unsigned int populate_memctl_options(int all_DIMMs_registered,
478 memctl_options_t *popts,
479 dimm_params_t *pdimm,
480 unsigned int ctrl_num)
483 char buffer[HWCONFIG_BUFFER_SIZE];
485 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
486 const struct dynamic_odt *pdodt = odt_unknown;
491 * Extract hwconfig from environment since we have not properly setup
492 * the environment but need it for ddr config params
494 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
497 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
498 /* Chip select options. */
499 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
500 switch (pdimm[0].n_ranks) {
511 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
512 switch (pdimm[0].n_ranks) {
514 switch (pdimm[1].n_ranks) {
527 switch (pdimm[1].n_ranks) {
540 switch (pdimm[1].n_ranks) {
553 /* Pick chip-select local options. */
554 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
555 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
556 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
557 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
558 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
559 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
561 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
562 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
564 popts->cs_local_opts[i].auto_precharge = 0;
567 /* Pick interleaving mode. */
570 * 0 = no interleaving
571 * 1 = interleaving between 2 controllers
573 popts->memctl_interleaving = 0;
579 * 3 = superbank (only if CS interleaving is enabled)
581 popts->memctl_interleaving_mode = 0;
584 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
585 * 1: page: bit to the left of the column bits selects the memctl
586 * 2: bank: bit to the left of the bank bits selects the memctl
587 * 3: superbank: bit to the left of the chip select selects the memctl
589 * NOTE: ba_intlv (rank interleaving) is independent of memory
590 * controller interleaving; it is only within a memory controller.
591 * Must use superbank interleaving if rank interleaving is used and
592 * memory controller interleaving is enabled.
599 * 0x60 = CS0,CS1 + CS2,CS3
600 * 0x04 = CS0,CS1,CS2,CS3
602 popts->ba_intlv_ctl = 0;
604 /* Memory Organization Parameters */
605 popts->registered_dimm_en = all_DIMMs_registered;
607 /* Operational Mode Paramters */
610 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
611 #ifdef CONFIG_DDR_ECC
612 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
613 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
618 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
625 #if defined(CONFIG_FSL_DDR1)
626 popts->DQS_config = 0;
627 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
628 popts->DQS_config = 1;
631 /* Choose self-refresh during sleep. */
632 popts->self_refresh_in_sleep = 1;
634 /* Choose dynamic power management mode. */
635 popts->dynamic_power = 0;
638 * check first dimm for primary sdram width
639 * presuming all dimms are similar
640 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
642 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
643 if (pdimm[0].n_ranks != 0) {
644 if ((pdimm[0].data_width >= 64) && \
645 (pdimm[0].data_width <= 72))
646 popts->data_bus_width = 0;
647 else if ((pdimm[0].data_width >= 32) || \
648 (pdimm[0].data_width <= 40))
649 popts->data_bus_width = 1;
651 panic("Error: data width %u is invalid!\n",
652 pdimm[0].data_width);
656 if (pdimm[0].n_ranks != 0) {
657 if (pdimm[0].primary_sdram_width == 64)
658 popts->data_bus_width = 0;
659 else if (pdimm[0].primary_sdram_width == 32)
660 popts->data_bus_width = 1;
661 else if (pdimm[0].primary_sdram_width == 16)
662 popts->data_bus_width = 2;
664 panic("Error: primary sdram width %u is invalid!\n",
665 pdimm[0].primary_sdram_width);
670 /* Choose burst length. */
671 #if defined(CONFIG_FSL_DDR3)
672 #if defined(CONFIG_E500MC)
673 popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
674 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
676 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
677 /* 32-bit or 16-bit bus */
678 popts->OTF_burst_chop_en = 0;
679 popts->burst_length = DDR_BL8;
681 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
682 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
686 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
689 /* Choose ddr controller address mirror mode */
690 #if defined(CONFIG_FSL_DDR3)
691 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
694 /* Global Timing Parameters. */
695 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
697 /* Pick a caslat override. */
698 popts->cas_latency_override = 0;
699 popts->cas_latency_override_value = 3;
700 if (popts->cas_latency_override) {
701 debug("using caslat override value = %u\n",
702 popts->cas_latency_override_value);
705 /* Decide whether to use the computed derated latency */
706 popts->use_derated_caslat = 0;
708 /* Choose an additive latency. */
709 popts->additive_latency_override = 0;
710 popts->additive_latency_override_value = 3;
711 if (popts->additive_latency_override) {
712 debug("using additive latency override value = %u\n",
713 popts->additive_latency_override_value);
719 * Factors to consider for 2T_EN:
720 * - number of DIMMs installed
721 * - number of components, number of active ranks
722 * - how much time you want to spend playing around
725 popts->threeT_en = 0;
727 /* for RDIMM, address parity enable */
731 * BSTTOPRE precharge interval
733 * Set this to 0 for global auto precharge
735 * FIXME: Should this be configured in picoseconds?
736 * Why it should be in ps: better understanding of this
737 * relative to actual DRAM timing parameters such as tRAS.
738 * e.g. tRAS(min) = 40 ns
740 popts->bstopre = 0x100;
742 /* Minimum CKE pulse width -- tCKE(MIN) */
743 popts->tCKE_clock_pulse_width_ps
744 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
747 * Window for four activates -- tFAW
749 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
750 * FIXME: varies depending upon number of column addresses or data
751 * FIXME: width, was considering looking at pdimm->primary_sdram_width
753 #if defined(CONFIG_FSL_DDR1)
754 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
756 #elif defined(CONFIG_FSL_DDR2)
758 * x4/x8; some datasheets have 35000
759 * x16 wide columns only? Use 50000?
761 popts->tFAW_window_four_activates_ps = 37500;
763 #elif defined(CONFIG_FSL_DDR3)
764 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
768 #if defined(CONFIG_FSL_DDR3)
770 * due to ddr3 dimm is fly-by topology
771 * we suggest to enable write leveling to
772 * meet the tQDSS under different loading.
776 popts->wrlvl_override = 0;
780 * Check interleaving configuration from environment.
781 * Please refer to doc/README.fsl-ddr for the detail.
783 * If memory controller interleaving is enabled, then the data
784 * bus widths must be programmed identically for all memory controllers.
786 * XXX: Attempt to set all controllers to the same chip select
787 * interleaving mode. It will do a best effort to get the
788 * requested ranks interleaved together such that the result
789 * should be a subset of the requested configuration.
791 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
792 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
795 if (pdimm[0].n_ranks == 0) {
796 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
797 popts->memctl_interleaving = 0;
800 popts->memctl_interleaving = 1;
802 * test null first. if CONFIG_HWCONFIG is not defined
803 * hwconfig_arg_cmp returns non-zero
805 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
807 popts->memctl_interleaving = 0;
808 debug("memory controller interleaving disabled.\n");
809 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
812 popts->memctl_interleaving_mode =
813 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
814 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
815 popts->memctl_interleaving =
816 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
818 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
821 popts->memctl_interleaving_mode =
822 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
823 0 : FSL_DDR_PAGE_INTERLEAVING;
824 popts->memctl_interleaving =
825 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
827 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
830 popts->memctl_interleaving_mode =
831 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
832 0 : FSL_DDR_BANK_INTERLEAVING;
833 popts->memctl_interleaving =
834 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
836 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
839 popts->memctl_interleaving_mode =
840 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
841 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
842 popts->memctl_interleaving =
843 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
845 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
846 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
849 popts->memctl_interleaving_mode =
850 FSL_DDR_3WAY_1KB_INTERLEAVING;
851 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
854 popts->memctl_interleaving_mode =
855 FSL_DDR_3WAY_4KB_INTERLEAVING;
856 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
859 popts->memctl_interleaving_mode =
860 FSL_DDR_3WAY_8KB_INTERLEAVING;
861 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
862 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
865 popts->memctl_interleaving_mode =
866 FSL_DDR_4WAY_1KB_INTERLEAVING;
867 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
870 popts->memctl_interleaving_mode =
871 FSL_DDR_4WAY_4KB_INTERLEAVING;
872 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
875 popts->memctl_interleaving_mode =
876 FSL_DDR_4WAY_8KB_INTERLEAVING;
879 popts->memctl_interleaving = 0;
880 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
884 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
885 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
886 /* test null first. if CONFIG_HWCONFIG is not defined,
887 * hwconfig_subarg_cmp_f returns non-zero */
888 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
890 debug("bank interleaving disabled.\n");
891 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
893 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
894 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
896 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
897 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
898 "cs0_cs1_and_cs2_cs3", buf))
899 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
900 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
901 "cs0_cs1_cs2_cs3", buf))
902 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
904 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
905 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
906 case FSL_DDR_CS0_CS1_CS2_CS3:
907 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
908 if (pdimm[0].n_ranks < 4) {
909 popts->ba_intlv_ctl = 0;
910 printf("Not enough bank(chip-select) for "
911 "CS0+CS1+CS2+CS3 on controller %d, "
912 "interleaving disabled!\n", ctrl_num);
914 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
915 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
916 popts->ba_intlv_ctl = 0;
917 printf("Not enough bank(chip-select) for "
918 "CS0+CS1+CS2+CS3 on controller %d, "
919 "interleaving disabled!\n", ctrl_num);
921 if (pdimm[0].capacity != pdimm[1].capacity) {
922 popts->ba_intlv_ctl = 0;
923 printf("Not identical DIMM size for "
924 "CS0+CS1+CS2+CS3 on controller %d, "
925 "interleaving disabled!\n", ctrl_num);
929 case FSL_DDR_CS0_CS1:
930 if (pdimm[0].n_ranks < 2) {
931 popts->ba_intlv_ctl = 0;
932 printf("Not enough bank(chip-select) for "
933 "CS0+CS1 on controller %d, "
934 "interleaving disabled!\n", ctrl_num);
937 case FSL_DDR_CS2_CS3:
938 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
939 if (pdimm[0].n_ranks < 4) {
940 popts->ba_intlv_ctl = 0;
941 printf("Not enough bank(chip-select) for CS2+CS3 "
942 "on controller %d, interleaving disabled!\n", ctrl_num);
944 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
945 if (pdimm[1].n_ranks < 2) {
946 popts->ba_intlv_ctl = 0;
947 printf("Not enough bank(chip-select) for CS2+CS3 "
948 "on controller %d, interleaving disabled!\n", ctrl_num);
952 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
953 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
954 if (pdimm[0].n_ranks < 4) {
955 popts->ba_intlv_ctl = 0;
956 printf("Not enough bank(CS) for CS0+CS1 and "
957 "CS2+CS3 on controller %d, "
958 "interleaving disabled!\n", ctrl_num);
960 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
961 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
962 popts->ba_intlv_ctl = 0;
963 printf("Not enough bank(CS) for CS0+CS1 and "
964 "CS2+CS3 on controller %d, "
965 "interleaving disabled!\n", ctrl_num);
970 popts->ba_intlv_ctl = 0;
975 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
976 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
977 popts->addr_hash = 0;
978 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
980 popts->addr_hash = 1;
983 if (pdimm[0].n_ranks == 4)
984 popts->quad_rank_present = 1;
986 ddr_freq = get_ddr_freq(0) / 1000000;
987 if (popts->registered_dimm_en) {
988 popts->rcw_override = 1;
989 popts->rcw_1 = 0x000a5a00;
991 popts->rcw_2 = 0x00000000;
992 else if (ddr_freq <= 1066)
993 popts->rcw_2 = 0x00100000;
994 else if (ddr_freq <= 1333)
995 popts->rcw_2 = 0x00200000;
997 popts->rcw_2 = 0x00300000;
1000 fsl_ddr_board_options(popts, pdimm, ctrl_num);
1005 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1007 int i, j, k, check_n_ranks, intlv_invalid = 0;
1008 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1009 unsigned long long check_rank_density;
1010 struct dimm_params_s *dimm;
1012 * Check if all controllers are configured for memory
1013 * controller interleaving. Identical dimms are recommended. At least
1014 * the size, row and col address should be checked.
1017 check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
1018 check_rank_density = pinfo->dimm_params[0][0].rank_density;
1019 check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr;
1020 check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr;
1021 check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode;
1022 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1023 dimm = &pinfo->dimm_params[i][0];
1024 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1026 } else if (((check_rank_density != dimm->rank_density) ||
1027 (check_n_ranks != dimm->n_ranks) ||
1028 (check_n_row_addr != dimm->n_row_addr) ||
1029 (check_n_col_addr != dimm->n_col_addr) ||
1031 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1039 if (intlv_invalid) {
1040 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1041 pinfo->memctl_opts[i].memctl_interleaving = 0;
1042 printf("Not all DIMMs are identical. "
1043 "Memory controller interleaving disabled.\n");
1045 switch (check_intlv) {
1046 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1047 case FSL_DDR_PAGE_INTERLEAVING:
1048 case FSL_DDR_BANK_INTERLEAVING:
1049 case FSL_DDR_SUPERBANK_INTERLEAVING:
1050 if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1053 k = CONFIG_NUM_DDR_CONTROLLERS;
1055 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1056 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1057 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1058 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1059 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1060 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1062 k = CONFIG_NUM_DDR_CONTROLLERS;
1065 debug("%d of %d controllers are interleaving.\n", j, k);
1067 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1068 pinfo->memctl_opts[i].memctl_interleaving = 0;
1069 printf("Not all controllers have compatible "
1070 "interleaving mode. All disabled.\n");
1073 debug("Checking interleaving options completed\n");
1076 int fsl_use_spd(void)
1080 #ifdef CONFIG_DDR_SPD
1081 char buffer[HWCONFIG_BUFFER_SIZE];
1085 * Extract hwconfig from environment since we have not properly setup
1086 * the environment but need it for ddr config params
1088 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1091 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1092 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1093 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1095 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",