2 * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
12 #include <asm/fsl_ddr_sdram.h>
17 * Use our own stack based buffer before relocation to allow accessing longer
18 * hwconfig strings that might be in the environment before we've relocated.
19 * This is pretty fragile on both the use of stack and if the buffer is big
20 * enough. However we will get a warning from getenv_f for the later.
23 /* Board-specific functions defined in each board's ddr.c */
24 extern void fsl_ddr_board_options(memctl_options_t *popts,
26 unsigned int ctrl_num);
29 unsigned int odt_rd_cfg;
30 unsigned int odt_wr_cfg;
31 unsigned int odt_rtt_norm;
32 unsigned int odt_rtt_wr;
35 #ifdef CONFIG_FSL_DDR3
36 static const struct dynamic_odt single_Q[4] = {
39 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
45 FSL_DDR_ODT_NEVER, /* tied high */
51 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
57 FSL_DDR_ODT_NEVER, /* tied high */
63 static const struct dynamic_odt single_D[4] = {
80 static const struct dynamic_odt single_S[4] = {
92 static const struct dynamic_odt dual_DD[4] = {
95 FSL_DDR_ODT_SAME_DIMM,
100 FSL_DDR_ODT_OTHER_DIMM,
101 FSL_DDR_ODT_OTHER_DIMM,
107 FSL_DDR_ODT_SAME_DIMM,
112 FSL_DDR_ODT_OTHER_DIMM,
113 FSL_DDR_ODT_OTHER_DIMM,
119 static const struct dynamic_odt dual_DS[4] = {
122 FSL_DDR_ODT_SAME_DIMM,
127 FSL_DDR_ODT_OTHER_DIMM,
128 FSL_DDR_ODT_OTHER_DIMM,
133 FSL_DDR_ODT_OTHER_DIMM,
140 static const struct dynamic_odt dual_SD[4] = {
142 FSL_DDR_ODT_OTHER_DIMM,
150 FSL_DDR_ODT_SAME_DIMM,
155 FSL_DDR_ODT_OTHER_DIMM,
156 FSL_DDR_ODT_OTHER_DIMM,
162 static const struct dynamic_odt dual_SS[4] = {
164 FSL_DDR_ODT_OTHER_DIMM,
171 FSL_DDR_ODT_OTHER_DIMM,
179 static const struct dynamic_odt dual_D0[4] = {
182 FSL_DDR_ODT_SAME_DIMM,
196 static const struct dynamic_odt dual_0D[4] = {
201 FSL_DDR_ODT_SAME_DIMM,
213 static const struct dynamic_odt dual_S0[4] = {
226 static const struct dynamic_odt dual_0S[4] = {
239 static const struct dynamic_odt odt_unknown[4] = {
265 #else /* CONFIG_FSL_DDR3 */
266 static const struct dynamic_odt single_Q[4] = {
273 static const struct dynamic_odt single_D[4] = {
290 static const struct dynamic_odt single_S[4] = {
302 static const struct dynamic_odt dual_DD[4] = {
304 FSL_DDR_ODT_OTHER_DIMM,
305 FSL_DDR_ODT_OTHER_DIMM,
316 FSL_DDR_ODT_OTHER_DIMM,
317 FSL_DDR_ODT_OTHER_DIMM,
329 static const struct dynamic_odt dual_DS[4] = {
331 FSL_DDR_ODT_OTHER_DIMM,
332 FSL_DDR_ODT_OTHER_DIMM,
343 FSL_DDR_ODT_OTHER_DIMM,
344 FSL_DDR_ODT_OTHER_DIMM,
351 static const struct dynamic_odt dual_SD[4] = {
353 FSL_DDR_ODT_OTHER_DIMM,
354 FSL_DDR_ODT_OTHER_DIMM,
360 FSL_DDR_ODT_OTHER_DIMM,
361 FSL_DDR_ODT_OTHER_DIMM,
373 static const struct dynamic_odt dual_SS[4] = {
375 FSL_DDR_ODT_OTHER_DIMM,
376 FSL_DDR_ODT_OTHER_DIMM,
382 FSL_DDR_ODT_OTHER_DIMM,
383 FSL_DDR_ODT_OTHER_DIMM,
390 static const struct dynamic_odt dual_D0[4] = {
407 static const struct dynamic_odt dual_0D[4] = {
424 static const struct dynamic_odt dual_S0[4] = {
437 static const struct dynamic_odt dual_0S[4] = {
450 static const struct dynamic_odt odt_unknown[4] = {
479 * Automatically seleect bank interleaving mode based on DIMMs
480 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
481 * This function only deal with one or two slots per controller.
483 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
485 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
486 if (pdimm[0].n_ranks == 4)
487 return FSL_DDR_CS0_CS1_CS2_CS3;
488 else if (pdimm[0].n_ranks == 2)
489 return FSL_DDR_CS0_CS1;
490 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
491 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
492 if (pdimm[0].n_ranks == 4)
493 return FSL_DDR_CS0_CS1_CS2_CS3;
495 if (pdimm[0].n_ranks == 2) {
496 if (pdimm[1].n_ranks == 2)
497 return FSL_DDR_CS0_CS1_CS2_CS3;
499 return FSL_DDR_CS0_CS1;
505 unsigned int populate_memctl_options(int all_DIMMs_registered,
506 memctl_options_t *popts,
507 dimm_params_t *pdimm,
508 unsigned int ctrl_num)
511 char buffer[HWCONFIG_BUFFER_SIZE];
513 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
514 const struct dynamic_odt *pdodt = odt_unknown;
519 * Extract hwconfig from environment since we have not properly setup
520 * the environment but need it for ddr config params
522 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
525 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
526 /* Chip select options. */
527 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
528 switch (pdimm[0].n_ranks) {
539 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
540 switch (pdimm[0].n_ranks) {
541 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
544 if (pdimm[1].n_ranks)
545 printf("Error: Quad- and Dual-rank DIMMs "
546 "cannot be used together\n");
550 switch (pdimm[1].n_ranks) {
563 switch (pdimm[1].n_ranks) {
576 switch (pdimm[1].n_ranks) {
589 /* Pick chip-select local options. */
590 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
591 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
592 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
593 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
594 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
595 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
597 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
598 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
600 popts->cs_local_opts[i].auto_precharge = 0;
603 /* Pick interleaving mode. */
606 * 0 = no interleaving
607 * 1 = interleaving between 2 controllers
609 popts->memctl_interleaving = 0;
615 * 3 = superbank (only if CS interleaving is enabled)
617 popts->memctl_interleaving_mode = 0;
620 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
621 * 1: page: bit to the left of the column bits selects the memctl
622 * 2: bank: bit to the left of the bank bits selects the memctl
623 * 3: superbank: bit to the left of the chip select selects the memctl
625 * NOTE: ba_intlv (rank interleaving) is independent of memory
626 * controller interleaving; it is only within a memory controller.
627 * Must use superbank interleaving if rank interleaving is used and
628 * memory controller interleaving is enabled.
635 * 0x60 = CS0,CS1 + CS2,CS3
636 * 0x04 = CS0,CS1,CS2,CS3
638 popts->ba_intlv_ctl = 0;
640 /* Memory Organization Parameters */
641 popts->registered_dimm_en = all_DIMMs_registered;
643 /* Operational Mode Paramters */
646 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
647 #ifdef CONFIG_DDR_ECC
648 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
649 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
654 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
661 #if defined(CONFIG_FSL_DDR1)
662 popts->DQS_config = 0;
663 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
664 popts->DQS_config = 1;
667 /* Choose self-refresh during sleep. */
668 popts->self_refresh_in_sleep = 1;
670 /* Choose dynamic power management mode. */
671 popts->dynamic_power = 0;
674 * check first dimm for primary sdram width
675 * presuming all dimms are similar
676 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
678 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
679 if (pdimm[0].n_ranks != 0) {
680 if ((pdimm[0].data_width >= 64) && \
681 (pdimm[0].data_width <= 72))
682 popts->data_bus_width = 0;
683 else if ((pdimm[0].data_width >= 32) || \
684 (pdimm[0].data_width <= 40))
685 popts->data_bus_width = 1;
687 panic("Error: data width %u is invalid!\n",
688 pdimm[0].data_width);
692 if (pdimm[0].n_ranks != 0) {
693 if (pdimm[0].primary_sdram_width == 64)
694 popts->data_bus_width = 0;
695 else if (pdimm[0].primary_sdram_width == 32)
696 popts->data_bus_width = 1;
697 else if (pdimm[0].primary_sdram_width == 16)
698 popts->data_bus_width = 2;
700 panic("Error: primary sdram width %u is invalid!\n",
701 pdimm[0].primary_sdram_width);
706 /* Choose burst length. */
707 #if defined(CONFIG_FSL_DDR3)
708 #if defined(CONFIG_E500MC)
709 popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
710 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
712 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
713 /* 32-bit or 16-bit bus */
714 popts->OTF_burst_chop_en = 0;
715 popts->burst_length = DDR_BL8;
717 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
718 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
722 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
725 /* Choose ddr controller address mirror mode */
726 #if defined(CONFIG_FSL_DDR3)
727 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
730 /* Global Timing Parameters. */
731 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
733 /* Pick a caslat override. */
734 popts->cas_latency_override = 0;
735 popts->cas_latency_override_value = 3;
736 if (popts->cas_latency_override) {
737 debug("using caslat override value = %u\n",
738 popts->cas_latency_override_value);
741 /* Decide whether to use the computed derated latency */
742 popts->use_derated_caslat = 0;
744 /* Choose an additive latency. */
745 popts->additive_latency_override = 0;
746 popts->additive_latency_override_value = 3;
747 if (popts->additive_latency_override) {
748 debug("using additive latency override value = %u\n",
749 popts->additive_latency_override_value);
755 * Factors to consider for 2T_EN:
756 * - number of DIMMs installed
757 * - number of components, number of active ranks
758 * - how much time you want to spend playing around
761 popts->threeT_en = 0;
763 /* for RDIMM, address parity enable */
767 * BSTTOPRE precharge interval
769 * Set this to 0 for global auto precharge
771 * FIXME: Should this be configured in picoseconds?
772 * Why it should be in ps: better understanding of this
773 * relative to actual DRAM timing parameters such as tRAS.
774 * e.g. tRAS(min) = 40 ns
776 popts->bstopre = 0x100;
778 /* Minimum CKE pulse width -- tCKE(MIN) */
779 popts->tCKE_clock_pulse_width_ps
780 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
783 * Window for four activates -- tFAW
785 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
786 * FIXME: varies depending upon number of column addresses or data
787 * FIXME: width, was considering looking at pdimm->primary_sdram_width
789 #if defined(CONFIG_FSL_DDR1)
790 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
792 #elif defined(CONFIG_FSL_DDR2)
794 * x4/x8; some datasheets have 35000
795 * x16 wide columns only? Use 50000?
797 popts->tFAW_window_four_activates_ps = 37500;
799 #elif defined(CONFIG_FSL_DDR3)
800 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
804 #if defined(CONFIG_FSL_DDR3)
806 * due to ddr3 dimm is fly-by topology
807 * we suggest to enable write leveling to
808 * meet the tQDSS under different loading.
812 popts->wrlvl_override = 0;
816 * Check interleaving configuration from environment.
817 * Please refer to doc/README.fsl-ddr for the detail.
819 * If memory controller interleaving is enabled, then the data
820 * bus widths must be programmed identically for all memory controllers.
822 * XXX: Attempt to set all controllers to the same chip select
823 * interleaving mode. It will do a best effort to get the
824 * requested ranks interleaved together such that the result
825 * should be a subset of the requested configuration.
827 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
828 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
831 if (pdimm[0].n_ranks == 0) {
832 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
833 popts->memctl_interleaving = 0;
836 popts->memctl_interleaving = 1;
838 * test null first. if CONFIG_HWCONFIG is not defined
839 * hwconfig_arg_cmp returns non-zero
841 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
843 popts->memctl_interleaving = 0;
844 debug("memory controller interleaving disabled.\n");
845 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
848 popts->memctl_interleaving_mode =
849 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
850 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
851 popts->memctl_interleaving =
852 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
854 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
857 popts->memctl_interleaving_mode =
858 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
859 0 : FSL_DDR_PAGE_INTERLEAVING;
860 popts->memctl_interleaving =
861 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
863 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
866 popts->memctl_interleaving_mode =
867 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
868 0 : FSL_DDR_BANK_INTERLEAVING;
869 popts->memctl_interleaving =
870 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
872 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
875 popts->memctl_interleaving_mode =
876 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
877 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
878 popts->memctl_interleaving =
879 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
881 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
882 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
885 popts->memctl_interleaving_mode =
886 FSL_DDR_3WAY_1KB_INTERLEAVING;
887 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
890 popts->memctl_interleaving_mode =
891 FSL_DDR_3WAY_4KB_INTERLEAVING;
892 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
895 popts->memctl_interleaving_mode =
896 FSL_DDR_3WAY_8KB_INTERLEAVING;
897 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
898 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
901 popts->memctl_interleaving_mode =
902 FSL_DDR_4WAY_1KB_INTERLEAVING;
903 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
906 popts->memctl_interleaving_mode =
907 FSL_DDR_4WAY_4KB_INTERLEAVING;
908 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
911 popts->memctl_interleaving_mode =
912 FSL_DDR_4WAY_8KB_INTERLEAVING;
915 popts->memctl_interleaving = 0;
916 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
920 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
921 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
922 /* test null first. if CONFIG_HWCONFIG is not defined,
923 * hwconfig_subarg_cmp_f returns non-zero */
924 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
926 debug("bank interleaving disabled.\n");
927 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
929 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
930 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
932 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
933 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
934 "cs0_cs1_and_cs2_cs3", buf))
935 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
936 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
937 "cs0_cs1_cs2_cs3", buf))
938 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
939 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
941 popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
943 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
944 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
945 case FSL_DDR_CS0_CS1_CS2_CS3:
946 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
947 if (pdimm[0].n_ranks < 4) {
948 popts->ba_intlv_ctl = 0;
949 printf("Not enough bank(chip-select) for "
950 "CS0+CS1+CS2+CS3 on controller %d, "
951 "interleaving disabled!\n", ctrl_num);
953 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
954 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
955 if (pdimm[0].n_ranks == 4)
958 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
959 popts->ba_intlv_ctl = 0;
960 printf("Not enough bank(chip-select) for "
961 "CS0+CS1+CS2+CS3 on controller %d, "
962 "interleaving disabled!\n", ctrl_num);
964 if (pdimm[0].capacity != pdimm[1].capacity) {
965 popts->ba_intlv_ctl = 0;
966 printf("Not identical DIMM size for "
967 "CS0+CS1+CS2+CS3 on controller %d, "
968 "interleaving disabled!\n", ctrl_num);
972 case FSL_DDR_CS0_CS1:
973 if (pdimm[0].n_ranks < 2) {
974 popts->ba_intlv_ctl = 0;
975 printf("Not enough bank(chip-select) for "
976 "CS0+CS1 on controller %d, "
977 "interleaving disabled!\n", ctrl_num);
980 case FSL_DDR_CS2_CS3:
981 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
982 if (pdimm[0].n_ranks < 4) {
983 popts->ba_intlv_ctl = 0;
984 printf("Not enough bank(chip-select) for CS2+CS3 "
985 "on controller %d, interleaving disabled!\n", ctrl_num);
987 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
988 if (pdimm[1].n_ranks < 2) {
989 popts->ba_intlv_ctl = 0;
990 printf("Not enough bank(chip-select) for CS2+CS3 "
991 "on controller %d, interleaving disabled!\n", ctrl_num);
995 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
996 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
997 if (pdimm[0].n_ranks < 4) {
998 popts->ba_intlv_ctl = 0;
999 printf("Not enough bank(CS) for CS0+CS1 and "
1000 "CS2+CS3 on controller %d, "
1001 "interleaving disabled!\n", ctrl_num);
1003 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1004 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
1005 popts->ba_intlv_ctl = 0;
1006 printf("Not enough bank(CS) for CS0+CS1 and "
1007 "CS2+CS3 on controller %d, "
1008 "interleaving disabled!\n", ctrl_num);
1013 popts->ba_intlv_ctl = 0;
1018 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1019 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
1020 popts->addr_hash = 0;
1021 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1023 popts->addr_hash = 1;
1026 if (pdimm[0].n_ranks == 4)
1027 popts->quad_rank_present = 1;
1029 ddr_freq = get_ddr_freq(0) / 1000000;
1030 if (popts->registered_dimm_en) {
1031 popts->rcw_override = 1;
1032 popts->rcw_1 = 0x000a5a00;
1033 if (ddr_freq <= 800)
1034 popts->rcw_2 = 0x00000000;
1035 else if (ddr_freq <= 1066)
1036 popts->rcw_2 = 0x00100000;
1037 else if (ddr_freq <= 1333)
1038 popts->rcw_2 = 0x00200000;
1040 popts->rcw_2 = 0x00300000;
1043 fsl_ddr_board_options(popts, pdimm, ctrl_num);
1048 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1050 int i, j, k, check_n_ranks, intlv_invalid = 0;
1051 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1052 unsigned long long check_rank_density;
1053 struct dimm_params_s *dimm;
1055 * Check if all controllers are configured for memory
1056 * controller interleaving. Identical dimms are recommended. At least
1057 * the size, row and col address should be checked.
1060 check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
1061 check_rank_density = pinfo->dimm_params[0][0].rank_density;
1062 check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr;
1063 check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr;
1064 check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode;
1065 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1066 dimm = &pinfo->dimm_params[i][0];
1067 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1069 } else if (((check_rank_density != dimm->rank_density) ||
1070 (check_n_ranks != dimm->n_ranks) ||
1071 (check_n_row_addr != dimm->n_row_addr) ||
1072 (check_n_col_addr != dimm->n_col_addr) ||
1074 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1082 if (intlv_invalid) {
1083 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1084 pinfo->memctl_opts[i].memctl_interleaving = 0;
1085 printf("Not all DIMMs are identical. "
1086 "Memory controller interleaving disabled.\n");
1088 switch (check_intlv) {
1089 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1090 case FSL_DDR_PAGE_INTERLEAVING:
1091 case FSL_DDR_BANK_INTERLEAVING:
1092 case FSL_DDR_SUPERBANK_INTERLEAVING:
1093 if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1096 k = CONFIG_NUM_DDR_CONTROLLERS;
1098 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1099 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1100 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1101 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1102 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1103 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1105 k = CONFIG_NUM_DDR_CONTROLLERS;
1108 debug("%d of %d controllers are interleaving.\n", j, k);
1109 if (j && (j != k)) {
1110 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1111 pinfo->memctl_opts[i].memctl_interleaving = 0;
1112 printf("Not all controllers have compatible "
1113 "interleaving mode. All disabled.\n");
1116 debug("Checking interleaving options completed\n");
1119 int fsl_use_spd(void)
1123 #ifdef CONFIG_DDR_SPD
1124 char buffer[HWCONFIG_BUFFER_SIZE];
1128 * Extract hwconfig from environment since we have not properly setup
1129 * the environment but need it for ddr config params
1131 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1134 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1135 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1136 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1138 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",