arch/powerpc/cpu/ppc4xx/iop480_uart.c

   1 /*
   2  * (C) Copyright 2000-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <commproc.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <watchdog.h>
  29 #include <serial.h>
  30 #include <linux/compiler.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #ifdef CONFIG_IOP480
  35
  36 #define SPU_BASE         0x40000000
  37
  38 #define spu_LineStat_rc  0x00   /* Line Status Register (Read/Clear) */
  39 #define spu_LineStat_w   0x04   /* Line Status Register (Set) */
  40 #define spu_Handshk_rc   0x08   /* Handshake Status Register (Read/Clear) */
  41 #define spu_Handshk_w    0x0c   /* Handshake Status Register (Set) */
  42 #define spu_BRateDivh    0x10   /* Baud rate divisor high */
  43 #define spu_BRateDivl    0x14   /* Baud rate divisor low */
  44 #define spu_CtlReg       0x18   /* Control Register */
  45 #define spu_RxCmd        0x1c   /* Rx Command Register */
  46 #define spu_TxCmd        0x20   /* Tx Command Register */
  47 #define spu_RxBuff       0x24   /* Rx data buffer */
  48 #define spu_TxBuff       0x24   /* Tx data buffer */
  49
  50 /*-----------------------------------------------------------------------------+
  51   | Line Status Register.
  52   +-----------------------------------------------------------------------------*/
  53 #define asyncLSRport1           0x40000000
  54 #define asyncLSRport1set        0x40000004
  55 #define asyncLSRDataReady             0x80
  56 #define asyncLSRFramingError          0x40
  57 #define asyncLSROverrunError          0x20
  58 #define asyncLSRParityError           0x10
  59 #define asyncLSRBreakInterrupt        0x08
  60 #define asyncLSRTxHoldEmpty           0x04
  61 #define asyncLSRTxShiftEmpty          0x02
  62
  63 /*-----------------------------------------------------------------------------+
  64   | Handshake Status Register.
  65   +-----------------------------------------------------------------------------*/
  66 #define asyncHSRport1           0x40000008
  67 #define asyncHSRport1set        0x4000000c
  68 #define asyncHSRDsr                   0x80
  69 #define asyncLSRCts                   0x40
  70
  71 /*-----------------------------------------------------------------------------+
  72   | Control Register.
  73   +-----------------------------------------------------------------------------*/
  74 #define asyncCRport1            0x40000018
  75 #define asyncCRNormal                 0x00
  76 #define asyncCRLoopback               0x40
  77 #define asyncCRAutoEcho               0x80
  78 #define asyncCRDtr                    0x20
  79 #define asyncCRRts                    0x10
  80 #define asyncCRWordLength7            0x00
  81 #define asyncCRWordLength8            0x08
  82 #define asyncCRParityDisable          0x00
  83 #define asyncCRParityEnable           0x04
  84 #define asyncCREvenParity             0x00
  85 #define asyncCROddParity              0x02
  86 #define asyncCRStopBitsOne            0x00
  87 #define asyncCRStopBitsTwo            0x01
  88 #define asyncCRDisableDtrRts          0x00
  89
  90 /*-----------------------------------------------------------------------------+
  91   | Receiver Command Register.
  92   +-----------------------------------------------------------------------------*/
  93 #define asyncRCRport1           0x4000001c
  94 #define asyncRCRDisable               0x00
  95 #define asyncRCREnable                0x80
  96 #define asyncRCRIntDisable            0x00
  97 #define asyncRCRIntEnabled            0x20
  98 #define asyncRCRDMACh2                0x40
  99 #define asyncRCRDMACh3                0x60
 100 #define asyncRCRErrorInt              0x10
 101 #define asyncRCRPauseEnable           0x08
 102
 103 /*-----------------------------------------------------------------------------+
 104   | Transmitter Command Register.
 105   +-----------------------------------------------------------------------------*/
 106 #define asyncTCRport1           0x40000020
 107 #define asyncTCRDisable               0x00
 108 #define asyncTCREnable                0x80
 109 #define asyncTCRIntDisable            0x00
 110 #define asyncTCRIntEnabled            0x20
 111 #define asyncTCRDMACh2                0x40
 112 #define asyncTCRDMACh3                0x60
 113 #define asyncTCRTxEmpty               0x10
 114 #define asyncTCRErrorInt              0x08
 115 #define asyncTCRStopPause             0x04
 116 #define asyncTCRBreakGen              0x02
 117
 118 /*-----------------------------------------------------------------------------+
 119   | Miscellanies defines.
 120   +-----------------------------------------------------------------------------*/
 121 #define asyncTxBufferport1      0x40000024
 122 #define asyncRxBufferport1      0x40000024
 123 #define asyncDLABLsbport1       0x40000014
 124 #define asyncDLABMsbport1       0x40000010
 125 #define asyncXOFFchar                 0x13
 126 #define asyncXONchar                  0x11
 127
 128 /*
 129  * Minimal serial functions needed to use one of the SMC ports
 130  * as serial console interface.
 131  */
 132
 133 static int iop480_serial_init(void)
 134 {
 135         unsigned short br_reg;
 136
 137         br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
 138
 139         /*
 140          * Init onboard UART
 141          */
 142         out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
 143         out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
 144         out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
 145         out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08);       /* Set 8 bits, no parity and 1 stop bit */
 146         out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0);        /* Enable Rx */
 147         out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c);        /* Enable Tx */
 148         out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff);   /* Clear Handshake */
 149         in_8((u8 *)SPU_BASE + spu_RxBuff);      /* Dummy read, to clear receiver */
 150
 151         return (0);
 152 }
 153
 154 static void iop480_serial_setbrg(void)
 155 {
 156         unsigned short br_reg;
 157
 158         br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
 159
 160         out_8((u8 *)SPU_BASE + spu_BRateDivl,
 161               (br_reg & 0x00ff)); /* Set baud rate divisor... */
 162         out_8((u8 *)SPU_BASE + spu_BRateDivh,
 163               ((br_reg & 0xff00) >> 8)); /* ... */
 164 }
 165
 166 static void iop480_serial_putc(const char c)
 167 {
 168         if (c == '\n')
 169                 serial_putc ('\r');
 170
 171         /* load status from handshake register */
 172         if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
 173                 out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff);   /* Clear Handshake */
 174
 175         out_8((u8 *)SPU_BASE + spu_TxBuff, c);  /* Put char */
 176
 177         while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) {
 178                 if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
 179                         out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff);   /* Clear Handshake */
 180         }
 181 }
 182
 183 static void iop480_serial_puts(const char *s)
 184 {
 185         while (*s) {
 186                 serial_putc (*s++);
 187         }
 188 }
 189
 190 static int iop480_serial_getc(void)
 191 {
 192         unsigned char status = 0;
 193
 194         while (1) {
 195                 status = in_8((u8 *)asyncLSRport1);
 196                 if ((status & asyncLSRDataReady) != 0x0) {
 197                         break;
 198                 }
 199                 if ((status & ( asyncLSRFramingError |
 200                                 asyncLSROverrunError |
 201                                 asyncLSRParityError  |
 202                                 asyncLSRBreakInterrupt )) != 0) {
 203                         (void) out_8((u8 *)asyncLSRport1,
 204                                      asyncLSRFramingError |
 205                                      asyncLSROverrunError |
 206                                      asyncLSRParityError  |
 207                                      asyncLSRBreakInterrupt );
 208                 }
 209         }
 210         return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1));
 211 }
 212
 213 static int iop480_serial_tstc(void)
 214 {
 215         unsigned char status;
 216
 217         status = in_8((u8 *)asyncLSRport1);
 218         if ((status & asyncLSRDataReady) != 0x0) {
 219                 return (1);
 220         }
 221         if ((status & ( asyncLSRFramingError |
 222                         asyncLSROverrunError |
 223                         asyncLSRParityError  |
 224                         asyncLSRBreakInterrupt )) != 0) {
 225                 (void) out_8((u8 *)asyncLSRport1,
 226                              asyncLSRFramingError |
 227                              asyncLSROverrunError |
 228                              asyncLSRParityError  |
 229                              asyncLSRBreakInterrupt);
 230         }
 231         return 0;
 232 }
 233
 234 static struct serial_device iop480_serial_drv = {
 235         .name   = "iop480_serial",
 236         .start  = iop480_serial_init,
 237         .stop   = NULL,
 238         .setbrg = iop480_serial_setbrg,
 239         .putc   = iop480_serial_putc,
 240         .puts   = iop480_serial_puts,
 241         .getc   = iop480_serial_getc,
 242         .tstc   = iop480_serial_tstc,
 243 };
 244
 245 void iop480_serial_initialize(void)
 246 {
 247         serial_register(&iop480_serial_drv);
 248 }
 249
 250 __weak struct serial_device *default_serial_console(void)
 251 {
 252         return &iop480_serial_drv;
 253 }
 254 #endif  /* CONFIG_IOP480 */