2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
22 #define FSL_DDR_VER_4_7 47
24 /* Number of TLB CAM entries we have on FSL Book-E chips */
25 #if defined(CONFIG_E500MC)
26 #define CONFIG_SYS_NUM_TLBCAMS 64
27 #elif defined(CONFIG_E500)
28 #define CONFIG_SYS_NUM_TLBCAMS 16
31 #if defined(CONFIG_MPC8536)
32 #define CONFIG_MAX_CPUS 1
33 #define CONFIG_SYS_FSL_NUM_LAWS 12
34 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
35 #define CONFIG_SYS_FSL_SEC_COMPAT 2
36 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
38 #elif defined(CONFIG_MPC8540)
39 #define CONFIG_MAX_CPUS 1
40 #define CONFIG_SYS_FSL_NUM_LAWS 8
41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
43 #elif defined(CONFIG_MPC8541)
44 #define CONFIG_MAX_CPUS 1
45 #define CONFIG_SYS_FSL_NUM_LAWS 8
46 #define CONFIG_SYS_FSL_SEC_COMPAT 2
47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
49 #elif defined(CONFIG_MPC8544)
50 #define CONFIG_MAX_CPUS 1
51 #define CONFIG_SYS_FSL_NUM_LAWS 10
52 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
53 #define CONFIG_SYS_FSL_SEC_COMPAT 2
54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
56 #elif defined(CONFIG_MPC8548)
57 #define CONFIG_MAX_CPUS 1
58 #define CONFIG_SYS_FSL_NUM_LAWS 10
59 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
60 #define CONFIG_SYS_FSL_SEC_COMPAT 2
61 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
62 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
63 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
64 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
65 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
66 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
67 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
68 #define CONFIG_SYS_FSL_RMU
69 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
71 #elif defined(CONFIG_MPC8555)
72 #define CONFIG_MAX_CPUS 1
73 #define CONFIG_SYS_FSL_NUM_LAWS 8
74 #define CONFIG_SYS_FSL_SEC_COMPAT 2
75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
77 #elif defined(CONFIG_MPC8560)
78 #define CONFIG_MAX_CPUS 1
79 #define CONFIG_SYS_FSL_NUM_LAWS 8
80 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
82 #elif defined(CONFIG_MPC8568)
83 #define CONFIG_MAX_CPUS 1
84 #define CONFIG_SYS_FSL_NUM_LAWS 10
85 #define CONFIG_SYS_FSL_SEC_COMPAT 2
86 #define QE_MURAM_SIZE 0x10000UL
88 #define QE_NUM_OF_SNUM 28
89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
90 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
91 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
92 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
93 #define CONFIG_SYS_FSL_RMU
94 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
96 #elif defined(CONFIG_MPC8569)
97 #define CONFIG_MAX_CPUS 1
98 #define CONFIG_SYS_FSL_NUM_LAWS 10
99 #define CONFIG_SYS_FSL_SEC_COMPAT 2
100 #define QE_MURAM_SIZE 0x20000UL
101 #define MAX_QE_RISC 4
102 #define QE_NUM_OF_SNUM 46
103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
104 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
105 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
106 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
107 #define CONFIG_SYS_FSL_RMU
108 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
110 #elif defined(CONFIG_MPC8572)
111 #define CONFIG_MAX_CPUS 2
112 #define CONFIG_SYS_FSL_NUM_LAWS 12
113 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
114 #define CONFIG_SYS_FSL_SEC_COMPAT 2
115 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
116 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
117 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
119 #elif defined(CONFIG_P1010)
120 #define CONFIG_MAX_CPUS 1
121 #define CONFIG_FSL_SDHC_V2_3
122 #define CONFIG_SYS_FSL_NUM_LAWS 12
123 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
124 #define CONFIG_TSECV2
125 #define CONFIG_SYS_FSL_SEC_COMPAT 4
126 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
127 #define CONFIG_NUM_DDR_CONTROLLERS 1
128 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
130 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
131 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
132 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
133 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
134 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
136 /* P1011 is single core version of P1020 */
137 #elif defined(CONFIG_P1011)
138 #define CONFIG_MAX_CPUS 1
139 #define CONFIG_SYS_FSL_NUM_LAWS 12
140 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
141 #define CONFIG_TSECV2
142 #define CONFIG_FSL_PCIE_DISABLE_ASPM
143 #define CONFIG_SYS_FSL_SEC_COMPAT 2
144 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
145 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
146 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
148 /* P1012 is single core version of P1021 */
149 #elif defined(CONFIG_P1012)
150 #define CONFIG_MAX_CPUS 1
151 #define CONFIG_SYS_FSL_NUM_LAWS 12
152 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
153 #define CONFIG_TSECV2
154 #define CONFIG_FSL_PCIE_DISABLE_ASPM
155 #define CONFIG_SYS_FSL_SEC_COMPAT 2
156 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
157 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
158 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
159 #define QE_MURAM_SIZE 0x6000UL
160 #define MAX_QE_RISC 1
161 #define QE_NUM_OF_SNUM 28
163 /* P1013 is single core version of P1022 */
164 #elif defined(CONFIG_P1013)
165 #define CONFIG_MAX_CPUS 1
166 #define CONFIG_SYS_FSL_NUM_LAWS 12
167 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
168 #define CONFIG_TSECV2
169 #define CONFIG_SYS_FSL_SEC_COMPAT 2
170 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
171 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
172 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
173 #define CONFIG_FSL_SATA_ERRATUM_A001
175 #elif defined(CONFIG_P1014)
176 #define CONFIG_MAX_CPUS 1
177 #define CONFIG_FSL_SDHC_V2_3
178 #define CONFIG_SYS_FSL_NUM_LAWS 12
179 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
180 #define CONFIG_TSECV2
181 #define CONFIG_SYS_FSL_SEC_COMPAT 4
182 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
183 #define CONFIG_NUM_DDR_CONTROLLERS 1
184 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
185 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
186 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
187 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
188 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
190 /* P1017 is single core version of P1023 */
191 #elif defined(CONFIG_P1017)
192 #define CONFIG_MAX_CPUS 1
193 #define CONFIG_SYS_FSL_NUM_LAWS 12
194 #define CONFIG_SYS_FSL_SEC_COMPAT 4
195 #define CONFIG_SYS_NUM_FMAN 1
196 #define CONFIG_SYS_NUM_FM1_DTSEC 2
197 #define CONFIG_NUM_DDR_CONTROLLERS 1
198 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
199 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
200 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
201 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
202 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
204 #elif defined(CONFIG_P1020)
205 #define CONFIG_MAX_CPUS 2
206 #define CONFIG_SYS_FSL_NUM_LAWS 12
207 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
208 #define CONFIG_TSECV2
209 #define CONFIG_FSL_PCIE_DISABLE_ASPM
210 #define CONFIG_SYS_FSL_SEC_COMPAT 2
211 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
212 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
213 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
215 #elif defined(CONFIG_P1021)
216 #define CONFIG_MAX_CPUS 2
217 #define CONFIG_SYS_FSL_NUM_LAWS 12
218 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
219 #define CONFIG_TSECV2
220 #define CONFIG_FSL_PCIE_DISABLE_ASPM
221 #define CONFIG_SYS_FSL_SEC_COMPAT 2
222 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
223 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
224 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
225 #define QE_MURAM_SIZE 0x6000UL
226 #define MAX_QE_RISC 1
227 #define QE_NUM_OF_SNUM 28
229 #elif defined(CONFIG_P1022)
230 #define CONFIG_MAX_CPUS 2
231 #define CONFIG_SYS_FSL_NUM_LAWS 12
232 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
233 #define CONFIG_TSECV2
234 #define CONFIG_SYS_FSL_SEC_COMPAT 2
235 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
236 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
237 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
238 #define CONFIG_FSL_SATA_ERRATUM_A001
240 #elif defined(CONFIG_P1023)
241 #define CONFIG_MAX_CPUS 2
242 #define CONFIG_SYS_FSL_NUM_LAWS 12
243 #define CONFIG_SYS_FSL_SEC_COMPAT 4
244 #define CONFIG_SYS_NUM_FMAN 1
245 #define CONFIG_SYS_NUM_FM1_DTSEC 2
246 #define CONFIG_NUM_DDR_CONTROLLERS 1
247 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
248 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
249 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
250 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
251 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
253 /* P1024 is lower end variant of P1020 */
254 #elif defined(CONFIG_P1024)
255 #define CONFIG_MAX_CPUS 2
256 #define CONFIG_SYS_FSL_NUM_LAWS 12
257 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
258 #define CONFIG_TSECV2
259 #define CONFIG_FSL_PCIE_DISABLE_ASPM
260 #define CONFIG_SYS_FSL_SEC_COMPAT 2
261 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
262 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
263 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
265 /* P1025 is lower end variant of P1021 */
266 #elif defined(CONFIG_P1025)
267 #define CONFIG_MAX_CPUS 2
268 #define CONFIG_SYS_FSL_NUM_LAWS 12
269 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
270 #define CONFIG_TSECV2
271 #define CONFIG_FSL_PCIE_DISABLE_ASPM
272 #define CONFIG_SYS_FSL_SEC_COMPAT 2
273 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
274 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
275 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
276 #define QE_MURAM_SIZE 0x6000UL
277 #define MAX_QE_RISC 1
278 #define QE_NUM_OF_SNUM 28
280 /* P2010 is single core version of P2020 */
281 #elif defined(CONFIG_P2010)
282 #define CONFIG_MAX_CPUS 1
283 #define CONFIG_SYS_FSL_NUM_LAWS 12
284 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
285 #define CONFIG_SYS_FSL_SEC_COMPAT 2
286 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
287 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
288 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
290 #elif defined(CONFIG_P2020)
291 #define CONFIG_MAX_CPUS 2
292 #define CONFIG_SYS_FSL_NUM_LAWS 12
293 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
294 #define CONFIG_SYS_FSL_SEC_COMPAT 2
295 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
296 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
297 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
298 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
299 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
300 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
301 #define CONFIG_SYS_FSL_RMU
302 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
304 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
305 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
306 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
307 #define CONFIG_MAX_CPUS 4
308 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
309 #define CONFIG_SYS_FSL_NUM_LAWS 32
310 #define CONFIG_SYS_FSL_SEC_COMPAT 4
311 #define CONFIG_SYS_NUM_FMAN 1
312 #define CONFIG_SYS_NUM_FM1_DTSEC 5
313 #define CONFIG_SYS_NUM_FM1_10GEC 1
314 #define CONFIG_NUM_DDR_CONTROLLERS 1
315 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
316 #define CONFIG_SYS_FSL_TBCLK_DIV 32
317 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
318 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
319 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
320 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
321 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
322 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
323 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
324 #define CONFIG_SYS_FSL_ERRATUM_USB14
325 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
326 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
327 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
328 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
329 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
330 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
331 #define CONFIG_SYS_FSL_ERRATUM_A004510
332 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
333 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
334 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
335 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
336 #define CONFIG_SYS_FSL_ERRATUM_A004849
338 #elif defined(CONFIG_PPC_P3041)
339 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
340 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
341 #define CONFIG_MAX_CPUS 4
342 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
343 #define CONFIG_SYS_FSL_NUM_LAWS 32
344 #define CONFIG_SYS_FSL_SEC_COMPAT 4
345 #define CONFIG_SYS_NUM_FMAN 1
346 #define CONFIG_SYS_NUM_FM1_DTSEC 5
347 #define CONFIG_SYS_NUM_FM1_10GEC 1
348 #define CONFIG_NUM_DDR_CONTROLLERS 1
349 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
350 #define CONFIG_SYS_FSL_TBCLK_DIV 32
351 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
352 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
353 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
354 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
355 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
356 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
357 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
358 #define CONFIG_SYS_FSL_ERRATUM_USB14
359 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
360 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
361 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
362 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
363 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
364 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
365 #define CONFIG_SYS_FSL_ERRATUM_A004510
366 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
367 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
368 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
369 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
370 #define CONFIG_SYS_FSL_ERRATUM_A004849
372 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
373 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
374 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
375 #define CONFIG_MAX_CPUS 8
376 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
377 #define CONFIG_SYS_FSL_NUM_LAWS 32
378 #define CONFIG_SYS_FSL_SEC_COMPAT 4
379 #define CONFIG_SYS_NUM_FMAN 2
380 #define CONFIG_SYS_NUM_FM1_DTSEC 4
381 #define CONFIG_SYS_NUM_FM2_DTSEC 4
382 #define CONFIG_SYS_NUM_FM1_10GEC 1
383 #define CONFIG_SYS_NUM_FM2_10GEC 1
384 #define CONFIG_NUM_DDR_CONTROLLERS 2
385 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
386 #define CONFIG_SYS_FSL_TBCLK_DIV 16
387 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
388 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
389 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
390 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
391 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
392 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
393 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
394 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
395 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
396 #define CONFIG_SYS_P4080_ERRATUM_CPU22
397 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
398 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
399 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
400 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
401 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
402 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
403 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
404 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
405 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
406 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
407 #define CONFIG_SYS_FSL_RMU
408 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
409 #define CONFIG_SYS_FSL_ERRATUM_A004510
410 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
411 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
412 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
413 #define CONFIG_SYS_FSL_ERRATUM_A004849
414 #define CONFIG_SYS_FSL_ERRATUM_A004580
415 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
417 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
418 #define CONFIG_SYS_PPC64 /* 64-bit core */
419 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
420 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
421 #define CONFIG_MAX_CPUS 2
422 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
423 #define CONFIG_SYS_FSL_NUM_LAWS 32
424 #define CONFIG_SYS_FSL_SEC_COMPAT 4
425 #define CONFIG_SYS_NUM_FMAN 1
426 #define CONFIG_SYS_NUM_FM1_DTSEC 5
427 #define CONFIG_SYS_NUM_FM1_10GEC 1
428 #define CONFIG_NUM_DDR_CONTROLLERS 2
429 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
430 #define CONFIG_SYS_FSL_TBCLK_DIV 32
431 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
432 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
433 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
434 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
435 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
436 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
437 #define CONFIG_SYS_FSL_ERRATUM_USB14
438 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
439 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
440 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
441 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
442 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
443 #define CONFIG_SYS_FSL_ERRATUM_A004510
444 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
445 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
446 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
448 #elif defined(CONFIG_PPC_P5040)
449 #define CONFIG_SYS_PPC64
450 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
451 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
452 #define CONFIG_MAX_CPUS 4
453 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
454 #define CONFIG_SYS_FSL_NUM_LAWS 32
455 #define CONFIG_SYS_FSL_SEC_COMPAT 4
456 #define CONFIG_SYS_NUM_FMAN 2
457 #define CONFIG_SYS_NUM_FM1_DTSEC 5
458 #define CONFIG_SYS_NUM_FM1_10GEC 1
459 #define CONFIG_SYS_NUM_FM2_DTSEC 5
460 #define CONFIG_SYS_NUM_FM2_10GEC 1
461 #define CONFIG_NUM_DDR_CONTROLLERS 2
462 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
463 #define CONFIG_SYS_FSL_TBCLK_DIV 16
464 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
465 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
466 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
467 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
468 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
469 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
470 #define CONFIG_SYS_FSL_ERRATUM_USB14
471 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
472 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
473 #define CONFIG_SYS_FSL_ERRATUM_A004699
474 #define CONFIG_SYS_FSL_ERRATUM_A004510
475 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
476 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
478 #elif defined(CONFIG_BSC9131)
479 #define CONFIG_MAX_CPUS 1
480 #define CONFIG_FSL_SDHC_V2_3
481 #define CONFIG_SYS_FSL_NUM_LAWS 12
482 #define CONFIG_TSECV2
483 #define CONFIG_SYS_FSL_SEC_COMPAT 4
484 #define CONFIG_NUM_DDR_CONTROLLERS 1
485 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
486 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
487 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
488 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
489 #define CONFIG_NAND_FSL_IFC
490 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
492 #elif defined(CONFIG_BSC9132)
493 #define CONFIG_MAX_CPUS 2
494 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
495 #define CONFIG_FSL_SDHC_V2_3
496 #define CONFIG_SYS_FSL_NUM_LAWS 12
497 #define CONFIG_TSECV2
498 #define CONFIG_SYS_FSL_SEC_COMPAT 4
499 #define CONFIG_NUM_DDR_CONTROLLERS 2
500 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
501 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
502 #define CONFIG_NAND_FSL_IFC
503 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
504 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
505 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
507 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
509 #define CONFIG_SYS_PPC64 /* 64-bit core */
510 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
511 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
512 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
513 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
514 #ifdef CONFIG_PPC_T4240
515 #define CONFIG_MAX_CPUS 12
516 #define CONFIG_SYS_NUM_FM1_DTSEC 8
517 #define CONFIG_SYS_NUM_FM1_10GEC 2
518 #define CONFIG_SYS_NUM_FM2_DTSEC 8
519 #define CONFIG_SYS_NUM_FM2_10GEC 2
520 #define CONFIG_NUM_DDR_CONTROLLERS 3
522 #define CONFIG_MAX_CPUS 8
523 #define CONFIG_SYS_NUM_FM1_DTSEC 7
524 #define CONFIG_SYS_NUM_FM1_10GEC 1
525 #define CONFIG_SYS_NUM_FM2_DTSEC 7
526 #define CONFIG_SYS_NUM_FM2_10GEC 1
527 #define CONFIG_NUM_DDR_CONTROLLERS 2
529 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
530 #define CONFIG_SYS_FSL_NUM_LAWS 32
531 #define CONFIG_SYS_FSL_SRDS_3
532 #define CONFIG_SYS_FSL_SRDS_4
533 #define CONFIG_SYS_FSL_SEC_COMPAT 4
534 #define CONFIG_SYS_NUM_FMAN 2
535 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
536 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
537 #define CONFIG_SYS_FMAN_V3
538 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
539 #define CONFIG_SYS_FSL_TBCLK_DIV 16
540 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
541 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
542 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
543 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
544 #define CONFIG_SYS_FSL_SRIO_LIODN
545 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
546 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
547 #define CONFIG_SYS_FSL_ERRATUM_A004468
548 #define CONFIG_SYS_FSL_ERRATUM_A_004934
549 #define CONFIG_SYS_FSL_ERRATUM_A005871
550 #define CONFIG_SYS_FSL_ERRATUM_A006593
551 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
552 #define CONFIG_SYS_FSL_PCI_VER_3_X
554 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
556 #define CONFIG_SYS_PPC64 /* 64-bit core */
557 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
558 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
559 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
560 #define CONFIG_SYS_FSL_NUM_LAWS 32
561 #define CONFIG_SYS_FSL_SEC_COMPAT 4
562 #define CONFIG_SYS_NUM_FMAN 1
563 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
564 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
565 #define CONFIG_SYS_FMAN_V3
566 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
567 #define CONFIG_SYS_FSL_TBCLK_DIV 16
568 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
569 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
570 #define CONFIG_SYS_FSL_ERRATUM_A_004934
571 #define CONFIG_SYS_FSL_ERRATUM_A005871
572 #define CONFIG_SYS_FSL_ERRATUM_A006593
573 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
575 #ifdef CONFIG_PPC_B4860
576 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
577 #define CONFIG_MAX_CPUS 4
578 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
579 #define CONFIG_SYS_NUM_FM1_DTSEC 6
580 #define CONFIG_SYS_NUM_FM1_10GEC 2
581 #define CONFIG_NUM_DDR_CONTROLLERS 2
582 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
583 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
584 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
585 #define CONFIG_SYS_FSL_SRIO_LIODN
587 #define CONFIG_MAX_CPUS 2
588 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
589 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
590 #define CONFIG_SYS_NUM_FM1_DTSEC 4
591 #define CONFIG_SYS_NUM_FM1_10GEC 0
592 #define CONFIG_NUM_DDR_CONTROLLERS 1
595 #elif defined(CONFIG_PPC_T1040)
597 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
598 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
599 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
600 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
601 #define CONFIG_MAX_CPUS 4
602 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
603 #define CONFIG_SYS_FSL_NUM_LAWS 16
604 #define CONFIG_SYS_FSL_SEC_COMPAT 4
605 #define CONFIG_SYS_NUM_FMAN 1
606 #define CONFIG_SYS_NUM_FM1_DTSEC 5
607 #define CONFIG_NUM_DDR_CONTROLLERS 1
608 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
609 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
610 #define CONFIG_SYS_FMAN_V3
611 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
612 #define CONFIG_SYS_FSL_TBCLK_DIV 32
613 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
614 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
615 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
616 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
617 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
618 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
619 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
620 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
623 #error Processor type not defined for this platform
626 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
627 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
631 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
633 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
636 #endif /* _ASM_MPC85xx_CONFIG_H_ */