2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
9 #ifndef FSL_DDR_MEMCTL_H
10 #define FSL_DDR_MEMCTL_H
13 * Pick a basic DDR Technology.
17 #define SDRAM_TYPE_DDR1 2
18 #define SDRAM_TYPE_DDR2 3
19 #define SDRAM_TYPE_LPDDR1 6
20 #define SDRAM_TYPE_DDR3 7
22 #define DDR_BL4 4 /* burst length 4 */
23 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
24 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
25 #define DDR_BL8 8 /* burst length 8 */
27 #define DDR3_RTT_OFF 0
28 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
29 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
30 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
31 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
32 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
34 #define DDR2_RTT_OFF 0
35 #define DDR2_RTT_75_OHM 1
36 #define DDR2_RTT_150_OHM 2
37 #define DDR2_RTT_50_OHM 3
39 #if defined(CONFIG_FSL_DDR1)
40 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
41 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
42 #ifndef CONFIG_FSL_SDRAM_TYPE
43 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
45 #elif defined(CONFIG_FSL_DDR2)
46 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
47 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
48 #ifndef CONFIG_FSL_SDRAM_TYPE
49 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
51 #elif defined(CONFIG_FSL_DDR3)
52 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
53 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
54 #ifndef CONFIG_FSL_SDRAM_TYPE
55 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
57 #endif /* #if defined(CONFIG_FSL_DDR1) */
59 #define FSL_DDR_ODT_NEVER 0x0
60 #define FSL_DDR_ODT_CS 0x1
61 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
62 #define FSL_DDR_ODT_OTHER_DIMM 0x3
63 #define FSL_DDR_ODT_ALL 0x4
64 #define FSL_DDR_ODT_SAME_DIMM 0x5
65 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
66 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
68 /* define bank(chip select) interleaving mode */
69 #define FSL_DDR_CS0_CS1 0x40
70 #define FSL_DDR_CS2_CS3 0x20
71 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
72 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
74 /* define memory controller interleaving mode */
75 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
76 #define FSL_DDR_PAGE_INTERLEAVING 0x1
77 #define FSL_DDR_BANK_INTERLEAVING 0x2
78 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
80 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
82 #define SDRAM_CFG_MEM_EN 0x80000000
83 #define SDRAM_CFG_SREN 0x40000000
84 #define SDRAM_CFG_ECC_EN 0x20000000
85 #define SDRAM_CFG_RD_EN 0x10000000
86 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
87 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
88 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
89 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
90 #define SDRAM_CFG_DYN_PWR 0x00200000
91 #define SDRAM_CFG_DBW_MASK 0x00180000
92 #define SDRAM_CFG_32_BE 0x00080000
93 #define SDRAM_CFG_16_BE 0x00100000
94 #define SDRAM_CFG_8_BE 0x00040000
95 #define SDRAM_CFG_NCAP 0x00020000
96 #define SDRAM_CFG_2T_EN 0x00008000
97 #define SDRAM_CFG_BI 0x00000001
99 #define SDRAM_CFG2_D_INIT 0x00000010
100 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
101 #define SDRAM_CFG2_ODT_NEVER 0
102 #define SDRAM_CFG2_ODT_ONLY_WRITE 1
103 #define SDRAM_CFG2_ODT_ONLY_READ 2
104 #define SDRAM_CFG2_ODT_ALWAYS 3
106 #define TIMING_CFG_2_CPO_MASK 0x0F800000
108 #if defined(CONFIG_P4080)
109 #define RD_TO_PRE_MASK 0xf
110 #define RD_TO_PRE_SHIFT 13
111 #define WR_DATA_DELAY_MASK 0xf
112 #define WR_DATA_DELAY_SHIFT 9
114 #define RD_TO_PRE_MASK 0x7
115 #define RD_TO_PRE_SHIFT 13
116 #define WR_DATA_DELAY_MASK 0x7
117 #define WR_DATA_DELAY_SHIFT 10
121 #define MD_CNTL_MD_EN 0x80000000
122 #define MD_CNTL_CS_SEL_CS0 0x00000000
123 #define MD_CNTL_CS_SEL_CS1 0x10000000
124 #define MD_CNTL_CS_SEL_CS2 0x20000000
125 #define MD_CNTL_CS_SEL_CS3 0x30000000
126 #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
127 #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
128 #define MD_CNTL_MD_SEL_MR 0x00000000
129 #define MD_CNTL_MD_SEL_EMR 0x01000000
130 #define MD_CNTL_MD_SEL_EMR2 0x02000000
131 #define MD_CNTL_MD_SEL_EMR3 0x03000000
132 #define MD_CNTL_SET_REF 0x00800000
133 #define MD_CNTL_SET_PRE 0x00400000
134 #define MD_CNTL_CKE_CNTL_LOW 0x00100000
135 #define MD_CNTL_CKE_CNTL_HIGH 0x00200000
136 #define MD_CNTL_WRCW 0x00080000
137 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
140 #define DDR_CDR1_DHC_EN 0x80000000
142 /* Record of register values computed */
143 typedef struct fsl_ddr_cfg_regs_s {
147 unsigned int config_2;
148 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
149 unsigned int timing_cfg_3;
150 unsigned int timing_cfg_0;
151 unsigned int timing_cfg_1;
152 unsigned int timing_cfg_2;
153 unsigned int ddr_sdram_cfg;
154 unsigned int ddr_sdram_cfg_2;
155 unsigned int ddr_sdram_mode;
156 unsigned int ddr_sdram_mode_2;
157 unsigned int ddr_sdram_mode_3;
158 unsigned int ddr_sdram_mode_4;
159 unsigned int ddr_sdram_mode_5;
160 unsigned int ddr_sdram_mode_6;
161 unsigned int ddr_sdram_mode_7;
162 unsigned int ddr_sdram_mode_8;
163 unsigned int ddr_sdram_md_cntl;
164 unsigned int ddr_sdram_interval;
165 unsigned int ddr_data_init;
166 unsigned int ddr_sdram_clk_cntl;
167 unsigned int ddr_init_addr;
168 unsigned int ddr_init_ext_addr;
169 unsigned int timing_cfg_4;
170 unsigned int timing_cfg_5;
171 unsigned int ddr_zq_cntl;
172 unsigned int ddr_wrlvl_cntl;
173 unsigned int ddr_sr_cntr;
174 unsigned int ddr_sdram_rcw_1;
175 unsigned int ddr_sdram_rcw_2;
176 unsigned int ddr_eor;
177 unsigned int ddr_cdr1;
178 unsigned int ddr_cdr2;
179 unsigned int err_disable;
180 unsigned int err_int_en;
181 unsigned int debug[32];
182 } fsl_ddr_cfg_regs_t;
184 typedef struct memctl_options_partial_s {
185 unsigned int all_DIMMs_ECC_capable;
186 unsigned int all_DIMMs_tCKmax_ps;
187 unsigned int all_DIMMs_burst_lengths_bitmask;
188 unsigned int all_DIMMs_registered;
189 unsigned int all_DIMMs_unbuffered;
190 /* unsigned int lowest_common_SPD_caslat; */
191 unsigned int all_DIMMs_minimum_tRCD_ps;
192 } memctl_options_partial_t;
194 #define DDR_DATA_BUS_WIDTH_64 0
195 #define DDR_DATA_BUS_WIDTH_32 1
196 #define DDR_DATA_BUS_WIDTH_16 2
198 * Generalized parameters for memory controller configuration,
199 * might be a little specific to the FSL memory controller
201 typedef struct memctl_options_s {
203 * Memory organization parameters
205 * if DIMM is present in the system
206 * where DIMMs are with respect to chip select
207 * where chip selects are with respect to memory boundaries
209 unsigned int registered_dimm_en; /* use registered DIMM support */
211 /* Options local to a Chip Select */
212 struct cs_local_opts_s {
213 unsigned int auto_precharge;
214 unsigned int odt_rd_cfg;
215 unsigned int odt_wr_cfg;
216 unsigned int odt_rtt_norm;
217 unsigned int odt_rtt_wr;
218 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
220 /* Special configurations for chip select */
221 unsigned int memctl_interleaving;
222 unsigned int memctl_interleaving_mode;
223 unsigned int ba_intlv_ctl;
224 unsigned int addr_hash;
226 /* Operational mode parameters */
227 unsigned int ECC_mode; /* Use ECC? */
228 /* Initialize ECC using memory controller? */
229 unsigned int ECC_init_using_memctl;
230 unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
231 /* SREN - self-refresh during sleep */
232 unsigned int self_refresh_in_sleep;
233 unsigned int dynamic_power; /* DYN_PWR */
234 /* memory data width to use (16-bit, 32-bit, 64-bit) */
235 unsigned int data_bus_width;
236 unsigned int burst_length; /* BL4, OTF and BL8 */
237 /* On-The-Fly Burst Chop enable */
238 unsigned int OTF_burst_chop_en;
239 /* mirrior DIMMs for DDR3 */
240 unsigned int mirrored_dimm;
241 unsigned int quad_rank_present;
242 unsigned int ap_en; /* address parity enable for RDIMM */
244 /* Global Timing Parameters */
245 unsigned int cas_latency_override;
246 unsigned int cas_latency_override_value;
247 unsigned int use_derated_caslat;
248 unsigned int additive_latency_override;
249 unsigned int additive_latency_override_value;
251 unsigned int clk_adjust; /* */
252 unsigned int cpo_override;
253 unsigned int write_data_delay; /* DQS adjust */
255 unsigned int wrlvl_override;
256 unsigned int wrlvl_sample; /* Write leveling */
257 unsigned int wrlvl_start;
259 unsigned int half_strength_driver_enable;
260 unsigned int twoT_en;
261 unsigned int threeT_en;
262 unsigned int bstopre;
263 unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
264 unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
267 unsigned int rtt_override; /* rtt_override enable */
268 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
269 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
271 /* Automatic self refresh */
272 unsigned int auto_self_refresh_en;
277 unsigned int wrlvl_en;
278 /* RCW override for RDIMM */
279 unsigned int rcw_override;
282 /* control register 1 */
283 unsigned int ddr_cdr1;
285 unsigned int trwt_override;
286 unsigned int trwt; /* read-to-write turnaround */
289 extern phys_size_t fsl_ddr_sdram(void);
290 extern phys_size_t fsl_ddr_sdram_size(void);
291 extern int fsl_use_spd(void);
292 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
293 unsigned int ctrl_num);
296 * The 85xx boards have a common prototype for fixed_sdram so put the
299 #ifdef CONFIG_MPC85xx
300 extern phys_size_t fixed_sdram(void);
303 #if defined(CONFIG_DDR_ECC)
304 extern void ddr_enable_ecc(unsigned int dram_size);
308 typedef struct fixed_ddr_parm{
311 fsl_ddr_cfg_regs_t *ddr_settings;