2 * Copyright 2009 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 * provides masks and opcode images for use by code generation, emulation
10 * and for instructions that older assemblers might not know about
12 #ifndef _ASM_POWERPC_PPC_OPCODE_H
13 #define _ASM_POWERPC_PPC_OPCODE_H
15 #include <linux/stringify.h>
16 #include <asm/asm-compat.h>
61 #define __REGA0_R10 10
62 #define __REGA0_R11 11
63 #define __REGA0_R12 12
64 #define __REGA0_R13 13
65 #define __REGA0_R14 14
66 #define __REGA0_R15 15
67 #define __REGA0_R16 16
68 #define __REGA0_R17 17
69 #define __REGA0_R18 18
70 #define __REGA0_R19 19
71 #define __REGA0_R20 20
72 #define __REGA0_R21 21
73 #define __REGA0_R22 22
74 #define __REGA0_R23 23
75 #define __REGA0_R24 24
76 #define __REGA0_R25 25
77 #define __REGA0_R26 26
78 #define __REGA0_R27 27
79 #define __REGA0_R28 28
80 #define __REGA0_R29 29
81 #define __REGA0_R30 30
82 #define __REGA0_R31 31
84 /* sorted alphabetically */
85 #define PPC_INST_DCBA 0x7c0005ec
86 #define PPC_INST_DCBA_MASK 0xfc0007fe
87 #define PPC_INST_DCBAL 0x7c2005ec
88 #define PPC_INST_DCBZL 0x7c2007ec
89 #define PPC_INST_ICBT 0x7c00002c
90 #define PPC_INST_ISEL 0x7c00001e
91 #define PPC_INST_ISEL_MASK 0xfc00003e
92 #define PPC_INST_LDARX 0x7c0000a8
93 #define PPC_INST_LSWI 0x7c0004aa
94 #define PPC_INST_LSWX 0x7c00042a
95 #define PPC_INST_LWARX 0x7c000028
96 #define PPC_INST_LWSYNC 0x7c2004ac
97 #define PPC_INST_LXVD2X 0x7c000698
98 #define PPC_INST_MCRXR 0x7c000400
99 #define PPC_INST_MCRXR_MASK 0xfc0007fe
100 #define PPC_INST_MFSPR_PVR 0x7c1f42a6
101 #define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
102 #define PPC_INST_MSGSND 0x7c00019c
103 #define PPC_INST_MSGSNDP 0x7c00011c
104 #define PPC_INST_NOP 0x60000000
105 #define PPC_INST_POPCNTB 0x7c0000f4
106 #define PPC_INST_POPCNTB_MASK 0xfc0007fe
107 #define PPC_INST_POPCNTD 0x7c0003f4
108 #define PPC_INST_POPCNTW 0x7c0002f4
109 #define PPC_INST_RFCI 0x4c000066
110 #define PPC_INST_RFDI 0x4c00004e
111 #define PPC_INST_RFMCI 0x4c00004c
112 #define PPC_INST_MFSPR_DSCR 0x7c1102a6
113 #define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
114 #define PPC_INST_MTSPR_DSCR 0x7c1103a6
115 #define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
116 #define PPC_INST_SLBFEE 0x7c0007a7
118 #define PPC_INST_STRING 0x7c00042a
119 #define PPC_INST_STRING_MASK 0xfc0007fe
120 #define PPC_INST_STRING_GEN_MASK 0xfc00067e
122 #define PPC_INST_STSWI 0x7c0005aa
123 #define PPC_INST_STSWX 0x7c00052a
124 #define PPC_INST_STXVD2X 0x7c000798
125 #define PPC_INST_TLBIE 0x7c000264
126 #define PPC_INST_TLBILX 0x7c000024
127 #define PPC_INST_WAIT 0x7c00007c
128 #define PPC_INST_TLBIVAX 0x7c000624
129 #define PPC_INST_TLBSRX_DOT 0x7c0006a5
130 #define PPC_INST_XXLOR 0xf0000510
131 #define PPC_INST_XVCPSGNDP 0xf0000780
132 #define PPC_INST_TRECHKPT 0x7c0007dd
133 #define PPC_INST_TRECLAIM 0x7c00075d
134 #define PPC_INST_TABORT 0x7c00071d
136 #define PPC_INST_NAP 0x4c000364
137 #define PPC_INST_SLEEP 0x4c0003a4
139 /* A2 specific instructions */
140 #define PPC_INST_ERATWE 0x7c0001a6
141 #define PPC_INST_ERATRE 0x7c000166
142 #define PPC_INST_ERATILX 0x7c000066
143 #define PPC_INST_ERATIVAX 0x7c000666
144 #define PPC_INST_ERATSX 0x7c000126
145 #define PPC_INST_ERATSX_DOT 0x7c000127
147 /* Misc instructions for BPF compiler */
148 #define PPC_INST_LD 0xe8000000
149 #define PPC_INST_LHZ 0xa0000000
150 #define PPC_INST_LWZ 0x80000000
151 #define PPC_INST_STD 0xf8000000
152 #define PPC_INST_STDU 0xf8000001
153 #define PPC_INST_MFLR 0x7c0802a6
154 #define PPC_INST_MTLR 0x7c0803a6
155 #define PPC_INST_CMPWI 0x2c000000
156 #define PPC_INST_CMPDI 0x2c200000
157 #define PPC_INST_CMPLW 0x7c000040
158 #define PPC_INST_CMPLWI 0x28000000
159 #define PPC_INST_ADDI 0x38000000
160 #define PPC_INST_ADDIS 0x3c000000
161 #define PPC_INST_ADD 0x7c000214
162 #define PPC_INST_SUB 0x7c000050
163 #define PPC_INST_BLR 0x4e800020
164 #define PPC_INST_BLRL 0x4e800021
165 #define PPC_INST_MULLW 0x7c0001d6
166 #define PPC_INST_MULHWU 0x7c000016
167 #define PPC_INST_MULLI 0x1c000000
168 #define PPC_INST_DIVWU 0x7c0003d6
169 #define PPC_INST_RLWINM 0x54000000
170 #define PPC_INST_RLDICR 0x78000004
171 #define PPC_INST_SLW 0x7c000030
172 #define PPC_INST_SRW 0x7c000430
173 #define PPC_INST_AND 0x7c000038
174 #define PPC_INST_ANDDOT 0x7c000039
175 #define PPC_INST_OR 0x7c000378
176 #define PPC_INST_XOR 0x7c000278
177 #define PPC_INST_ANDI 0x70000000
178 #define PPC_INST_ORI 0x60000000
179 #define PPC_INST_ORIS 0x64000000
180 #define PPC_INST_XORI 0x68000000
181 #define PPC_INST_XORIS 0x6c000000
182 #define PPC_INST_NEG 0x7c0000d0
183 #define PPC_INST_BRANCH 0x48000000
184 #define PPC_INST_BRANCH_COND 0x40800000
185 #define PPC_INST_LBZCIX 0x7c0006aa
186 #define PPC_INST_STBCIX 0x7c0007aa
188 /* macros to insert fields into opcodes */
189 #define ___PPC_RA(a) (((a) & 0x1f) << 16)
190 #define ___PPC_RB(b) (((b) & 0x1f) << 11)
191 #define ___PPC_RS(s) (((s) & 0x1f) << 21)
192 #define ___PPC_RT(t) ___PPC_RS(t)
193 #define __PPC_RA(a) ___PPC_RA(__REG_##a)
194 #define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
195 #define __PPC_RB(b) ___PPC_RB(__REG_##b)
196 #define __PPC_RS(s) ___PPC_RS(__REG_##s)
197 #define __PPC_RT(t) ___PPC_RT(__REG_##t)
198 #define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
199 #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
200 #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
201 #define __PPC_XT(s) __PPC_XS(s)
202 #define __PPC_T_TLB(t) (((t) & 0x3) << 21)
203 #define __PPC_WC(w) (((w) & 0x3) << 21)
204 #define __PPC_WS(w) (((w) & 0x1f) << 11)
205 #define __PPC_SH(s) __PPC_WS(s)
206 #define __PPC_MB(s) (((s) & 0x1f) << 6)
207 #define __PPC_ME(s) (((s) & 0x1f) << 1)
208 #define __PPC_BI(s) (((s) & 0x1f) << 16)
209 #define __PPC_CT(t) (((t) & 0x0f) << 21)
212 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
213 * larx with EH set as an illegal instruction.
216 #define __PPC_EH(eh) (((eh) & 0x1) << 0)
218 #define __PPC_EH(eh) 0
221 /* Deal with instructions that older assemblers aren't aware of */
222 #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
223 __PPC_RA(a) | __PPC_RB(b))
224 #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
225 __PPC_RA(a) | __PPC_RB(b))
226 #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
227 ___PPC_RT(t) | ___PPC_RA(a) | \
228 ___PPC_RB(b) | __PPC_EH(eh))
229 #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
230 ___PPC_RT(t) | ___PPC_RA(a) | \
231 ___PPC_RB(b) | __PPC_EH(eh))
232 #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
234 #define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \
236 #define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
237 __PPC_RA(a) | __PPC_RS(s))
238 #define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
239 __PPC_RA(a) | __PPC_RS(s))
240 #define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
241 __PPC_RA(a) | __PPC_RS(s))
242 #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
243 #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
244 #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
245 #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
246 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
247 #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
248 #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
249 #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
250 #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
252 #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
253 ___PPC_RB(a) | ___PPC_RS(lp))
254 #define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
255 __PPC_RA0(a) | __PPC_RB(b))
256 #define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
257 __PPC_RA0(a) | __PPC_RB(b))
259 #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
260 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
261 #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
262 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
263 #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
264 __PPC_T_TLB(t) | __PPC_RA0(a) | \
266 #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
267 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
268 #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
269 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
270 #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
271 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
272 #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
273 __PPC_RT(t) | __PPC_RB(b))
274 #define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
275 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
276 /* PASemi instructions */
277 #define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
278 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
279 #define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
280 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
283 * Define what the VSX XX1 form instructions will look like, then add
284 * the 128 bit load store instructions based on that.
286 #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
287 #define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
288 #define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
290 #define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
292 #define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
294 #define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
295 VSX_XX3((t), (a), (b))))
297 #define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
298 #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
300 /* Transactional memory instructions */
301 #define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT)
302 #define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \
304 #define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \
307 #endif /* _ASM_POWERPC_PPC_OPCODE_H */