2 * Copyright 2017, Nicholas Piggin, IBM Corporation
3 * Licensed under GPLv2.
6 #define pr_fmt(fmt) "dt-cpu-ftrs: " fmt
8 #include <linux/export.h>
9 #include <linux/init.h>
10 #include <linux/jump_label.h>
11 #include <linux/libfdt.h>
12 #include <linux/memblock.h>
13 #include <linux/printk.h>
14 #include <linux/sched.h>
15 #include <linux/string.h>
16 #include <linux/threads.h>
18 #include <asm/cputable.h>
19 #include <asm/dt_cpu_ftrs.h>
21 #include <asm/oprofile_impl.h>
23 #include <asm/setup.h>
26 /* Device-tree visible constants follow */
27 #define ISA_V2_07B 2070
28 #define ISA_V3_0B 3000
30 #define USABLE_PR (1U << 0)
31 #define USABLE_OS (1U << 1)
32 #define USABLE_HV (1U << 2)
34 #define HV_SUPPORT_HFSCR (1U << 0)
35 #define OS_SUPPORT_FSCR (1U << 0)
37 /* For parsing, we define all bits set as "NONE" case */
38 #define HV_SUPPORT_NONE 0xffffffffU
39 #define OS_SUPPORT_NONE 0xffffffffU
41 struct dt_cpu_feature {
44 uint32_t usable_privilege;
47 uint32_t hfscr_bit_nr;
49 uint32_t hwcap_bit_nr;
56 #define CPU_FTRS_BASE \
59 CPU_FTR_FPU_UNAVAILABLE |\
60 CPU_FTR_NODSISRALIGN |\
62 CPU_FTR_COHERENT_ICACHE | \
63 CPU_FTR_STCX_CHECKS_ADDRESS |\
64 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
69 #define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8)
71 #define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \
72 PPC_FEATURE_ARCH_2_06 |\
73 PPC_FEATURE_ICACHE_SNOOP)
74 #define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \
80 extern void __flush_tlb_power8(unsigned int action);
81 extern void __flush_tlb_power9(unsigned int action);
82 extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
83 extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
93 static void (*init_pmu_registers)(void);
95 static void cpufeatures_flush_tlb(void)
98 * This is a temporary measure to keep equivalent TLB flush as the
99 * cputable based setup code.
101 switch (PVR_VER(mfspr(SPRN_PVR))) {
105 __flush_tlb_power8(POWER8_TLB_SETS);
108 __flush_tlb_power9(POWER9_TLB_SETS_HASH);
111 pr_err("unknown CPU version for boot TLB flush\n");
116 static void __restore_cpu_cpufeatures(void)
119 * LPCR is restored by the power on engine already. It can be changed
120 * after early init e.g., by radix enable, and we have no unified API
121 * for saving and restoring such SPRs.
123 * This ->restore hook should really be removed from idle and register
124 * restore moved directly into the idle restore code, because this code
125 * doesn't know how idle is implemented or what it needs restored here.
127 * The best we can do to accommodate secondary boot and idle restore
128 * for now is "or" LPCR with existing.
131 mtspr(SPRN_LPCR, system_registers.lpcr | mfspr(SPRN_LPCR));
134 mtspr(SPRN_HFSCR, system_registers.hfscr);
136 mtspr(SPRN_FSCR, system_registers.fscr);
138 if (init_pmu_registers)
139 init_pmu_registers();
141 cpufeatures_flush_tlb();
144 static char dt_cpu_name[64];
146 static struct cpu_spec __initdata base_cpu_spec = {
148 .cpu_features = CPU_FTRS_BASE,
149 .cpu_user_features = COMMON_USER_BASE,
150 .cpu_user_features2 = COMMON_USER2_BASE,
152 .icache_bsize = 32, /* minimum block size, fixed by */
153 .dcache_bsize = 32, /* cache info init. */
155 .pmc_type = PPC_PMC_DEFAULT,
156 .oprofile_cpu_type = NULL,
157 .oprofile_type = PPC_OPROFILE_INVALID,
159 .cpu_restore = __restore_cpu_cpufeatures,
161 .machine_check_early = NULL,
165 static void __init cpufeatures_setup_cpu(void)
167 set_cur_cpu_spec(&base_cpu_spec);
169 cur_cpu_spec->pvr_mask = -1;
170 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR);
172 /* Initialize the base environment -- clear FSCR/HFSCR. */
173 hv_mode = !!(mfmsr() & MSR_HV);
175 /* CPU_FTR_HVMODE is used early in PACA setup */
176 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
177 mtspr(SPRN_HFSCR, 0);
182 * LPCR does not get cleared, to match behaviour with secondaries
183 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this
184 * could clear LPCR too.
188 static int __init feat_try_enable_unknown(struct dt_cpu_feature *f)
190 if (f->hv_support == HV_SUPPORT_NONE) {
191 } else if (f->hv_support & HV_SUPPORT_HFSCR) {
192 u64 hfscr = mfspr(SPRN_HFSCR);
193 hfscr |= 1UL << f->hfscr_bit_nr;
194 mtspr(SPRN_HFSCR, hfscr);
196 /* Does not have a known recipe */
200 if (f->os_support == OS_SUPPORT_NONE) {
201 } else if (f->os_support & OS_SUPPORT_FSCR) {
202 u64 fscr = mfspr(SPRN_FSCR);
203 fscr |= 1UL << f->fscr_bit_nr;
204 mtspr(SPRN_FSCR, fscr);
206 /* Does not have a known recipe */
210 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
211 uint32_t word = f->hwcap_bit_nr / 32;
212 uint32_t bit = f->hwcap_bit_nr % 32;
215 cur_cpu_spec->cpu_user_features |= 1U << bit;
217 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
219 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name);
225 static int __init feat_enable(struct dt_cpu_feature *f)
227 if (f->hv_support != HV_SUPPORT_NONE) {
228 if (f->hfscr_bit_nr != -1) {
229 u64 hfscr = mfspr(SPRN_HFSCR);
230 hfscr |= 1UL << f->hfscr_bit_nr;
231 mtspr(SPRN_HFSCR, hfscr);
235 if (f->os_support != OS_SUPPORT_NONE) {
236 if (f->fscr_bit_nr != -1) {
237 u64 fscr = mfspr(SPRN_FSCR);
238 fscr |= 1UL << f->fscr_bit_nr;
239 mtspr(SPRN_FSCR, fscr);
243 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
244 uint32_t word = f->hwcap_bit_nr / 32;
245 uint32_t bit = f->hwcap_bit_nr % 32;
248 cur_cpu_spec->cpu_user_features |= 1U << bit;
250 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
252 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name);
258 static int __init feat_disable(struct dt_cpu_feature *f)
263 static int __init feat_enable_hv(struct dt_cpu_feature *f)
268 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n");
274 lpcr = mfspr(SPRN_LPCR);
275 lpcr &= ~LPCR_LPES0; /* HV external interrupts */
276 mtspr(SPRN_LPCR, lpcr);
278 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
283 static int __init feat_enable_le(struct dt_cpu_feature *f)
285 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE;
289 static int __init feat_enable_smt(struct dt_cpu_feature *f)
291 cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
292 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT;
296 static int __init feat_enable_idle_nap(struct dt_cpu_feature *f)
300 /* Set PECE wakeup modes for ISA 207 */
301 lpcr = mfspr(SPRN_LPCR);
305 mtspr(SPRN_LPCR, lpcr);
310 static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
312 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN;
317 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
321 /* Set PECE wakeup modes for ISAv3.0B */
322 lpcr = mfspr(SPRN_LPCR);
326 mtspr(SPRN_LPCR, lpcr);
331 static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f)
335 lpcr = mfspr(SPRN_LPCR);
341 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */
342 mtspr(SPRN_LPCR, lpcr);
344 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
345 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
350 static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
354 lpcr = mfspr(SPRN_LPCR);
356 mtspr(SPRN_LPCR, lpcr);
358 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
359 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
365 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f)
367 #ifdef CONFIG_PPC_RADIX_MMU
368 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
369 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
370 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
377 static int __init feat_enable_dscr(struct dt_cpu_feature *f)
383 lpcr = mfspr(SPRN_LPCR);
385 lpcr |= (4UL << LPCR_DPFD_SH);
386 mtspr(SPRN_LPCR, lpcr);
391 static void hfscr_pmu_enable(void)
393 u64 hfscr = mfspr(SPRN_HFSCR);
394 hfscr |= PPC_BIT(60);
395 mtspr(SPRN_HFSCR, hfscr);
398 static void init_pmu_power8(void)
401 mtspr(SPRN_MMCRC, 0);
402 mtspr(SPRN_MMCRH, 0);
405 mtspr(SPRN_MMCRA, 0);
406 mtspr(SPRN_MMCR0, 0);
407 mtspr(SPRN_MMCR1, 0);
408 mtspr(SPRN_MMCR2, 0);
409 mtspr(SPRN_MMCRS, 0);
412 static int __init feat_enable_mce_power8(struct dt_cpu_feature *f)
414 cur_cpu_spec->platform = "power8";
415 cur_cpu_spec->flush_tlb = __flush_tlb_power8;
416 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8;
421 static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f)
426 init_pmu_registers = init_pmu_power8;
428 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
429 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
430 if (pvr_version_is(PVR_POWER8E))
431 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG;
433 cur_cpu_spec->num_pmcs = 6;
434 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
435 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8";
440 static void init_pmu_power9(void)
443 mtspr(SPRN_MMCRC, 0);
445 mtspr(SPRN_MMCRA, 0);
446 mtspr(SPRN_MMCR0, 0);
447 mtspr(SPRN_MMCR1, 0);
448 mtspr(SPRN_MMCR2, 0);
451 static int __init feat_enable_mce_power9(struct dt_cpu_feature *f)
453 cur_cpu_spec->platform = "power9";
454 cur_cpu_spec->flush_tlb = __flush_tlb_power9;
455 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9;
460 static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f)
465 init_pmu_registers = init_pmu_power9;
467 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
468 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
470 cur_cpu_spec->num_pmcs = 6;
471 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
472 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9";
477 static int __init feat_enable_tm(struct dt_cpu_feature *f)
479 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
481 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC;
487 static int __init feat_enable_fp(struct dt_cpu_feature *f)
490 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE;
495 static int __init feat_enable_vector(struct dt_cpu_feature *f)
497 #ifdef CONFIG_ALTIVEC
499 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
500 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY;
501 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
508 static int __init feat_enable_vsx(struct dt_cpu_feature *f)
512 cur_cpu_spec->cpu_features |= CPU_FTR_VSX;
513 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX;
520 static int __init feat_enable_purr(struct dt_cpu_feature *f)
522 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR;
527 static int __init feat_enable_ebb(struct dt_cpu_feature *f)
530 * PPC_FEATURE2_EBB is enabled in PMU init code because it has
531 * historically been related to the PMU facility. This may have
532 * to be decoupled if EBB becomes more generic. For now, follow
533 * existing convention.
535 f->hwcap_bit_nr = -1;
541 static int __init feat_enable_dbell(struct dt_cpu_feature *f)
545 /* P9 has an HFSCR for privileged state */
548 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL;
550 lpcr = mfspr(SPRN_LPCR);
551 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */
552 mtspr(SPRN_LPCR, lpcr);
557 static int __init feat_enable_hvi(struct dt_cpu_feature *f)
562 * POWER9 XIVE interrupts including in OPAL XICS compatibility
563 * are always delivered as hypervisor virtualization interrupts (HVI)
566 * However LPES0 is not set here, in the chance that an EE does get
567 * delivered to the host somehow, the EE handler would not expect it
568 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could
569 * happen if there is a bug in interrupt controller code, or IC is
570 * misconfigured in systemsim.
573 lpcr = mfspr(SPRN_LPCR);
574 lpcr |= LPCR_HVICE; /* enable hvi interrupts */
575 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */
576 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */
577 mtspr(SPRN_LPCR, lpcr);
582 static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
584 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE;
589 struct dt_cpu_feature_match {
591 int (*enable)(struct dt_cpu_feature *f);
592 u64 cpu_ftr_bit_mask;
595 static struct dt_cpu_feature_match __initdata
596 dt_cpu_feature_match_table[] = {
597 {"hypervisor", feat_enable_hv, 0},
598 {"big-endian", feat_enable, 0},
599 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE},
600 {"smt", feat_enable_smt, 0},
601 {"interrupt-facilities", feat_enable, 0},
602 {"timer-facilities", feat_enable, 0},
603 {"timer-facilities-v3", feat_enable, 0},
604 {"debug-facilities", feat_enable, 0},
605 {"come-from-address-register", feat_enable, CPU_FTR_CFAR},
606 {"branch-tracing", feat_enable, 0},
607 {"floating-point", feat_enable_fp, 0},
608 {"vector", feat_enable_vector, 0},
609 {"vector-scalar", feat_enable_vsx, 0},
610 {"vector-scalar-v3", feat_enable, 0},
611 {"decimal-floating-point", feat_enable, 0},
612 {"decimal-integer", feat_enable, 0},
613 {"quadword-load-store", feat_enable, 0},
614 {"vector-crypto", feat_enable, 0},
615 {"mmu-hash", feat_enable_mmu_hash, 0},
616 {"mmu-radix", feat_enable_mmu_radix, 0},
617 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0},
618 {"virtual-page-class-key-protection", feat_enable, 0},
619 {"transactional-memory", feat_enable_tm, CPU_FTR_TM},
620 {"transactional-memory-v3", feat_enable_tm, 0},
621 {"idle-nap", feat_enable_idle_nap, 0},
622 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
623 {"idle-stop", feat_enable_idle_stop, 0},
624 {"machine-check-power8", feat_enable_mce_power8, 0},
625 {"performance-monitor-power8", feat_enable_pmu_power8, 0},
626 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR},
627 {"event-based-branch", feat_enable_ebb, 0},
628 {"target-address-register", feat_enable, 0},
629 {"branch-history-rolling-buffer", feat_enable, 0},
630 {"control-register", feat_enable, CPU_FTR_CTRL},
631 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},
632 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
633 {"processor-utilization-of-resources-register", feat_enable_purr, 0},
634 {"no-execute", feat_enable, 0},
635 {"strong-access-ordering", feat_enable, CPU_FTR_SAO},
636 {"cache-inhibited-large-page", feat_enable_large_ci, 0},
637 {"coprocessor-icswx", feat_enable, CPU_FTR_ICSWX},
638 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},
639 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR},
640 {"wait", feat_enable, 0},
641 {"atomic-memory-operations", feat_enable, 0},
642 {"branch-v3", feat_enable, 0},
643 {"copy-paste", feat_enable, 0},
644 {"decimal-floating-point-v3", feat_enable, 0},
645 {"decimal-integer-v3", feat_enable, 0},
646 {"fixed-point-v3", feat_enable, 0},
647 {"floating-point-v3", feat_enable, 0},
648 {"group-start-register", feat_enable, 0},
649 {"pc-relative-addressing", feat_enable, 0},
650 {"machine-check-power9", feat_enable_mce_power9, 0},
651 {"performance-monitor-power9", feat_enable_pmu_power9, 0},
652 {"event-based-branch-v3", feat_enable, 0},
653 {"random-number-generator", feat_enable, 0},
654 {"system-call-vectored", feat_disable, 0},
655 {"trace-interrupt-v3", feat_enable, 0},
656 {"vector-v3", feat_enable, 0},
657 {"vector-binary128", feat_enable, 0},
658 {"vector-binary16", feat_enable, 0},
659 {"wait-v3", feat_enable, 0},
662 static bool __initdata using_dt_cpu_ftrs;
663 static bool __initdata enable_unknown = true;
665 static int __init dt_cpu_ftrs_parse(char *str)
670 if (!strcmp(str, "off"))
671 using_dt_cpu_ftrs = false;
672 else if (!strcmp(str, "known"))
673 enable_unknown = false;
679 early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse);
681 static void __init cpufeatures_setup_start(u32 isa)
683 pr_info("setup for ISA %d\n", isa);
686 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
687 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
691 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
693 const struct dt_cpu_feature_match *m;
697 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) {
698 m = &dt_cpu_feature_match_table[i];
699 if (!strcmp(f->name, m->name)) {
704 pr_info("not enabling: %s (disabled or unsupported by kernel)\n",
710 if (!known && enable_unknown) {
711 if (!feat_try_enable_unknown(f)) {
712 pr_info("not enabling: %s (unknown and unsupported by kernel)\n",
718 if (m->cpu_ftr_bit_mask)
719 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask;
722 pr_debug("enabling: %s\n", f->name);
724 pr_debug("enabling: %s (unknown)\n", f->name);
729 static __init void cpufeatures_cpu_quirks(void)
731 int version = mfspr(SPRN_PVR);
734 * Not all quirks can be derived from the cpufeatures device tree.
736 if ((version & 0xffffff00) == 0x004e0100)
737 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1;
740 static void __init cpufeatures_setup_finished(void)
742 cpufeatures_cpu_quirks();
744 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) {
745 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n");
746 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
749 system_registers.lpcr = mfspr(SPRN_LPCR);
750 system_registers.hfscr = mfspr(SPRN_HFSCR);
751 system_registers.fscr = mfspr(SPRN_FSCR);
753 cpufeatures_flush_tlb();
755 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
756 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
759 static int __init disabled_on_cmdline(void)
761 unsigned long root, chosen;
764 root = of_get_flat_dt_root();
765 chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
766 if (chosen == -FDT_ERR_NOTFOUND)
769 p = of_get_flat_dt_prop(chosen, "bootargs", NULL);
773 if (strstr(p, "dt_cpu_ftrs=off"))
779 static int __init fdt_find_cpu_features(unsigned long node, const char *uname,
780 int depth, void *data)
782 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")
783 && of_get_flat_dt_prop(node, "isa", NULL))
789 bool __init dt_cpu_ftrs_in_use(void)
791 return using_dt_cpu_ftrs;
794 bool __init dt_cpu_ftrs_init(void *fdt)
796 using_dt_cpu_ftrs = false;
798 /* Setup and verify the FDT, if it fails we just bail */
799 if (!early_init_dt_verify(fdt))
802 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))
805 if (disabled_on_cmdline())
808 cpufeatures_setup_cpu();
810 using_dt_cpu_ftrs = true;
814 static int nr_dt_cpu_features;
815 static struct dt_cpu_feature *dt_cpu_features;
817 static int __init process_cpufeatures_node(unsigned long node,
818 const char *uname, int i)
821 struct dt_cpu_feature *f;
824 f = &dt_cpu_features[i];
825 memset(f, 0, sizeof(struct dt_cpu_feature));
831 prop = of_get_flat_dt_prop(node, "isa", &len);
833 pr_warn("%s: missing isa property\n", uname);
836 f->isa = be32_to_cpup(prop);
838 prop = of_get_flat_dt_prop(node, "usable-privilege", &len);
840 pr_warn("%s: missing usable-privilege property", uname);
843 f->usable_privilege = be32_to_cpup(prop);
845 prop = of_get_flat_dt_prop(node, "hv-support", &len);
847 f->hv_support = be32_to_cpup(prop);
849 f->hv_support = HV_SUPPORT_NONE;
851 prop = of_get_flat_dt_prop(node, "os-support", &len);
853 f->os_support = be32_to_cpup(prop);
855 f->os_support = OS_SUPPORT_NONE;
857 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len);
859 f->hfscr_bit_nr = be32_to_cpup(prop);
861 f->hfscr_bit_nr = -1;
862 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len);
864 f->fscr_bit_nr = be32_to_cpup(prop);
867 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len);
869 f->hwcap_bit_nr = be32_to_cpup(prop);
871 f->hwcap_bit_nr = -1;
873 if (f->usable_privilege & USABLE_HV) {
874 if (!(mfmsr() & MSR_HV)) {
875 pr_warn("%s: HV feature passed to guest\n", uname);
879 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) {
880 pr_warn("%s: unwanted hfscr_bit_nr\n", uname);
884 if (f->hv_support == HV_SUPPORT_HFSCR) {
885 if (f->hfscr_bit_nr == -1) {
886 pr_warn("%s: missing hfscr_bit_nr\n", uname);
891 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) {
892 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname);
897 if (f->usable_privilege & USABLE_OS) {
898 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) {
899 pr_warn("%s: unwanted fscr_bit_nr\n", uname);
903 if (f->os_support == OS_SUPPORT_FSCR) {
904 if (f->fscr_bit_nr == -1) {
905 pr_warn("%s: missing fscr_bit_nr\n", uname);
910 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) {
911 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname);
916 if (!(f->usable_privilege & USABLE_PR)) {
917 if (f->hwcap_bit_nr != -1) {
918 pr_warn("%s: unwanted hwcap_bit_nr\n", uname);
923 /* Do all the independent features in the first pass */
924 if (!of_get_flat_dt_prop(node, "dependencies", &len)) {
925 if (cpufeatures_process_feature(f))
934 static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f)
941 if (f->enabled || f->disabled)
944 prop = of_get_flat_dt_prop(f->node, "dependencies", &len);
946 pr_warn("%s: missing dependencies property", f->name);
950 nr_deps = len / sizeof(int);
952 for (i = 0; i < nr_deps; i++) {
953 unsigned long phandle = be32_to_cpu(prop[i]);
956 for (j = 0; j < nr_dt_cpu_features; j++) {
957 struct dt_cpu_feature *d = &dt_cpu_features[j];
959 if (of_get_flat_dt_phandle(d->node) == phandle) {
960 cpufeatures_deps_enable(d);
969 if (cpufeatures_process_feature(f))
975 static int __init scan_cpufeatures_subnodes(unsigned long node,
981 process_cpufeatures_node(node, uname, *count);
988 static int __init count_cpufeatures_subnodes(unsigned long node,
999 static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char
1000 *uname, int depth, void *data)
1006 /* We are scanning "ibm,powerpc-cpu-features" nodes only */
1007 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features"))
1010 prop = of_get_flat_dt_prop(node, "isa", NULL);
1012 /* We checked before, "can't happen" */
1015 isa = be32_to_cpup(prop);
1017 /* Count and allocate space for cpu features */
1018 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes,
1019 &nr_dt_cpu_features);
1020 dt_cpu_features = __va(
1021 memblock_alloc(sizeof(struct dt_cpu_feature)*
1022 nr_dt_cpu_features, PAGE_SIZE));
1024 cpufeatures_setup_start(isa);
1026 /* Scan nodes into dt_cpu_features and enable those without deps */
1028 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count);
1030 /* Recursive enable remaining features with dependencies */
1031 for (i = 0; i < nr_dt_cpu_features; i++) {
1032 struct dt_cpu_feature *f = &dt_cpu_features[i];
1034 cpufeatures_deps_enable(f);
1037 prop = of_get_flat_dt_prop(node, "display-name", NULL);
1038 if (prop && strlen((char *)prop) != 0) {
1039 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name));
1040 cur_cpu_spec->cpu_name = dt_cpu_name;
1043 cpufeatures_setup_finished();
1045 memblock_free(__pa(dt_cpu_features),
1046 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features);
1051 void __init dt_cpu_ftrs_scan(void)
1053 if (!using_dt_cpu_ftrs)
1056 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);