3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <asm/unistd.h>
24 #include <asm/processor.h>
27 #include <asm/thread_info.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
31 #include <asm/firmware.h>
33 #include <asm/ptrace.h>
34 #include <asm/irqflags.h>
35 #include <asm/hw_irq.h>
36 #include <asm/context_tracking.h>
38 #include <asm/ppc-opcode.h>
39 #include <asm/export.h>
46 .tc sys_call_table[TC],sys_call_table
48 /* This value is used to mark exception frames on the stack. */
50 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
55 .globl system_call_common
57 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
59 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
61 END_FTR_SECTION_IFSET(CPU_FTR_TM)
65 addi r1,r1,-INT_FRAME_SIZE
73 beq 2f /* if from kernel mode */
74 ACCOUNT_CPU_USER_ENTRY(r13, r10, r11)
93 * This clears CR0.SO (bit 28), which is the error indication on
94 * return from this system call.
96 rldimi r2,r11,28,(63-28)
103 addi r9,r1,STACK_FRAME_OVERHEAD
104 ld r11,exception_marker@toc(r2)
105 std r11,-16(r9) /* "regshere" marker */
106 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
109 /* if from user, see if there are any DTL entries to process */
110 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
111 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
112 addi r10,r10,LPPACA_DTLIDX
113 LDX_BE r10,0,r10 /* get log write index */
116 bl accumulate_stolen_time
120 addi r9,r1,STACK_FRAME_OVERHEAD
122 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
123 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
126 * A syscall should always be called with interrupts enabled
127 * so we just unconditionally hard-enable here. When some kind
128 * of irq tracing is used, we additionally check that condition
131 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
132 lbz r10,PACASOFTIRQEN(r13)
135 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
138 #ifdef CONFIG_PPC_BOOK3E
144 #endif /* CONFIG_PPC_BOOK3E */
146 /* We do need to set SOFTE in the stack frame or the return
147 * from interrupt will be painful
152 CURRENT_THREAD_INFO(r11, r1)
154 andi. r11,r10,_TIF_SYSCALL_DOTRACE
155 bne syscall_dotrace /* does not return */
156 cmpldi 0,r0,NR_syscalls
159 system_call: /* label this so stack traces look sane */
161 * Need to vector to 32 Bit or default sys_call_table here,
162 * based on caller's run-mode / personality.
164 ld r11,SYS_CALL_TABLE@toc(2)
165 andi. r10,r10,_TIF_32BIT
167 addi r11,r11,8 /* use 32-bit syscall entries */
176 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
178 bctrl /* Call handler */
182 CURRENT_THREAD_INFO(r12, r1)
185 #ifdef CONFIG_PPC_BOOK3S
186 /* No MSR:RI on BookE */
191 * Disable interrupts so current_thread_info()->flags can't change,
192 * and so that we don't get interrupted after loading SRR0/1.
194 #ifdef CONFIG_PPC_BOOK3E
198 * For performance reasons we clear RI the same time that we
199 * clear EE. We only need to clear RI just before we restore r13
200 * below, but batching it with EE saves us one expensive mtmsrd call.
201 * We have to be careful to restore RI if we branch anywhere from
202 * here (eg syscall_exit_work).
206 #endif /* CONFIG_PPC_BOOK3E */
210 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
211 bne- syscall_exit_work
215 #ifdef CONFIG_ALTIVEC
216 andis. r0,r8,MSR_VEC@h
219 2: addi r3,r1,STACK_FRAME_OVERHEAD
220 #ifdef CONFIG_PPC_BOOK3S
222 mtmsrd r10,1 /* Restore RI */
225 #ifdef CONFIG_PPC_BOOK3S
236 .Lsyscall_error_cont:
239 stdcx. r0,0,r1 /* to clear the reservation */
240 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
245 ACCOUNT_CPU_USER_EXIT(r13, r11, r12)
249 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
251 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
259 b . /* prevent speculative execution */
262 oris r5,r5,0x1000 /* Set SO bit in CR */
265 b .Lsyscall_error_cont
267 /* Traced system call support */
270 addi r3,r1,STACK_FRAME_OVERHEAD
271 bl do_syscall_trace_enter
274 * We use the return value of do_syscall_trace_enter() as the syscall
275 * number. If the syscall was rejected for any reason do_syscall_trace_enter()
276 * returns an invalid syscall number and the test below against
277 * NR_syscalls will fail.
281 /* Restore argument registers just clobbered and/or possibly changed. */
289 /* Repopulate r9 and r10 for the system_call path */
290 addi r9,r1,STACK_FRAME_OVERHEAD
291 CURRENT_THREAD_INFO(r10, r1)
294 cmpldi r0,NR_syscalls
297 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
306 #ifdef CONFIG_PPC_BOOK3S
308 mtmsrd r10,1 /* Restore RI */
310 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
311 If TIF_NOERROR is set, just save r3 as it is. */
313 andi. r0,r9,_TIF_RESTOREALL
317 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */
319 andi. r0,r9,_TIF_NOERROR
323 oris r5,r5,0x1000 /* Set SO bit in CR */
326 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
329 /* Clear per-syscall TIF flags if any are set. */
331 li r11,_TIF_PERSYSCALL_MASK
332 addi r12,r12,TI_FLAGS
337 subi r12,r12,TI_FLAGS
339 4: /* Anything else left to do? */
341 lis r3,INIT_PPR@highest /* Set thread.ppr = 3 */
342 ld r10,PACACURRENT(r13)
343 sldi r3,r3,32 /* bits 11-13 are used for ppr */
344 std r3,TASKTHREADPPR(r10)
345 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
347 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
348 beq ret_from_except_lite
350 /* Re-enable interrupts */
351 #ifdef CONFIG_PPC_BOOK3E
357 #endif /* CONFIG_PPC_BOOK3E */
360 addi r3,r1,STACK_FRAME_OVERHEAD
361 bl do_syscall_trace_leave
364 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
366 /* Firstly we need to enable TM in the kernel */
369 rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
372 /* tabort, this dooms the transaction, nothing else */
373 li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
377 * Return directly to userspace. We have corrupted user register state,
378 * but userspace will never see that register state. Execution will
379 * resume after the tbegin of the aborted transaction with the
380 * checkpointed register state.
389 b . /* prevent speculative execution */
392 /* Save non-volatile GPRs, if not already saved. */
404 * The sigsuspend and rt_sigsuspend system calls can call do_signal
405 * and thus put the process into the stopped state where we might
406 * want to examine its user state with ptrace. Therefore we need
407 * to save all the nonvolatile registers (r14 - r31) before calling
408 * the C code. Similarly, fork, vfork and clone need the full
409 * register state on the stack so that it can be copied to the child.
427 _GLOBAL(ppc32_swapcontext)
429 bl compat_sys_swapcontext
432 _GLOBAL(ppc64_swapcontext)
437 _GLOBAL(ppc_switch_endian)
442 _GLOBAL(ret_from_fork)
448 _GLOBAL(ret_from_kernel_thread)
453 #ifdef PPC64_ELF_ABI_v2
461 * This routine switches between two different tasks. The process
462 * state of one is saved on its kernel stack. Then the state
463 * of the other is restored from its kernel stack. The memory
464 * management hardware is updated to the second process's state.
465 * Finally, we can return to the second process, via ret_from_except.
466 * On entry, r3 points to the THREAD for the current task, r4
467 * points to the THREAD for the new task.
469 * Note: there are two ways to get to the "going out" portion
470 * of this code; either by coming in via the entry (_switch)
471 * or via "fork" which must set up an environment equivalent
472 * to the "_switch" path. If you change this you'll have to change
473 * the fork code also.
475 * The code which creates the new task context is in 'copy_thread'
476 * in arch/powerpc/kernel/process.c
482 stdu r1,-SWITCH_FRAME_SIZE(r1)
483 /* r3-r13 are caller saved -- Cort */
486 std r0,_NIP(r1) /* Return to switch caller */
489 std r1,KSP(r3) /* Set old stack pointer */
492 /* We need a sync somewhere here to make sure that if the
493 * previous task gets rescheduled on another CPU, it sees all
494 * stores it has performed on this one.
497 #endif /* CONFIG_SMP */
500 * If we optimise away the clear of the reservation in system
501 * calls because we know the CPU tracks the address of the
502 * reservation, then we need to clear it here to cover the
503 * case that the kernel context switch path has no larx
508 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
512 * A cp_abort (copy paste abort) here ensures that when context switching, a
513 * copy from one process can't leak into the paste of another.
516 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
518 #ifdef CONFIG_PPC_BOOK3S
519 /* Cancel all explict user streams as they will have no use after context
520 * switch and will stop the HW from creating streams itself
522 DCBT_STOP_ALL_STREAM_IDS(r6)
525 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
526 std r6,PACACURRENT(r13) /* Set new 'current' */
528 ld r8,KSP(r4) /* new stack pointer */
529 #ifdef CONFIG_PPC_STD_MMU_64
530 BEGIN_MMU_FTR_SECTION
532 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
534 clrrdi r6,r8,28 /* get its ESID */
535 clrrdi r9,r1,28 /* get current sp ESID */
537 clrrdi r6,r8,40 /* get its 1T ESID */
538 clrrdi r9,r1,40 /* get current sp 1T ESID */
539 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
540 clrldi. r0,r6,2 /* is new ESID c00000000? */
541 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
543 beq 2f /* if yes, don't slbie it */
545 /* Bolt in the new stack SLB entry */
546 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
547 oris r0,r6,(SLB_ESID_V)@h
548 ori r0,r0,(SLB_NUM_BOLTED-1)@l
550 li r9,MMU_SEGSIZE_1T /* insert B field */
551 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
552 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
553 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
555 /* Update the last bolted SLB. No write barriers are needed
556 * here, provided we only update the current CPU's SLB shadow
559 ld r9,PACA_SLBSHADOWPTR(r13)
561 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
562 li r12,SLBSHADOW_STACKVSID
563 STDX_BE r7,r12,r9 /* Save VSID */
564 li r12,SLBSHADOW_STACKESID
565 STDX_BE r0,r12,r9 /* Save ESID */
567 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
568 * we have 1TB segments, the only CPUs known to have the errata
569 * only support less than 1TB of system memory and we'll never
570 * actually hit this code path.
574 slbie r6 /* Workaround POWER5 < DD2.1 issue */
578 #endif /* CONFIG_PPC_STD_MMU_64 */
580 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
581 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
582 because we don't need to leave the 288-byte ABI gap at the
583 top of the kernel stack. */
584 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
586 mr r1,r8 /* start using new stack pointer */
587 std r7,PACAKSAVE(r13)
592 /* r3-r13 are destroyed -- Cort */
596 /* convert old thread to its task_struct for return value */
598 ld r7,_NIP(r1) /* Return to _switch caller in new task */
600 addi r1,r1,SWITCH_FRAME_SIZE
604 _GLOBAL(ret_from_except)
607 bne ret_from_except_lite
610 _GLOBAL(ret_from_except_lite)
612 * Disable interrupts so that current_thread_info()->flags
613 * can't change between when we test it and when we return
614 * from the interrupt.
616 #ifdef CONFIG_PPC_BOOK3E
620 mtmsrd r10,1 /* Update machine state */
621 #endif /* CONFIG_PPC_BOOK3E */
623 CURRENT_THREAD_INFO(r9, r1)
625 #ifdef CONFIG_PPC_BOOK3E
626 ld r10,PACACURRENT(r13)
627 #endif /* CONFIG_PPC_BOOK3E */
631 #ifdef CONFIG_PPC_BOOK3E
632 lwz r3,(THREAD+THREAD_DBCR0)(r10)
633 #endif /* CONFIG_PPC_BOOK3E */
635 /* Check current_thread_info()->flags */
636 andi. r0,r4,_TIF_USER_WORK_MASK
638 #ifdef CONFIG_PPC_BOOK3E
640 * Check to see if the dbcr0 register is set up to debug.
641 * Use the internal debug mode bit to do this.
643 andis. r0,r3,DBCR0_IDM@h
646 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
653 addi r3,r1,STACK_FRAME_OVERHEAD
657 1: andi. r0,r4,_TIF_NEED_RESCHED
659 bl restore_interrupts
661 b ret_from_except_lite
663 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
664 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
665 bne 3f /* only restore TM if nothing else to do */
666 addi r3,r1,STACK_FRAME_OVERHEAD
673 * Use a non volatile GPR to save and restore our thread_info flags
674 * across the call to restore_interrupts.
677 bl restore_interrupts
679 addi r3,r1,STACK_FRAME_OVERHEAD
684 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
685 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
688 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
691 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
692 mr r4,r1 /* src: current exception frame */
693 mr r1,r3 /* Reroute the trampoline frame to r1 */
695 /* Copy from the original to the trampoline. */
696 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
697 li r6,0 /* start offset: 0 */
704 /* Do real store operation to complete stdu */
708 /* Clear _TIF_EMULATE_STACK_STORE flag */
709 lis r11,_TIF_EMULATE_STACK_STORE@h
717 #ifdef CONFIG_PREEMPT
718 /* Check if we need to preempt */
719 andi. r0,r4,_TIF_NEED_RESCHED
721 /* Check that preempt_count() == 0 and interrupts are enabled */
722 lwz r8,TI_PREEMPT(r9)
726 crandc eq,cr1*4+eq,eq
730 * Here we are preempting the current task. We want to make
731 * sure we are soft-disabled first and reconcile irq state.
733 RECONCILE_IRQ_STATE(r3,r4)
734 1: bl preempt_schedule_irq
736 /* Re-test flags and eventually loop */
737 CURRENT_THREAD_INFO(r9, r1)
739 andi. r0,r4,_TIF_NEED_RESCHED
743 * arch_local_irq_restore() from preempt_schedule_irq above may
744 * enable hard interrupt but we really should disable interrupts
745 * when we return from the interrupt, and so that we don't get
746 * interrupted after loading SRR0/1.
748 #ifdef CONFIG_PPC_BOOK3E
752 mtmsrd r10,1 /* Update machine state */
753 #endif /* CONFIG_PPC_BOOK3E */
754 #endif /* CONFIG_PREEMPT */
756 .globl fast_exc_return_irq
760 * This is the main kernel exit path. First we check if we
761 * are about to re-enable interrupts
764 lbz r6,PACASOFTIRQEN(r13)
768 /* We are enabling, were we already enabled ? Yes, just return */
773 * We are about to soft-enable interrupts (we are hard disabled
774 * at this point). We check if there's anything that needs to
777 lbz r0,PACAIRQHAPPENED(r13)
779 bne- restore_check_irq_replay
782 * Get here when nothing happened while soft-disabled, just
783 * soft-enable and move-on. We will hard-enable as a side
789 stb r0,PACASOFTIRQEN(r13);
792 * Final return path. BookE is handled in a different file
795 #ifdef CONFIG_PPC_BOOK3E
796 b exception_return_book3e
799 * Clear the reservation. If we know the CPU tracks the address of
800 * the reservation then we can potentially save some cycles and use
801 * a larx. On POWER6 and POWER7 this is significantly faster.
804 stdcx. r0,0,r1 /* to clear the reservation */
807 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
810 * Some code path such as load_up_fpu or altivec return directly
811 * here. They run entirely hard disabled and do not alter the
812 * interrupt state. They also don't use lwarx/stwcx. and thus
813 * are known not to leave dangling reservations.
815 .globl fast_exception_return
816 fast_exception_return:
830 /* Load PPR from thread struct before we clear MSR:RI */
832 ld r2,PACACURRENT(r13)
833 ld r2,TASKTHREADPPR(r2)
834 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
837 * Clear RI before restoring r13. If we are returning to
838 * userspace and we take an exception after restoring r13,
839 * we end up corrupting the userspace r13 value.
844 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
846 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
849 * r13 is our per cpu area, only restore it if we are returning to
850 * userspace the value stored in the stack frame may belong to
856 mtspr SPRN_PPR,r2 /* Restore PPR */
857 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
858 ACCOUNT_CPU_USER_EXIT(r13, r2, r4)
875 b . /* prevent speculative execution */
877 #endif /* CONFIG_PPC_BOOK3E */
880 * We are returning to a context with interrupts soft disabled.
882 * However, we may also about to hard enable, so we need to
883 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
884 * or that bit can get out of sync and bad things will happen
888 lbz r7,PACAIRQHAPPENED(r13)
891 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
892 stb r7,PACAIRQHAPPENED(r13)
894 stb r0,PACASOFTIRQEN(r13);
899 * Something did happen, check if a re-emit is needed
900 * (this also clears paca->irq_happened)
902 restore_check_irq_replay:
903 /* XXX: We could implement a fast path here where we check
904 * for irq_happened being just 0x01, in which case we can
905 * clear it and return. That means that we would potentially
906 * miss a decrementer having wrapped all the way around.
908 * Still, this might be useful for things like hash_page
910 bl __check_irq_replay
912 beq restore_no_replay
915 * We need to re-emit an interrupt. We do so by re-using our
916 * existing exception frame. We first change the trap value,
917 * but we need to ensure we preserve the low nibble of it
925 * Then find the right handler and call it. Interrupts are
926 * still soft-disabled and we keep them that way.
930 addi r3,r1,STACK_FRAME_OVERHEAD;
933 1: cmpwi cr0,r3,0xe60
935 addi r3,r1,STACK_FRAME_OVERHEAD;
936 bl handle_hmi_exception
938 1: cmpwi cr0,r3,0x900
940 addi r3,r1,STACK_FRAME_OVERHEAD;
943 #ifdef CONFIG_PPC_DOORBELL
945 #ifdef CONFIG_PPC_BOOK3E
952 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
953 #endif /* CONFIG_PPC_BOOK3E */
955 addi r3,r1,STACK_FRAME_OVERHEAD;
956 bl doorbell_exception
958 #endif /* CONFIG_PPC_DOORBELL */
959 1: b ret_from_except /* What else to do here ? */
962 addi r3,r1,STACK_FRAME_OVERHEAD
963 bl unrecoverable_exception
966 #ifdef CONFIG_PPC_RTAS
968 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
969 * called with the MMU off.
971 * In addition, we need to be in 32b mode, at least for now.
973 * Note: r3 is an input parameter to rtas, so don't trash it...
978 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
980 /* Because RTAS is running in 32b mode, it clobbers the high order half
981 * of all registers that it saves. We therefore save those registers
982 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
984 SAVE_GPR(2, r1) /* Save the TOC */
985 SAVE_GPR(13, r1) /* Save paca */
986 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
987 SAVE_10GPRS(22, r1) /* ditto */
1000 /* Temporary workaround to clear CR until RTAS can be modified to
1007 /* There is no way it is acceptable to get here with interrupts enabled,
1008 * check it with the asm equivalent of WARN_ON
1010 lbz r0,PACASOFTIRQEN(r13)
1012 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1015 /* Hard-disable interrupts */
1021 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1022 * so they are saved in the PACA which allows us to restore
1023 * our original state after RTAS returns.
1026 std r6,PACASAVEDMSR(r13)
1028 /* Setup our real return addr */
1029 LOAD_REG_ADDR(r4,rtas_return_loc)
1030 clrldi r4,r4,2 /* convert to realmode address */
1034 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1038 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1039 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1041 sync /* disable interrupts so SRR0/1 */
1042 mtmsrd r0 /* don't get trashed */
1044 LOAD_REG_ADDR(r4, rtas)
1045 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1046 ld r4,RTASBASE(r4) /* get the rtas->base value */
1051 b . /* prevent speculative execution */
1056 /* relocation is off at this point */
1058 clrldi r4,r4,2 /* convert to realmode address */
1062 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1070 ld r1,PACAR1(r4) /* Restore our SP */
1071 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1076 b . /* prevent speculative execution */
1079 1: .llong rtas_restore_regs
1082 /* relocation is on at this point */
1083 REST_GPR(2, r1) /* Restore the TOC */
1084 REST_GPR(13, r1) /* Restore paca */
1085 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1086 REST_10GPRS(22, r1) /* ditto */
1101 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1102 ld r0,16(r1) /* get return address */
1105 blr /* return to caller */
1107 #endif /* CONFIG_PPC_RTAS */
1112 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1114 /* Because PROM is running in 32b mode, it clobbers the high order half
1115 * of all registers that it saves. We therefore save those registers
1116 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1127 /* Put PROM address in SRR0 */
1130 /* Setup our trampoline return addr in LR */
1133 addi r4,r4,(1f - 0b)
1136 /* Prepare a 32-bit mode big endian MSR
1138 #ifdef CONFIG_PPC_BOOK3E
1139 rlwinm r11,r11,0,1,31
1142 #else /* CONFIG_PPC_BOOK3E */
1143 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1147 #endif /* CONFIG_PPC_BOOK3E */
1149 1: /* Return from OF */
1152 /* Just make sure that r1 top 32 bits didn't get
1157 /* Restore the MSR (back to 64 bits) */
1162 /* Restore other registers */
1170 addi r1,r1,PROM_FRAME_SIZE