2 * Kernel execution entry point code.
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include <asm/ptrace.h>
45 #include "head_booke.h"
47 /* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 * r4 - Starting address of the init RAM disk
53 * r5 - Ending address of the init RAM disk
54 * r6 - Start of kernel command line string (e.g. "mem=128")
55 * r7 - End of kernel command line string
62 * Reserve a word at a fixed location to store the address
67 /* Translate device tree address to physical, save in r30/r31 */
70 rlwinm r17,r17,16,0x3fff0000 /* turn PID into MAS6[SPID] */
71 rlwimi r17,r16,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
74 tlbsx 0,r3 /* must succeed */
78 rlwinm r17,r16,25,0x1f /* r17 = log2(page size) */
80 slw r18,r18,r17 /* r18 = page size */
82 and r19,r3,r18 /* r19 = page offset */
83 andc r31,r20,r18 /* r31 = page base */
84 or r31,r31,r19 /* r31 = devtree phys addr */
87 li r25,0 /* phys kernel start (low) */
88 li r24,0 /* CPU number */
89 li r23,0 /* phys kernel start (high) */
91 /* We try to not make any assumptions about how the boot loader
92 * setup or used the TLBs. We invalidate all mappings from the
93 * boot loader and load a single entry in TLB1[0] to map the
94 * first 64M of kernel memory. Any boot info passed from the
95 * bootloader needs to live in this first 64M.
97 * Requirement on bootloader:
98 * - The page we're executing in needs to reside in TLB1 and
99 * have IPROT=1. If not an invalidate broadcast could
100 * evict the entry we're currently executing in.
102 * r3 = Index of TLB1 were executing in
103 * r4 = Current MSR[IS]
104 * r5 = Index of TLB1 temp mapping
106 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
110 _ENTRY(__early_start)
112 #define ENTRY_MAPPING_BOOT_SETUP
113 #include "fsl_booke_entry_mapping.S"
114 #undef ENTRY_MAPPING_BOOT_SETUP
116 /* Establish the interrupt vector offsets */
117 SET_IVOR(0, CriticalInput);
118 SET_IVOR(1, MachineCheck);
119 SET_IVOR(2, DataStorage);
120 SET_IVOR(3, InstructionStorage);
121 SET_IVOR(4, ExternalInput);
122 SET_IVOR(5, Alignment);
123 SET_IVOR(6, Program);
124 SET_IVOR(7, FloatingPointUnavailable);
125 SET_IVOR(8, SystemCall);
126 SET_IVOR(9, AuxillaryProcessorUnavailable);
127 SET_IVOR(10, Decrementer);
128 SET_IVOR(11, FixedIntervalTimer);
129 SET_IVOR(12, WatchdogTimer);
130 SET_IVOR(13, DataTLBError);
131 SET_IVOR(14, InstructionTLBError);
132 SET_IVOR(15, DebugCrit);
134 /* Establish the interrupt vector base */
135 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
138 /* Setup the defaults for TLB entries */
139 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
141 oris r2,r2,MAS4_TLBSELD(1)@h
148 oris r2,r2,HID0_DOZE@h
152 #if !defined(CONFIG_BDI_SWITCH)
154 * The Abatron BDI JTAG debugger does not tolerate others
155 * mucking with the debug registers.
160 /* clear any residual debug events */
166 /* Check to see if we're the second processor, and jump
167 * to the secondary_start code if so
169 lis r24, boot_cpuid@h
170 ori r24, r24, boot_cpuid@l
174 bne __secondary_start
178 * This is where the main kernel code starts.
183 ori r2,r2,init_task@l
185 /* ptr to current thread */
186 addi r4,r2,THREAD /* init task's THREAD */
187 mtspr SPRN_SPRG_THREAD,r4
190 lis r1,init_thread_union@h
191 ori r1,r1,init_thread_union@l
193 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
195 rlwinm r22,r1,0,0,31-THREAD_SHIFT /* current thread_info */
200 #ifdef CONFIG_DYNAMIC_MEMSTART
201 lis r3,kernstart_addr@ha
202 la r3,kernstart_addr@l(r3)
203 #ifdef CONFIG_PHYS_64BIT
212 * Decide what sort of machine this is and initialize the MMU.
219 /* Setup PTE pointers for the Abatron bdiGDB */
220 lis r6, swapper_pg_dir@h
221 ori r6, r6, swapper_pg_dir@l
222 lis r5, abatron_pteptrs@h
223 ori r5, r5, abatron_pteptrs@l
225 ori r4, r4, KERNELBASE@l
226 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
230 lis r4,start_kernel@h
231 ori r4,r4,start_kernel@l
233 ori r3,r3,MSR_KERNEL@l
236 rfi /* change context and jump to start_kernel */
238 /* Macros to hide the PTE size differences
240 * FIND_PTE -- walks the page tables given EA & pgdir pointer
242 * r11 -- PGDIR pointer
244 * label 2: is the bailout case
246 * if we find the pte (fall through):
247 * r11 is low pte word
248 * r12 is pointer to the pte
249 * r10 is the pshift from the PGD, if we're a hugepage
251 #ifdef CONFIG_PTE_64BIT
252 #ifdef CONFIG_HUGETLB_PAGE
254 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
255 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
256 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
257 blt 1000f; /* Normal non-huge page */ \
258 beq 2f; /* Bail if no table */ \
259 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
260 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
261 xor r12, r10, r11; /* drop size bits from pointer */ \
263 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
264 li r10, 0; /* clear r10 */ \
265 1001: lwz r11, 4(r12); /* Get pte entry */
268 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
269 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
270 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
271 beq 2f; /* Bail if no table */ \
272 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
273 lwz r11, 4(r12); /* Get pte entry */
274 #endif /* HUGEPAGE */
275 #else /* !PTE_64BIT */
277 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
278 lwz r11, 0(r11); /* Get L1 entry */ \
279 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
280 beq 2f; /* Bail if no table */ \
281 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
282 lwz r11, 0(r12); /* Get Linux PTE */
286 * Interrupt vector entry code
288 * The Book E MMUs are always on so we don't need to handle
289 * interrupts in real mode as with previous PPC processors. In
290 * this case we handle interrupts in the kernel virtual address
293 * Interrupt vectors are dynamically placed relative to the
294 * interrupt prefix as determined by the address of interrupt_base.
295 * The interrupt vectors offsets are programmed using the labels
296 * for each interrupt vector entry.
298 * Interrupt vectors must be aligned on a 16 byte boundary.
299 * We align on a 32 byte cache line boundary for good measure.
303 /* Critical Input Interrupt */
304 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
306 /* Machine Check Interrupt */
308 /* no RFMCI, MCSRRs on E200 */
309 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
310 machine_check_exception)
312 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
315 /* Data Storage Interrupt */
316 START_EXCEPTION(DataStorage)
317 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
318 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
320 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
321 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
323 EXC_XFER_LITE(0x0300, handle_page_fault)
325 addi r3,r1,STACK_FRAME_OVERHEAD
326 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
328 /* Instruction Storage Interrupt */
329 INSTRUCTION_STORAGE_EXCEPTION
331 /* External Input Interrupt */
332 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
334 /* Alignment Interrupt */
337 /* Program Interrupt */
340 /* Floating Point Unavailable Interrupt */
341 #ifdef CONFIG_PPC_FPU
342 FP_UNAVAILABLE_EXCEPTION
345 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
346 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
347 program_check_exception, EXC_XFER_EE)
349 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
350 unknown_exception, EXC_XFER_EE)
354 /* System Call Interrupt */
355 START_EXCEPTION(SystemCall)
356 NORMAL_EXCEPTION_PROLOG(SYSCALL)
357 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
359 /* Auxiliary Processor Unavailable Interrupt */
360 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
361 unknown_exception, EXC_XFER_EE)
363 /* Decrementer Interrupt */
364 DECREMENTER_EXCEPTION
366 /* Fixed Internal Timer Interrupt */
367 /* TODO: Add FIT support */
368 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
369 unknown_exception, EXC_XFER_EE)
371 /* Watchdog Timer Interrupt */
372 #ifdef CONFIG_BOOKE_WDT
373 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
375 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
378 /* Data TLB Error Interrupt */
379 START_EXCEPTION(DataTLBError)
380 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
381 mfspr r10, SPRN_SPRG_THREAD
382 stw r11, THREAD_NORMSAVE(0)(r10)
383 #ifdef CONFIG_KVM_BOOKE_HV
386 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
388 stw r12, THREAD_NORMSAVE(1)(r10)
389 stw r13, THREAD_NORMSAVE(2)(r10)
391 stw r13, THREAD_NORMSAVE(3)(r10)
392 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
393 mfspr r10, SPRN_DEAR /* Get faulting address */
395 /* If we are faulting a kernel address, we have to use the
396 * kernel page tables.
398 lis r11, PAGE_OFFSET@h
401 lis r11, swapper_pg_dir@h
402 ori r11, r11, swapper_pg_dir@l
404 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
405 rlwinm r12,r12,0,16,1
410 /* Get the PGD for the current thread */
412 mfspr r11,SPRN_SPRG_THREAD
416 /* Mask of required permission bits. Note that while we
417 * do copy ESR:ST to _PAGE_RW position as trying to write
418 * to an RO page is pretty common, we don't do it with
419 * _PAGE_DIRTY. We could do it, but it's a fairly rare
420 * event so I'd rather take the overhead when it happens
421 * rather than adding an instruction here. We should measure
422 * whether the whole thing is worth it in the first place
423 * as we could avoid loading SPRN_ESR completely in the first
426 * TODO: Is it worth doing that mfspr & rlwimi in the first
427 * place or can we save a couple of instructions here ?
430 #ifdef CONFIG_PTE_64BIT
432 oris r13,r13,_PAGE_ACCESSED@h
434 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
436 rlwimi r13,r12,11,29,29
439 andc. r13,r13,r11 /* Check permission */
441 #ifdef CONFIG_PTE_64BIT
443 subf r13,r11,r12 /* create false data dep */
444 lwzx r13,r11,r13 /* Get upper pte bits */
446 lwz r13,0(r12) /* Get upper pte bits */
450 bne 2f /* Bail if permission/valid mismach */
452 /* Jump to common tlb load */
455 /* The bailout. Restore registers to pre-exception conditions
456 * and call the heavyweights to help us out.
458 mfspr r10, SPRN_SPRG_THREAD
459 lwz r11, THREAD_NORMSAVE(3)(r10)
461 lwz r13, THREAD_NORMSAVE(2)(r10)
462 lwz r12, THREAD_NORMSAVE(1)(r10)
463 lwz r11, THREAD_NORMSAVE(0)(r10)
464 mfspr r10, SPRN_SPRG_RSCRATCH0
467 /* Instruction TLB Error Interrupt */
469 * Nearly the same as above, except we get our
470 * information from different registers and bailout
471 * to a different point.
473 START_EXCEPTION(InstructionTLBError)
474 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
475 mfspr r10, SPRN_SPRG_THREAD
476 stw r11, THREAD_NORMSAVE(0)(r10)
477 #ifdef CONFIG_KVM_BOOKE_HV
480 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
482 stw r12, THREAD_NORMSAVE(1)(r10)
483 stw r13, THREAD_NORMSAVE(2)(r10)
485 stw r13, THREAD_NORMSAVE(3)(r10)
486 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
487 mfspr r10, SPRN_SRR0 /* Get faulting address */
489 /* If we are faulting a kernel address, we have to use the
490 * kernel page tables.
492 lis r11, PAGE_OFFSET@h
495 lis r11, swapper_pg_dir@h
496 ori r11, r11, swapper_pg_dir@l
498 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
499 rlwinm r12,r12,0,16,1
502 /* Make up the required permissions for kernel code */
503 #ifdef CONFIG_PTE_64BIT
504 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
505 oris r13,r13,_PAGE_ACCESSED@h
507 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
511 /* Get the PGD for the current thread */
513 mfspr r11,SPRN_SPRG_THREAD
516 /* Make up the required permissions for user code */
517 #ifdef CONFIG_PTE_64BIT
518 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
519 oris r13,r13,_PAGE_ACCESSED@h
521 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
526 andc. r13,r13,r11 /* Check permission */
528 #ifdef CONFIG_PTE_64BIT
530 subf r13,r11,r12 /* create false data dep */
531 lwzx r13,r11,r13 /* Get upper pte bits */
533 lwz r13,0(r12) /* Get upper pte bits */
537 bne 2f /* Bail if permission mismach */
539 /* Jump to common TLB load point */
543 /* The bailout. Restore registers to pre-exception conditions
544 * and call the heavyweights to help us out.
546 mfspr r10, SPRN_SPRG_THREAD
547 lwz r11, THREAD_NORMSAVE(3)(r10)
549 lwz r13, THREAD_NORMSAVE(2)(r10)
550 lwz r12, THREAD_NORMSAVE(1)(r10)
551 lwz r11, THREAD_NORMSAVE(0)(r10)
552 mfspr r10, SPRN_SPRG_RSCRATCH0
556 /* SPE Unavailable */
557 START_EXCEPTION(SPEUnavailable)
558 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
560 addi r3,r1,STACK_FRAME_OVERHEAD
561 EXC_XFER_EE_LITE(0x2010, KernelSPE)
563 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
564 unknown_exception, EXC_XFER_EE)
565 #endif /* CONFIG_SPE */
567 /* SPE Floating Point Data */
569 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData, \
570 SPEFloatingPointException, EXC_XFER_EE);
572 /* SPE Floating Point Round */
573 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
574 SPEFloatingPointRoundException, EXC_XFER_EE)
576 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, \
577 unknown_exception, EXC_XFER_EE)
578 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
579 unknown_exception, EXC_XFER_EE)
580 #endif /* CONFIG_SPE */
582 /* Performance Monitor */
583 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
584 performance_monitor_exception, EXC_XFER_STD)
586 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
588 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
589 CriticalDoorbell, unknown_exception)
591 /* Debug Interrupt */
592 DEBUG_DEBUG_EXCEPTION
595 GUEST_DOORBELL_EXCEPTION
597 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
601 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE)
603 /* Embedded Hypervisor Privilege */
604 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
611 * Both the instruction and data TLB miss get to this
612 * point to load the TLB.
613 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
614 * r11 - TLB (info from Linux PTE)
615 * r12 - available to use
616 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
617 * CR5 - results of addr >= PAGE_OFFSET
618 * MAS0, MAS1 - loaded with proper value when we get here
619 * MAS2, MAS3 - will need additional info from Linux PTE
620 * Upon exit, we reload everything and RFI.
623 #ifdef CONFIG_HUGETLB_PAGE
624 cmpwi 6, r10, 0 /* check for huge page */
625 beq 6, finish_tlb_load_cont /* !huge */
627 /* Alas, we need more scratch registers for hugepages */
628 mfspr r12, SPRN_SPRG_THREAD
629 stw r14, THREAD_NORMSAVE(4)(r12)
630 stw r15, THREAD_NORMSAVE(5)(r12)
631 stw r16, THREAD_NORMSAVE(6)(r12)
632 stw r17, THREAD_NORMSAVE(7)(r12)
634 /* Get the next_tlbcam_idx percpu var */
636 lwz r12, THREAD_INFO-THREAD(r12)
638 lis r14, __per_cpu_offset@h
639 ori r14, r14, __per_cpu_offset@l
640 rlwinm r15, r15, 2, 0, 29
645 lis r17, next_tlbcam_idx@h
646 ori r17, r17, next_tlbcam_idx@l
647 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
648 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
650 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
651 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
654 /* Extract TLB1CFG(NENTRY) */
655 mfspr r16, SPRN_TLB1CFG
656 andi. r16, r16, 0xfff
658 /* Update next_tlbcam_idx, wrapping when necessary */
662 lis r14, tlbcam_index@h
663 ori r14, r14, tlbcam_index@l
668 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
669 * tlb_enc = (pshift - 10).
673 rlwimi r16, r15, 7, 20, 24
676 /* copy the pshift for use later */
681 #endif /* CONFIG_HUGETLB_PAGE */
684 * We set execute, because we don't have the granularity to
685 * properly set this at the page level (Linux problem).
686 * Many of these bits are software only. Bits we don't set
687 * here we (properly should) assume have the appropriate value.
689 finish_tlb_load_cont:
690 #ifdef CONFIG_PTE_64BIT
691 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
692 andi. r10, r11, _PAGE_DIRTY
694 li r10, MAS3_SW | MAS3_UW
696 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
697 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
698 2: mtspr SPRN_MAS3, r12
699 BEGIN_MMU_FTR_SECTION
700 srwi r10, r13, 12 /* grab RPN[12:31] */
702 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
704 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
706 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
708 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
712 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
717 #ifdef CONFIG_PTE_64BIT
718 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
720 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
722 #ifdef CONFIG_HUGETLB_PAGE
723 beq 6, 3f /* don't mask if page isn't huge */
727 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
728 andc r12, r12, r13 /* mask off ea bits within the page */
730 3: mtspr SPRN_MAS2, r12
733 /* Round robin TLB1 entries assignment */
736 /* Extract TLB1CFG(NENTRY) */
737 mfspr r11, SPRN_TLB1CFG
738 andi. r11, r11, 0xfff
740 /* Extract MAS0(NV) */
741 andi. r13, r12, 0xfff
746 /* check if we need to wrap */
749 /* wrap back to first free tlbcam entry */
750 lis r13, tlbcam_index@ha
751 lwz r13, tlbcam_index@l(r13)
752 rlwimi r12, r13, 0, 20, 31
755 #endif /* CONFIG_E200 */
760 /* Done...restore registers and get out of here. */
761 mfspr r10, SPRN_SPRG_THREAD
762 #ifdef CONFIG_HUGETLB_PAGE
763 beq 6, 8f /* skip restore for 4k page faults */
764 lwz r14, THREAD_NORMSAVE(4)(r10)
765 lwz r15, THREAD_NORMSAVE(5)(r10)
766 lwz r16, THREAD_NORMSAVE(6)(r10)
767 lwz r17, THREAD_NORMSAVE(7)(r10)
769 8: lwz r11, THREAD_NORMSAVE(3)(r10)
771 lwz r13, THREAD_NORMSAVE(2)(r10)
772 lwz r12, THREAD_NORMSAVE(1)(r10)
773 lwz r11, THREAD_NORMSAVE(0)(r10)
774 mfspr r10, SPRN_SPRG_RSCRATCH0
775 rfi /* Force context change */
778 /* Note that the SPE support is closely modeled after the AltiVec
779 * support. Changes to one are likely to be applicable to the
783 * Disable SPE for the task which had SPE previously,
784 * and save its SPE registers in its thread_struct.
785 * Enables SPE for use in the kernel on return.
786 * On SMP we know the SPE units are free, since we give it up every
791 mtmsr r5 /* enable use of SPE now */
794 * For SMP, we don't do lazy SPE switching because it just gets too
795 * horrendously complex, especially when a task switches from one CPU
796 * to another. Instead we call giveup_spe in switch_to.
799 lis r3,last_task_used_spe@ha
800 lwz r4,last_task_used_spe@l(r3)
803 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
804 SAVE_32EVRS(0,r10,r4,THREAD_EVR0)
805 evxor evr10, evr10, evr10 /* clear out evr10 */
806 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
808 evstddx evr10, r4, r5 /* save off accumulator */
810 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
812 andc r4,r4,r10 /* disable SPE for previous task */
813 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
815 #endif /* !CONFIG_SMP */
816 /* enable use of SPE after return */
818 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
821 stw r4,THREAD_USED_SPE(r5)
824 REST_32EVRS(0,r10,r5,THREAD_EVR0)
827 stw r4,last_task_used_spe@l(r3)
828 #endif /* !CONFIG_SMP */
829 /* restore registers and return */
830 2: REST_4GPRS(3, r11)
845 * SPE unavailable trap from kernel - print a message, but let
846 * the task use SPE in the kernel until it returns to user mode.
851 stw r3,_MSR(r1) /* enable use of SPE after return */
855 mr r4,r2 /* current */
861 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
865 #endif /* CONFIG_SPE */
871 /* Adjust or setup IVORs for e200 */
872 _GLOBAL(__setup_e200_ivors)
875 li r3,SPEUnavailable@l
877 li r3,SPEFloatingPointData@l
879 li r3,SPEFloatingPointRound@l
884 /* Adjust or setup IVORs for e500v1/v2 */
885 _GLOBAL(__setup_e500_ivors)
888 li r3,SPEUnavailable@l
890 li r3,SPEFloatingPointData@l
892 li r3,SPEFloatingPointRound@l
894 li r3,PerformanceMonitor@l
899 /* Adjust or setup IVORs for e500mc */
900 _GLOBAL(__setup_e500mc_ivors)
903 li r3,PerformanceMonitor@l
907 li r3,CriticalDoorbell@l
911 * We only want to touch IVOR38-41 if we're running on hardware
912 * that supports category E.HV. The architectural way to determine
913 * this is MMUCFG[LPIDSIZE].
915 mfspr r3, SPRN_MMUCFG
916 andis. r3, r3, MMUCFG_LPIDSIZE@h
918 li r3,GuestDoorbell@l
920 li r3,CriticalGuestDoorbell@l
930 lwz r3, CPU_SPEC_FEATURES(r5)
931 rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV
932 stw r3, CPU_SPEC_FEATURES(r5)
937 * extern void giveup_spe(struct task_struct *prev)
943 mtmsr r5 /* enable use of SPE now */
946 beqlr- /* if no previous owner, done */
947 addi r3,r3,THREAD /* want THREAD of task */
950 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
951 evxor evr6, evr6, evr6 /* clear out evr6 */
952 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
954 evstddx evr6, r4, r3 /* save off accumulator */
956 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
958 andc r4,r4,r3 /* disable SPE for previous task */
959 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
963 lis r4,last_task_used_spe@ha
964 stw r5,last_task_used_spe@l(r4)
965 #endif /* !CONFIG_SMP */
967 #endif /* CONFIG_SPE */
970 * extern void giveup_fpu(struct task_struct *prev)
972 * Not all FSL Book-E cores have an FPU
974 #ifndef CONFIG_PPC_FPU
980 * extern void abort(void)
982 * At present, this routine just applies a system reset.
986 mtspr SPRN_DBCR0,r13 /* disable all debug events */
989 ori r13,r13,MSR_DE@l /* Enable Debug Events */
993 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
999 #ifdef CONFIG_BDI_SWITCH
1000 /* Context switch the PTE pointer for the Abatron BDI2000.
1001 * The PGDIR is the second parameter.
1003 lis r5, abatron_pteptrs@h
1004 ori r5, r5, abatron_pteptrs@l
1008 isync /* Force context change */
1011 _GLOBAL(flush_dcache_L1)
1012 mfspr r3,SPRN_L1CFG0
1014 rlwinm r5,r3,9,3 /* Extract cache block size */
1015 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1016 * are currently defined.
1019 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1020 * log2(number of ways)
1022 slw r5,r4,r5 /* r5 = cache block size */
1024 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1025 mulli r7,r7,13 /* An 8-way cache will require 13
1030 /* save off HID0 and set DCFA */
1032 ori r9,r8,HID0_DCFA@l
1039 1: lwz r3,0(r4) /* Load... */
1047 1: dcbf 0,r4 /* ...and flush. */
1058 /* When we get here, r24 needs to hold the CPU # */
1059 .globl __secondary_start
1061 lis r3,__secondary_hold_acknowledge@h
1062 ori r3,r3,__secondary_hold_acknowledge@l
1066 mr r4,r24 /* Why? */
1069 lis r3,tlbcam_index@ha
1070 lwz r3,tlbcam_index@l(r3)
1072 li r26,0 /* r26 safe? */
1074 /* Load each CAM entry */
1080 /* get current_thread_info and current */
1081 lis r1,secondary_ti@ha
1082 lwz r1,secondary_ti@l(r1)
1086 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1090 /* ptr to current thread */
1091 addi r4,r2,THREAD /* address of our thread_struct */
1092 mtspr SPRN_SPRG_THREAD,r4
1094 /* Setup the defaults for TLB entries */
1095 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1098 /* Jump to start_secondary */
1100 ori r4,r4,MSR_KERNEL@l
1101 lis r3,start_secondary@h
1102 ori r3,r3,start_secondary@l
1109 .globl __secondary_hold_acknowledge
1110 __secondary_hold_acknowledge:
1115 * We put a few things here that have to be page-aligned. This stuff
1116 * goes at the beginning of the data segment, which is page-aligned.
1122 .globl empty_zero_page
1125 .globl swapper_pg_dir
1127 .space PGD_TABLE_SIZE
1130 * Room for two PTE pointers, usually the kernel and current user pointers
1131 * to their respective root page table.