2 * Machine check exception handling CPU-side for power7 and power8
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright 2013 IBM Corporation
19 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
23 #define pr_fmt(fmt) "mce_power: " fmt
25 #include <linux/types.h>
26 #include <linux/ptrace.h>
30 /* flush SLBs and reload */
31 static void flush_and_reload_slb(void)
33 struct slb_shadow *slb;
36 /* Invalidate all SLBs */
37 asm volatile("slbmte %0,%0; slbia" : : "r" (0));
39 #ifdef CONFIG_KVM_BOOK3S_HANDLER
41 * If machine check is hit when in guest or in transition, we will
42 * only flush the SLBs and continue.
44 if (get_paca()->kvm_hstate.in_guest)
48 /* For host kernel, reload the SLBs from shadow SLB buffer. */
49 slb = get_slb_shadow();
53 n = min_t(u32, slb->persistent, SLB_MIN_SIZE);
55 /* Load up the SLB entries from shadow SLB */
56 for (i = 0; i < n; i++) {
57 unsigned long rb = slb->save_area[i].esid;
58 unsigned long rs = slb->save_area[i].vsid;
60 rb = (rb & ~0xFFFul) | i;
61 asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
65 static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
70 * flush and reload SLBs for SLB errors and flush TLBs for TLB errors.
71 * reset the error bits whenever we handle them so that at the end
72 * we can check whether we handled all of them or not.
74 if (dsisr & slb_error_bits) {
75 flush_and_reload_slb();
76 /* reset error bits */
77 dsisr &= ~(slb_error_bits);
79 if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
80 if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
81 cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
82 /* reset error bits */
83 dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
85 /* Any other errors we don't understand? */
86 if (dsisr & 0xffffffffUL)
92 static long mce_handle_derror_p7(uint64_t dsisr)
94 return mce_handle_derror(dsisr, P7_DSISR_MC_SLB_ERRORS);
97 static long mce_handle_common_ierror(uint64_t srr1)
101 switch (P7_SRR1_MC_IFETCH(srr1)) {
104 case P7_SRR1_MC_IFETCH_SLB_PARITY:
105 case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
106 /* flush and reload SLBs for SLB errors. */
107 flush_and_reload_slb();
110 case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
111 if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
112 cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
123 static long mce_handle_ierror_p7(uint64_t srr1)
127 handled = mce_handle_common_ierror(srr1);
129 if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
130 flush_and_reload_slb();
136 long __machine_check_early_realmode_p7(struct pt_regs *regs)
143 if (P7_SRR1_MC_LOADSTORE(srr1))
144 handled = mce_handle_derror_p7(regs->dsisr);
146 handled = mce_handle_ierror_p7(srr1);
148 /* TODO: Decode machine check reason. */
152 static long mce_handle_ierror_p8(uint64_t srr1)
156 handled = mce_handle_common_ierror(srr1);
158 if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
159 flush_and_reload_slb();
165 static long mce_handle_derror_p8(uint64_t dsisr)
167 return mce_handle_derror(dsisr, P8_DSISR_MC_SLB_ERRORS);
170 long __machine_check_early_realmode_p8(struct pt_regs *regs)
177 if (P7_SRR1_MC_LOADSTORE(srr1))
178 handled = mce_handle_derror_p8(regs->dsisr);
180 handled = mce_handle_ierror_p8(srr1);
182 /* TODO: Decode machine check reason. */