2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
25 #include <linux/vmalloc.h>
27 #include <asm/processor.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
34 #include <asm/firmware.h>
38 #define DBG(fmt...) printk(fmt)
43 unsigned long pci_probe_only = 1;
44 int pci_assign_all_buses = 0;
46 static void fixup_resource(struct resource *res, struct pci_dev *dev);
47 static void do_bus_setup(struct pci_bus *bus);
49 /* pci_io_base -- the base address from which io bars are offsets.
50 * This is the lowest I/O base address (so bar values are always positive),
51 * and it *must* be the start of ISA space if an ISA bus exists because
52 * ISA drivers use hard coded offsets. If no ISA bus exists nothing
53 * is mapped on the first 64K of IO space
55 unsigned long pci_io_base = ISA_IO_BASE;
56 EXPORT_SYMBOL(pci_io_base);
60 static struct dma_mapping_ops *pci_dma_ops;
62 void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
64 pci_dma_ops = dma_ops;
67 struct dma_mapping_ops *get_pci_dma_ops(void)
71 EXPORT_SYMBOL(get_pci_dma_ops);
73 static void fixup_broken_pcnet32(struct pci_dev* dev)
75 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
76 dev->vendor = PCI_VENDOR_ID_AMD;
77 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
80 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
82 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
85 unsigned long offset = 0;
86 struct pci_controller *hose = pci_bus_to_host(dev->bus);
91 if (res->flags & IORESOURCE_IO)
92 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
94 if (res->flags & IORESOURCE_MEM)
95 offset = hose->pci_mem_offset;
97 region->start = res->start - offset;
98 region->end = res->end - offset;
101 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
102 struct pci_bus_region *region)
104 unsigned long offset = 0;
105 struct pci_controller *hose = pci_bus_to_host(dev->bus);
110 if (res->flags & IORESOURCE_IO)
111 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
113 if (res->flags & IORESOURCE_MEM)
114 offset = hose->pci_mem_offset;
116 res->start = region->start + offset;
117 res->end = region->end + offset;
120 #ifdef CONFIG_HOTPLUG
121 EXPORT_SYMBOL(pcibios_resource_to_bus);
122 EXPORT_SYMBOL(pcibios_bus_to_resource);
126 * We need to avoid collisions with `mirrored' VGA ports
127 * and other strange ISA hardware, so we always want the
128 * addresses to be allocated in the 0x000-0x0ff region
131 * Why? Because some silly external IO cards only decode
132 * the low 10 bits of the IO address. The 0x00-0xff region
133 * is reserved for motherboard devices that decode all 16
134 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
135 * but we want to try to avoid allocating at 0x2900-0x2bff
136 * which might have be mirrored at 0x0100-0x03ff..
138 void pcibios_align_resource(void *data, struct resource *res,
139 resource_size_t size, resource_size_t align)
141 struct pci_dev *dev = data;
142 struct pci_controller *hose = pci_bus_to_host(dev->bus);
143 resource_size_t start = res->start;
144 unsigned long alignto;
146 if (res->flags & IORESOURCE_IO) {
147 unsigned long offset = (unsigned long)hose->io_base_virt -
149 /* Make sure we start at our min on all hoses */
150 if (start - offset < PCIBIOS_MIN_IO)
151 start = PCIBIOS_MIN_IO + offset;
154 * Put everything into 0x00-0xff region modulo 0x400
157 start = (start + 0x3ff) & ~0x3ff;
159 } else if (res->flags & IORESOURCE_MEM) {
160 /* Make sure we start at our min on all hoses */
161 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
162 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
164 /* Align to multiple of size of minimum base. */
165 alignto = max(0x1000UL, align);
166 start = ALIGN(start, alignto);
172 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
175 struct pci_bus *child_bus;
177 list_for_each_entry(dev, &b->devices, bus_list) {
180 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
181 struct resource *r = &dev->resource[i];
183 if (r->parent || !r->start || !r->flags)
185 pci_claim_resource(dev, i);
189 list_for_each_entry(child_bus, &b->children, node)
190 pcibios_claim_one_bus(child_bus);
192 #ifdef CONFIG_HOTPLUG
193 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
196 static void __init pcibios_claim_of_setup(void)
200 if (firmware_has_feature(FW_FEATURE_ISERIES))
203 list_for_each_entry(b, &pci_root_buses, node)
204 pcibios_claim_one_bus(b);
207 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
212 prop = of_get_property(np, name, &len);
213 if (prop && len >= 4)
218 static unsigned int pci_parse_of_flags(u32 addr0)
220 unsigned int flags = 0;
222 if (addr0 & 0x02000000) {
223 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
224 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
225 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
226 if (addr0 & 0x40000000)
227 flags |= IORESOURCE_PREFETCH
228 | PCI_BASE_ADDRESS_MEM_PREFETCH;
229 } else if (addr0 & 0x01000000)
230 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
234 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
236 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
240 struct resource *res;
245 addrs = of_get_property(node, "assigned-addresses", &proplen);
248 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
249 for (; proplen >= 20; proplen -= 20, addrs += 5) {
250 flags = pci_parse_of_flags(addrs[0]);
253 base = GET_64BIT(addrs, 1);
254 size = GET_64BIT(addrs, 3);
258 DBG(" base: %llx, size: %llx, i: %x\n",
259 (unsigned long long)base, (unsigned long long)size, i);
261 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
262 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
263 } else if (i == dev->rom_base_reg) {
264 res = &dev->resource[PCI_ROM_RESOURCE];
265 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
267 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
271 res->end = base + size - 1;
273 res->name = pci_name(dev);
274 fixup_resource(res, dev);
278 struct pci_dev *of_create_pci_dev(struct device_node *node,
279 struct pci_bus *bus, int devfn)
284 dev = alloc_pci_dev();
287 type = of_get_property(node, "device_type", NULL);
291 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
295 dev->dev.parent = bus->bridge;
296 dev->dev.bus = &pci_bus_type;
298 dev->multifunction = 0; /* maybe a lie? */
300 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
301 dev->device = get_int_prop(node, "device-id", 0xffff);
302 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
303 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
305 dev->cfg_size = pci_cfg_space_size(dev);
307 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
308 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
309 dev->class = get_int_prop(node, "class-code", 0);
311 DBG(" class: 0x%x\n", dev->class);
313 dev->current_state = 4; /* unknown power state */
314 dev->error_state = pci_channel_io_normal;
316 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
317 /* a PCI-PCI bridge */
318 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
319 dev->rom_base_reg = PCI_ROM_ADDRESS1;
320 } else if (!strcmp(type, "cardbus")) {
321 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
323 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
324 dev->rom_base_reg = PCI_ROM_ADDRESS;
325 /* Maybe do a default OF mapping here */
329 pci_parse_of_addrs(node, dev);
331 DBG(" adding to system ...\n");
333 pci_device_add(dev, bus);
337 EXPORT_SYMBOL(of_create_pci_dev);
339 void __devinit of_scan_bus(struct device_node *node,
342 struct device_node *child = NULL;
347 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
349 while ((child = of_get_next_child(node, child)) != NULL) {
350 DBG(" * %s\n", child->full_name);
351 reg = of_get_property(child, "reg", ®len);
352 if (reg == NULL || reglen < 20)
354 devfn = (reg[0] >> 8) & 0xff;
356 /* create a new pci_dev for this device */
357 dev = of_create_pci_dev(child, bus, devfn);
360 DBG("dev header type: %x\n", dev->hdr_type);
362 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
363 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
364 of_scan_pci_bridge(child, dev);
369 EXPORT_SYMBOL(of_scan_bus);
371 void __devinit of_scan_pci_bridge(struct device_node *node,
375 const u32 *busrange, *ranges;
377 struct resource *res;
381 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
383 /* parse bus-range property */
384 busrange = of_get_property(node, "bus-range", &len);
385 if (busrange == NULL || len != 8) {
386 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
390 ranges = of_get_property(node, "ranges", &len);
391 if (ranges == NULL) {
392 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
397 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
399 printk(KERN_ERR "Failed to create pci bus for %s\n",
404 bus->primary = dev->bus->number;
405 bus->subordinate = busrange[1];
409 /* parse ranges property */
410 /* PCI #address-cells == 3 and #size-cells == 2 always */
411 res = &dev->resource[PCI_BRIDGE_RESOURCES];
412 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
414 bus->resource[i] = res;
418 for (; len >= 32; len -= 32, ranges += 8) {
419 flags = pci_parse_of_flags(ranges[0]);
420 size = GET_64BIT(ranges, 6);
421 if (flags == 0 || size == 0)
423 if (flags & IORESOURCE_IO) {
424 res = bus->resource[0];
426 printk(KERN_ERR "PCI: ignoring extra I/O range"
427 " for bridge %s\n", node->full_name);
431 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
432 printk(KERN_ERR "PCI: too many memory ranges"
433 " for bridge %s\n", node->full_name);
436 res = bus->resource[i];
439 res->start = GET_64BIT(ranges, 1);
440 res->end = res->start + size - 1;
442 fixup_resource(res, dev);
444 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
446 DBG(" bus name: %s\n", bus->name);
448 mode = PCI_PROBE_NORMAL;
449 if (ppc_md.pci_probe_mode)
450 mode = ppc_md.pci_probe_mode(bus);
451 DBG(" probe mode: %d\n", mode);
453 if (mode == PCI_PROBE_DEVTREE)
454 of_scan_bus(node, bus);
455 else if (mode == PCI_PROBE_NORMAL)
456 pci_scan_child_bus(bus);
458 EXPORT_SYMBOL(of_scan_pci_bridge);
460 void __devinit scan_phb(struct pci_controller *hose)
463 struct device_node *node = hose->arch_data;
465 struct resource *res;
467 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
469 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
471 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
472 hose->global_number);
475 bus->secondary = hose->first_busno;
478 if (!firmware_has_feature(FW_FEATURE_ISERIES))
479 pcibios_map_io_space(bus);
481 bus->resource[0] = res = &hose->io_resource;
482 if (res->flags && request_resource(&ioport_resource, res)) {
483 printk(KERN_ERR "Failed to request PCI IO region "
484 "on PCI domain %04x\n", hose->global_number);
485 DBG("res->start = 0x%016lx, res->end = 0x%016lx\n",
486 res->start, res->end);
489 for (i = 0; i < 3; ++i) {
490 res = &hose->mem_resources[i];
491 bus->resource[i+1] = res;
492 if (res->flags && request_resource(&iomem_resource, res))
493 printk(KERN_ERR "Failed to request PCI memory region "
494 "on PCI domain %04x\n", hose->global_number);
497 mode = PCI_PROBE_NORMAL;
499 if (node && ppc_md.pci_probe_mode)
500 mode = ppc_md.pci_probe_mode(bus);
501 DBG(" probe mode: %d\n", mode);
502 if (mode == PCI_PROBE_DEVTREE) {
503 bus->subordinate = hose->last_busno;
504 of_scan_bus(node, bus);
507 if (mode == PCI_PROBE_NORMAL)
508 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
511 static int __init pcibios_init(void)
513 struct pci_controller *hose, *tmp;
515 /* For now, override phys_mem_access_prot. If we need it,
516 * later, we may move that initialization to each ppc_md
518 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
520 if (firmware_has_feature(FW_FEATURE_ISERIES))
521 iSeries_pcibios_init();
523 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
525 /* Scan all of the recorded PCI controllers. */
526 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
528 pci_bus_add_devices(hose->bus);
531 if (!firmware_has_feature(FW_FEATURE_ISERIES)) {
533 pcibios_claim_of_setup();
535 /* FIXME: `else' will be removed when
536 pci_assign_unassigned_resources() is able to work
537 correctly with [partially] allocated PCI tree. */
538 pci_assign_unassigned_resources();
541 /* Call machine dependent final fixup */
542 if (ppc_md.pcibios_fixup)
543 ppc_md.pcibios_fixup();
545 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
550 subsys_initcall(pcibios_init);
552 int pcibios_enable_device(struct pci_dev *dev, int mask)
557 pci_read_config_word(dev, PCI_COMMAND, &cmd);
560 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
561 struct resource *res = &dev->resource[i];
563 /* Only set up the requested stuff */
564 if (!(mask & (1<<i)))
567 if (res->flags & IORESOURCE_IO)
568 cmd |= PCI_COMMAND_IO;
569 if (res->flags & IORESOURCE_MEM)
570 cmd |= PCI_COMMAND_MEMORY;
574 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
576 /* Enable the appropriate bits in the PCI command register. */
577 pci_write_config_word(dev, PCI_COMMAND, cmd);
582 /* Decide whether to display the domain number in /proc */
583 int pci_proc_domain(struct pci_bus *bus)
585 if (firmware_has_feature(FW_FEATURE_ISERIES))
588 struct pci_controller *hose = pci_bus_to_host(bus);
593 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
594 struct device_node *dev, int prim)
596 const unsigned int *ranges;
597 unsigned int pci_space;
601 struct resource *res;
602 int np, na = of_n_addr_cells(dev);
603 unsigned long pci_addr, cpu_phys_addr;
607 /* From "PCI Binding to 1275"
608 * The ranges property is laid out as an array of elements,
609 * each of which comprises:
610 * cells 0 - 2: a PCI address
611 * cells 3 or 3+4: a CPU physical address
612 * (size depending on dev->n_addr_cells)
613 * cells 4+5 or 5+6: the size of the range
615 ranges = of_get_property(dev, "ranges", &rlen);
618 hose->io_base_phys = 0;
619 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
621 pci_space = ranges[0];
622 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
623 cpu_phys_addr = of_translate_address(dev, &ranges[3]);
624 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
629 /* Now consume following elements while they are contiguous */
630 while (rlen >= np * sizeof(unsigned int)) {
631 unsigned long addr, phys;
633 if (ranges[0] != pci_space)
635 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
638 phys = (phys << 32) | ranges[4];
639 if (addr != pci_addr + size ||
640 phys != cpu_phys_addr + size)
643 size += ((unsigned long)ranges[na+3] << 32)
646 rlen -= np * sizeof(unsigned int);
649 switch ((pci_space >> 24) & 0x3) {
650 case 1: /* I/O space */
651 hose->io_base_phys = cpu_phys_addr - pci_addr;
652 /* handle from 0 to top of I/O window */
653 hose->pci_io_size = pci_addr + size;
655 res = &hose->io_resource;
656 res->flags = IORESOURCE_IO;
657 res->start = pci_addr;
658 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
659 res->start, res->start + size - 1);
661 case 2: /* memory space */
663 while (memno < 3 && hose->mem_resources[memno].flags)
667 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
669 res = &hose->mem_resources[memno];
670 res->flags = IORESOURCE_MEM;
671 res->start = cpu_phys_addr;
672 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
673 res->start, res->start + size - 1);
678 res->name = dev->full_name;
679 res->end = res->start + size - 1;
687 #ifdef CONFIG_HOTPLUG
689 int pcibios_unmap_io_space(struct pci_bus *bus)
691 struct pci_controller *hose;
693 WARN_ON(bus == NULL);
695 /* If this is not a PHB, we only flush the hash table over
696 * the area mapped by this bridge. We don't play with the PTE
697 * mappings since we might have to deal with sub-page alignemnts
698 * so flushing the hash table is the only sane way to make sure
699 * that no hash entries are covering that removed bridge area
700 * while still allowing other busses overlapping those pages
703 struct resource *res = bus->resource[0];
705 DBG("IO unmapping for PCI-PCI bridge %s\n",
706 pci_name(bus->self));
708 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
709 res->end - res->start + 1);
713 /* Get the host bridge */
714 hose = pci_bus_to_host(bus);
716 /* Check if we have IOs allocated */
717 if (hose->io_base_alloc == 0)
720 DBG("IO unmapping for PHB %s\n",
721 ((struct device_node *)hose->arch_data)->full_name);
722 DBG(" alloc=0x%p\n", hose->io_base_alloc);
724 /* This is a PHB, we fully unmap the IO area */
725 vunmap(hose->io_base_alloc);
729 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
731 #endif /* CONFIG_HOTPLUG */
733 int __devinit pcibios_map_io_space(struct pci_bus *bus)
735 struct vm_struct *area;
736 unsigned long phys_page;
737 unsigned long size_page;
738 unsigned long io_virt_offset;
739 struct pci_controller *hose;
741 WARN_ON(bus == NULL);
743 /* If this not a PHB, nothing to do, page tables still exist and
744 * thus HPTEs will be faulted in when needed
747 DBG("IO mapping for PCI-PCI bridge %s\n",
748 pci_name(bus->self));
749 DBG(" virt=0x%016lx...0x%016lx\n",
750 bus->resource[0]->start + _IO_BASE,
751 bus->resource[0]->end + _IO_BASE);
755 /* Get the host bridge */
756 hose = pci_bus_to_host(bus);
757 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
758 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
760 /* Make sure IO area address is clear */
761 hose->io_base_alloc = NULL;
763 /* If there's no IO to map on that bus, get away too */
764 if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
767 /* Let's allocate some IO space for that guy. We don't pass
768 * VM_IOREMAP because we don't care about alignment tricks that
769 * the core does in that case. Maybe we should due to stupid card
770 * with incomplete address decoding but I'd rather not deal with
771 * those outside of the reserved 64K legacy region.
773 area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
776 hose->io_base_alloc = area->addr;
777 hose->io_base_virt = (void __iomem *)(area->addr +
778 hose->io_base_phys - phys_page);
780 DBG("IO mapping for PHB %s\n",
781 ((struct device_node *)hose->arch_data)->full_name);
782 DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
783 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
784 DBG(" size=0x%016lx (alloc=0x%016lx)\n",
785 hose->pci_io_size, size_page);
787 /* Establish the mapping */
788 if (__ioremap_at(phys_page, area->addr, size_page,
789 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
792 /* Fixup hose IO resource */
793 io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
794 hose->io_resource.start += io_virt_offset;
795 hose->io_resource.end += io_virt_offset;
797 DBG(" hose->io_resource=0x%016lx...0x%016lx\n",
798 hose->io_resource.start, hose->io_resource.end);
802 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
804 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
806 struct pci_controller *hose = pci_bus_to_host(dev->bus);
807 unsigned long offset;
809 if (res->flags & IORESOURCE_IO) {
810 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
811 res->start += offset;
813 } else if (res->flags & IORESOURCE_MEM) {
814 res->start += hose->pci_mem_offset;
815 res->end += hose->pci_mem_offset;
819 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
822 /* Update device resources. */
825 DBG("%s: Fixup resources:\n", pci_name(dev));
826 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
827 struct resource *res = &dev->resource[i];
831 DBG(" 0x%02x < %08lx:0x%016lx...0x%016lx\n",
832 i, res->flags, res->start, res->end);
834 fixup_resource(res, dev);
836 DBG(" > %08lx:0x%016lx...0x%016lx\n",
837 res->flags, res->start, res->end);
840 EXPORT_SYMBOL(pcibios_fixup_device_resources);
842 void __devinit pcibios_setup_new_device(struct pci_dev *dev)
844 struct dev_archdata *sd = &dev->dev.archdata;
846 sd->of_node = pci_device_to_OF_node(dev);
848 DBG("PCI device %s OF node: %s\n", pci_name(dev),
849 sd->of_node ? sd->of_node->full_name : "<none>");
851 sd->dma_ops = pci_dma_ops;
853 sd->numa_node = pcibus_to_node(dev->bus);
857 if (ppc_md.pci_dma_dev_setup)
858 ppc_md.pci_dma_dev_setup(dev);
860 EXPORT_SYMBOL(pcibios_setup_new_device);
862 static void __devinit do_bus_setup(struct pci_bus *bus)
866 if (ppc_md.pci_dma_bus_setup)
867 ppc_md.pci_dma_bus_setup(bus);
869 list_for_each_entry(dev, &bus->devices, bus_list)
870 pcibios_setup_new_device(dev);
872 /* Read default IRQs and fixup if necessary */
873 list_for_each_entry(dev, &bus->devices, bus_list) {
874 pci_read_irq_line(dev);
875 if (ppc_md.pci_irq_fixup)
876 ppc_md.pci_irq_fixup(dev);
880 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
882 struct pci_dev *dev = bus->self;
883 struct device_node *np;
885 np = pci_bus_to_OF_node(bus);
887 DBG("pcibios_fixup_bus(%s)\n", np ? np->full_name : "<???>");
889 if (dev && pci_probe_only &&
890 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
891 /* This is a subordinate bridge */
893 pci_read_bridge_bases(bus);
894 pcibios_fixup_device_resources(dev, bus);
902 list_for_each_entry(dev, &bus->devices, bus_list)
903 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
904 pcibios_fixup_device_resources(dev, bus);
906 EXPORT_SYMBOL(pcibios_fixup_bus);
908 unsigned long pci_address_to_pio(phys_addr_t address)
910 struct pci_controller *hose, *tmp;
912 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
913 if (address >= hose->io_base_phys &&
914 address < (hose->io_base_phys + hose->pci_io_size)) {
916 (unsigned long)hose->io_base_virt - _IO_BASE;
917 return base + (address - hose->io_base_phys);
920 return (unsigned int)-1;
922 EXPORT_SYMBOL_GPL(pci_address_to_pio);
925 #define IOBASE_BRIDGE_NUMBER 0
926 #define IOBASE_MEMORY 1
928 #define IOBASE_ISA_IO 3
929 #define IOBASE_ISA_MEM 4
931 long sys_pciconfig_iobase(long which, unsigned long in_bus,
932 unsigned long in_devfn)
934 struct pci_controller* hose;
935 struct list_head *ln;
936 struct pci_bus *bus = NULL;
937 struct device_node *hose_node;
939 /* Argh ! Please forgive me for that hack, but that's the
940 * simplest way to get existing XFree to not lockup on some
941 * G5 machines... So when something asks for bus 0 io base
942 * (bus 0 is HT root), we return the AGP one instead.
944 if (machine_is_compatible("MacRISC4"))
948 /* That syscall isn't quite compatible with PCI domains, but it's
949 * used on pre-domains setup. We return the first match
952 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
954 if (in_bus >= bus->number && in_bus <= bus->subordinate)
958 if (bus == NULL || bus->sysdata == NULL)
961 hose_node = (struct device_node *)bus->sysdata;
962 hose = PCI_DN(hose_node)->phb;
965 case IOBASE_BRIDGE_NUMBER:
966 return (long)hose->first_busno;
968 return (long)hose->pci_mem_offset;
970 return (long)hose->io_base_phys;
972 return (long)isa_io_base;
981 int pcibus_to_node(struct pci_bus *bus)
983 struct pci_controller *phb = pci_bus_to_host(bus);
986 EXPORT_SYMBOL(pcibus_to_node);