arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/init.h>
  29 #include <linux/prctl.h>
  30 #include <linux/init_task.h>
  31 #include <linux/export.h>
  32 #include <linux/kallsyms.h>
  33 #include <linux/mqueue.h>
  34 #include <linux/hardirq.h>
  35 #include <linux/utsname.h>
  36 #include <linux/ftrace.h>
  37 #include <linux/kernel_stat.h>
  38 #include <linux/personality.h>
  39 #include <linux/random.h>
  40 #include <linux/hw_breakpoint.h>
  41
  42 #include <asm/pgtable.h>
  43 #include <asm/uaccess.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <linux/kprobes.h>
  59 #include <linux/kdebug.h>
  60
  61 /* Transactional Memory debug */
  62 #ifdef TM_DEBUG_SW
  63 #define TM_DEBUG(x...) printk(KERN_INFO x)
  64 #else
  65 #define TM_DEBUG(x...) do { } while(0)
  66 #endif
  67
  68 extern unsigned long _get_SP(void);
  69
  70 #ifndef CONFIG_SMP
  71 struct task_struct *last_task_used_math = NULL;
  72 struct task_struct *last_task_used_altivec = NULL;
  73 struct task_struct *last_task_used_vsx = NULL;
  74 struct task_struct *last_task_used_spe = NULL;
  75 #endif
  76
  77 #ifdef CONFIG_PPC_FPU
  78 /*
  79  * Make sure the floating-point register state in the
  80  * the thread_struct is up to date for task tsk.
  81  */
  82 void flush_fp_to_thread(struct task_struct *tsk)
  83 {
  84         if (tsk->thread.regs) {
  85                 /*
  86                  * We need to disable preemption here because if we didn't,
  87                  * another process could get scheduled after the regs->msr
  88                  * test but before we have finished saving the FP registers
  89                  * to the thread_struct.  That process could take over the
  90                  * FPU, and then when we get scheduled again we would store
  91                  * bogus values for the remaining FP registers.
  92                  */
  93                 preempt_disable();
  94                 if (tsk->thread.regs->msr & MSR_FP) {
  95 #ifdef CONFIG_SMP
  96                         /*
  97                          * This should only ever be called for current or
  98                          * for a stopped child process.  Since we save away
  99                          * the FP register state on context switch on SMP,
 100                          * there is something wrong if a stopped child appears
 101                          * to still have its FP state in the CPU registers.
 102                          */
 103                         BUG_ON(tsk != current);
 104 #endif
 105                         giveup_fpu(tsk);
 106                 }
 107                 preempt_enable();
 108         }
 109 }
 110 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 111 #endif
 112
 113 void enable_kernel_fp(void)
 114 {
 115         WARN_ON(preemptible());
 116
 117 #ifdef CONFIG_SMP
 118         if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
 119                 giveup_fpu(current);
 120         else
 121                 giveup_fpu(NULL);       /* just enables FP for kernel */
 122 #else
 123         giveup_fpu(last_task_used_math);
 124 #endif /* CONFIG_SMP */
 125 }
 126 EXPORT_SYMBOL(enable_kernel_fp);
 127
 128 #ifdef CONFIG_ALTIVEC
 129 void enable_kernel_altivec(void)
 130 {
 131         WARN_ON(preemptible());
 132
 133 #ifdef CONFIG_SMP
 134         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
 135                 giveup_altivec(current);
 136         else
 137                 giveup_altivec_notask();
 138 #else
 139         giveup_altivec(last_task_used_altivec);
 140 #endif /* CONFIG_SMP */
 141 }
 142 EXPORT_SYMBOL(enable_kernel_altivec);
 143
 144 /*
 145  * Make sure the VMX/Altivec register state in the
 146  * the thread_struct is up to date for task tsk.
 147  */
 148 void flush_altivec_to_thread(struct task_struct *tsk)
 149 {
 150         if (tsk->thread.regs) {
 151                 preempt_disable();
 152                 if (tsk->thread.regs->msr & MSR_VEC) {
 153 #ifdef CONFIG_SMP
 154                         BUG_ON(tsk != current);
 155 #endif
 156                         giveup_altivec(tsk);
 157                 }
 158                 preempt_enable();
 159         }
 160 }
 161 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 162 #endif /* CONFIG_ALTIVEC */
 163
 164 #ifdef CONFIG_VSX
 165 #if 0
 166 /* not currently used, but some crazy RAID module might want to later */
 167 void enable_kernel_vsx(void)
 168 {
 169         WARN_ON(preemptible());
 170
 171 #ifdef CONFIG_SMP
 172         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
 173                 giveup_vsx(current);
 174         else
 175                 giveup_vsx(NULL);       /* just enable vsx for kernel - force */
 176 #else
 177         giveup_vsx(last_task_used_vsx);
 178 #endif /* CONFIG_SMP */
 179 }
 180 EXPORT_SYMBOL(enable_kernel_vsx);
 181 #endif
 182
 183 void giveup_vsx(struct task_struct *tsk)
 184 {
 185         giveup_fpu(tsk);
 186         giveup_altivec(tsk);
 187         __giveup_vsx(tsk);
 188 }
 189
 190 void flush_vsx_to_thread(struct task_struct *tsk)
 191 {
 192         if (tsk->thread.regs) {
 193                 preempt_disable();
 194                 if (tsk->thread.regs->msr & MSR_VSX) {
 195 #ifdef CONFIG_SMP
 196                         BUG_ON(tsk != current);
 197 #endif
 198                         giveup_vsx(tsk);
 199                 }
 200                 preempt_enable();
 201         }
 202 }
 203 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 204 #endif /* CONFIG_VSX */
 205
 206 #ifdef CONFIG_SPE
 207
 208 void enable_kernel_spe(void)
 209 {
 210         WARN_ON(preemptible());
 211
 212 #ifdef CONFIG_SMP
 213         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
 214                 giveup_spe(current);
 215         else
 216                 giveup_spe(NULL);       /* just enable SPE for kernel - force */
 217 #else
 218         giveup_spe(last_task_used_spe);
 219 #endif /* __SMP __ */
 220 }
 221 EXPORT_SYMBOL(enable_kernel_spe);
 222
 223 void flush_spe_to_thread(struct task_struct *tsk)
 224 {
 225         if (tsk->thread.regs) {
 226                 preempt_disable();
 227                 if (tsk->thread.regs->msr & MSR_SPE) {
 228 #ifdef CONFIG_SMP
 229                         BUG_ON(tsk != current);
 230 #endif
 231                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 232                         giveup_spe(tsk);
 233                 }
 234                 preempt_enable();
 235         }
 236 }
 237 #endif /* CONFIG_SPE */
 238
 239 #ifndef CONFIG_SMP
 240 /*
 241  * If we are doing lazy switching of CPU state (FP, altivec or SPE),
 242  * and the current task has some state, discard it.
 243  */
 244 void discard_lazy_cpu_state(void)
 245 {
 246         preempt_disable();
 247         if (last_task_used_math == current)
 248                 last_task_used_math = NULL;
 249 #ifdef CONFIG_ALTIVEC
 250         if (last_task_used_altivec == current)
 251                 last_task_used_altivec = NULL;
 252 #endif /* CONFIG_ALTIVEC */
 253 #ifdef CONFIG_VSX
 254         if (last_task_used_vsx == current)
 255                 last_task_used_vsx = NULL;
 256 #endif /* CONFIG_VSX */
 257 #ifdef CONFIG_SPE
 258         if (last_task_used_spe == current)
 259                 last_task_used_spe = NULL;
 260 #endif
 261         preempt_enable();
 262 }
 263 #endif /* CONFIG_SMP */
 264
 265 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 266 void do_send_trap(struct pt_regs *regs, unsigned long address,
 267                   unsigned long error_code, int signal_code, int breakpt)
 268 {
 269         siginfo_t info;
 270
 271         current->thread.trap_nr = signal_code;
 272         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 273                         11, SIGSEGV) == NOTIFY_STOP)
 274                 return;
 275
 276         /* Deliver the signal to userspace */
 277         info.si_signo = SIGTRAP;
 278         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 279         info.si_code = signal_code;
 280         info.si_addr = (void __user *)address;
 281         force_sig_info(SIGTRAP, &info, current);
 282 }
 283 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 284 void do_break (struct pt_regs *regs, unsigned long address,
 285                     unsigned long error_code)
 286 {
 287         siginfo_t info;
 288
 289         current->thread.trap_nr = TRAP_HWBKPT;
 290         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 291                         11, SIGSEGV) == NOTIFY_STOP)
 292                 return;
 293
 294         if (debugger_break_match(regs))
 295                 return;
 296
 297         /* Clear the breakpoint */
 298         hw_breakpoint_disable();
 299
 300         /* Deliver the signal to userspace */
 301         info.si_signo = SIGTRAP;
 302         info.si_errno = 0;
 303         info.si_code = TRAP_HWBKPT;
 304         info.si_addr = (void __user *)address;
 305         force_sig_info(SIGTRAP, &info, current);
 306 }
 307 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 308
 309 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 310
 311 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 312 /*
 313  * Set the debug registers back to their default "safe" values.
 314  */
 315 static void set_debug_reg_defaults(struct thread_struct *thread)
 316 {
 317         thread->iac1 = thread->iac2 = 0;
 318 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 319         thread->iac3 = thread->iac4 = 0;
 320 #endif
 321         thread->dac1 = thread->dac2 = 0;
 322 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 323         thread->dvc1 = thread->dvc2 = 0;
 324 #endif
 325         thread->dbcr0 = 0;
 326 #ifdef CONFIG_BOOKE
 327         /*
 328          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 329          */
 330         thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 331                         DBCR1_IAC3US | DBCR1_IAC4US;
 332         /*
 333          * Force Data Address Compare User/Supervisor bits to be User-only
 334          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 335          */
 336         thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 337 #else
 338         thread->dbcr1 = 0;
 339 #endif
 340 }
 341
 342 static void prime_debug_regs(struct thread_struct *thread)
 343 {
 344         /*
 345          * We could have inherited MSR_DE from userspace, since
 346          * it doesn't get cleared on exception entry.  Make sure
 347          * MSR_DE is clear before we enable any debug events.
 348          */
 349         mtmsr(mfmsr() & ~MSR_DE);
 350
 351         mtspr(SPRN_IAC1, thread->iac1);
 352         mtspr(SPRN_IAC2, thread->iac2);
 353 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 354         mtspr(SPRN_IAC3, thread->iac3);
 355         mtspr(SPRN_IAC4, thread->iac4);
 356 #endif
 357         mtspr(SPRN_DAC1, thread->dac1);
 358         mtspr(SPRN_DAC2, thread->dac2);
 359 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 360         mtspr(SPRN_DVC1, thread->dvc1);
 361         mtspr(SPRN_DVC2, thread->dvc2);
 362 #endif
 363         mtspr(SPRN_DBCR0, thread->dbcr0);
 364         mtspr(SPRN_DBCR1, thread->dbcr1);
 365 #ifdef CONFIG_BOOKE
 366         mtspr(SPRN_DBCR2, thread->dbcr2);
 367 #endif
 368 }
 369 /*
 370  * Unless neither the old or new thread are making use of the
 371  * debug registers, set the debug registers from the values
 372  * stored in the new thread.
 373  */
 374 static void switch_booke_debug_regs(struct thread_struct *new_thread)
 375 {
 376         if ((current->thread.dbcr0 & DBCR0_IDM)
 377                 || (new_thread->dbcr0 & DBCR0_IDM))
 378                         prime_debug_regs(new_thread);
 379 }
 380 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 381 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 382 static void set_debug_reg_defaults(struct thread_struct *thread)
 383 {
 384         thread->hw_brk.address = 0;
 385         thread->hw_brk.type = 0;
 386         set_breakpoint(&thread->hw_brk);
 387 }
 388 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 389 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 390
 391 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 392 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 393 {
 394         mtspr(SPRN_DAC1, dabr);
 395 #ifdef CONFIG_PPC_47x
 396         isync();
 397 #endif
 398         return 0;
 399 }
 400 #elif defined(CONFIG_PPC_BOOK3S)
 401 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 402 {
 403         mtspr(SPRN_DABR, dabr);
 404         if (cpu_has_feature(CPU_FTR_DABRX))
 405                 mtspr(SPRN_DABRX, dabrx);
 406         return 0;
 407 }
 408 #else
 409 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 410 {
 411         return -EINVAL;
 412 }
 413 #endif
 414
 415 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 416 {
 417         unsigned long dabr, dabrx;
 418
 419         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 420         dabrx = ((brk->type >> 3) & 0x7);
 421
 422         if (ppc_md.set_dabr)
 423                 return ppc_md.set_dabr(dabr, dabrx);
 424
 425         return __set_dabr(dabr, dabrx);
 426 }
 427
 428 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 429 {
 430         unsigned long dawr, dawrx, mrd;
 431
 432         dawr = brk->address;
 433
 434         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 435                                    << (63 - 58); //* read/write bits */
 436         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 437                                    << (63 - 59); //* translate */
 438         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 439                                    >> 3; //* PRIM bits */
 440         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 441            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 442            0b111111=64DW.
 443            brk->len is in bytes.
 444            This aligns up to double word size, shifts and does the bias.
 445         */
 446         mrd = ((brk->len + 7) >> 3) - 1;
 447         dawrx |= (mrd & 0x3f) << (63 - 53);
 448
 449         if (ppc_md.set_dawr)
 450                 return ppc_md.set_dawr(dawr, dawrx);
 451         mtspr(SPRN_DAWR, dawr);
 452         mtspr(SPRN_DAWRX, dawrx);
 453         return 0;
 454 }
 455
 456 int set_breakpoint(struct arch_hw_breakpoint *brk)
 457 {
 458         __get_cpu_var(current_brk) = *brk;
 459
 460         if (cpu_has_feature(CPU_FTR_DAWR))
 461                 return set_dawr(brk);
 462
 463         return set_dabr(brk);
 464 }
 465
 466 #ifdef CONFIG_PPC64
 467 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 468 #endif
 469
 470 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 471                               struct arch_hw_breakpoint *b)
 472 {
 473         if (a->address != b->address)
 474                 return false;
 475         if (a->type != b->type)
 476                 return false;
 477         if (a->len != b->len)
 478                 return false;
 479         return true;
 480 }
 481 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 482 static inline void tm_reclaim_task(struct task_struct *tsk)
 483 {
 484         /* We have to work out if we're switching from/to a task that's in the
 485          * middle of a transaction.
 486          *
 487          * In switching we need to maintain a 2nd register state as
 488          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 489          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 490          * (current) FPRs into oldtask->thread.transact_fpr[].
 491          *
 492          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 493          */
 494         struct thread_struct *thr = &tsk->thread;
 495
 496         if (!thr->regs)
 497                 return;
 498
 499         if (!MSR_TM_ACTIVE(thr->regs->msr))
 500                 goto out_and_saveregs;
 501
 502         /* Stash the original thread MSR, as giveup_fpu et al will
 503          * modify it.  We hold onto it to see whether the task used
 504          * FP & vector regs.
 505          */
 506         thr->tm_orig_msr = thr->regs->msr;
 507
 508         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 509                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 510                  tsk->pid, thr->regs->nip,
 511                  thr->regs->ccr, thr->regs->msr,
 512                  thr->regs->trap);
 513
 514         tm_reclaim(thr, thr->regs->msr, TM_CAUSE_RESCHED);
 515
 516         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 517                  tsk->pid);
 518
 519 out_and_saveregs:
 520         /* Always save the regs here, even if a transaction's not active.
 521          * This context-switches a thread's TM info SPRs.  We do it here to
 522          * be consistent with the restore path (in recheckpoint) which
 523          * cannot happen later in _switch().
 524          */
 525         tm_save_sprs(thr);
 526 }
 527
 528 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 529 {
 530         unsigned long msr;
 531
 532         if (!cpu_has_feature(CPU_FTR_TM))
 533                 return;
 534
 535         /* Recheckpoint the registers of the thread we're about to switch to.
 536          *
 537          * If the task was using FP, we non-lazily reload both the original and
 538          * the speculative FP register states.  This is because the kernel
 539          * doesn't see if/when a TM rollback occurs, so if we take an FP
 540          * unavoidable later, we are unable to determine which set of FP regs
 541          * need to be restored.
 542          */
 543         if (!new->thread.regs)
 544                 return;
 545
 546         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 547          * before the trecheckpoint and no explosion occurs.
 548          */
 549         tm_restore_sprs(&new->thread);
 550
 551         if (!MSR_TM_ACTIVE(new->thread.regs->msr))
 552                 return;
 553         msr = new->thread.tm_orig_msr;
 554         /* Recheckpoint to restore original checkpointed register state. */
 555         TM_DEBUG("*** tm_recheckpoint of pid %d "
 556                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 557                  new->pid, new->thread.regs->msr, msr);
 558
 559         /* This loads the checkpointed FP/VEC state, if used */
 560         tm_recheckpoint(&new->thread, msr);
 561
 562         /* This loads the speculative FP/VEC state, if used */
 563         if (msr & MSR_FP) {
 564                 do_load_up_transact_fpu(&new->thread);
 565                 new->thread.regs->msr |=
 566                         (MSR_FP | new->thread.fpexc_mode);
 567         }
 568 #ifdef CONFIG_ALTIVEC
 569         if (msr & MSR_VEC) {
 570                 do_load_up_transact_altivec(&new->thread);
 571                 new->thread.regs->msr |= MSR_VEC;
 572         }
 573 #endif
 574         /* We may as well turn on VSX too since all the state is restored now */
 575         if (msr & MSR_VSX)
 576                 new->thread.regs->msr |= MSR_VSX;
 577
 578         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 579                  "(kernel msr 0x%lx)\n",
 580                  new->pid, mfmsr());
 581 }
 582
 583 static inline void __switch_to_tm(struct task_struct *prev)
 584 {
 585         if (cpu_has_feature(CPU_FTR_TM)) {
 586                 tm_enable();
 587                 tm_reclaim_task(prev);
 588         }
 589 }
 590 #else
 591 #define tm_recheckpoint_new_task(new)
 592 #define __switch_to_tm(prev)
 593 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 594
 595 struct task_struct *__switch_to(struct task_struct *prev,
 596         struct task_struct *new)
 597 {
 598         struct thread_struct *new_thread, *old_thread;
 599         unsigned long flags;
 600         struct task_struct *last;
 601 #ifdef CONFIG_PPC_BOOK3S_64
 602         struct ppc64_tlb_batch *batch;
 603 #endif
 604
 605         /* Back up the TAR across context switches.
 606          * Note that the TAR is not available for use in the kernel.  (To
 607          * provide this, the TAR should be backed up/restored on exception
 608          * entry/exit instead, and be in pt_regs.  FIXME, this should be in
 609          * pt_regs anyway (for debug).)
 610          * Save the TAR here before we do treclaim/trecheckpoint as these
 611          * will change the TAR.
 612          */
 613         save_tar(&prev->thread);
 614
 615         __switch_to_tm(prev);
 616
 617 #ifdef CONFIG_SMP
 618         /* avoid complexity of lazy save/restore of fpu
 619          * by just saving it every time we switch out if
 620          * this task used the fpu during the last quantum.
 621          *
 622          * If it tries to use the fpu again, it'll trap and
 623          * reload its fp regs.  So we don't have to do a restore
 624          * every switch, just a save.
 625          *  -- Cort
 626          */
 627         if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
 628                 giveup_fpu(prev);
 629 #ifdef CONFIG_ALTIVEC
 630         /*
 631          * If the previous thread used altivec in the last quantum
 632          * (thus changing altivec regs) then save them.
 633          * We used to check the VRSAVE register but not all apps
 634          * set it, so we don't rely on it now (and in fact we need
 635          * to save & restore VSCR even if VRSAVE == 0).  -- paulus
 636          *
 637          * On SMP we always save/restore altivec regs just to avoid the
 638          * complexity of changing processors.
 639          *  -- Cort
 640          */
 641         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
 642                 giveup_altivec(prev);
 643 #endif /* CONFIG_ALTIVEC */
 644 #ifdef CONFIG_VSX
 645         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
 646                 /* VMX and FPU registers are already save here */
 647                 __giveup_vsx(prev);
 648 #endif /* CONFIG_VSX */
 649 #ifdef CONFIG_SPE
 650         /*
 651          * If the previous thread used spe in the last quantum
 652          * (thus changing spe regs) then save them.
 653          *
 654          * On SMP we always save/restore spe regs just to avoid the
 655          * complexity of changing processors.
 656          */
 657         if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
 658                 giveup_spe(prev);
 659 #endif /* CONFIG_SPE */
 660
 661 #else  /* CONFIG_SMP */
 662 #ifdef CONFIG_ALTIVEC
 663         /* Avoid the trap.  On smp this this never happens since
 664          * we don't set last_task_used_altivec -- Cort
 665          */
 666         if (new->thread.regs && last_task_used_altivec == new)
 667                 new->thread.regs->msr |= MSR_VEC;
 668 #endif /* CONFIG_ALTIVEC */
 669 #ifdef CONFIG_VSX
 670         if (new->thread.regs && last_task_used_vsx == new)
 671                 new->thread.regs->msr |= MSR_VSX;
 672 #endif /* CONFIG_VSX */
 673 #ifdef CONFIG_SPE
 674         /* Avoid the trap.  On smp this this never happens since
 675          * we don't set last_task_used_spe
 676          */
 677         if (new->thread.regs && last_task_used_spe == new)
 678                 new->thread.regs->msr |= MSR_SPE;
 679 #endif /* CONFIG_SPE */
 680
 681 #endif /* CONFIG_SMP */
 682
 683 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 684         switch_booke_debug_regs(&new->thread);
 685 #else
 686 /*
 687  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
 688  * schedule DABR
 689  */
 690 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 691         if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
 692                 set_breakpoint(&new->thread.hw_brk);
 693 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 694 #endif
 695
 696
 697         new_thread = &new->thread;
 698         old_thread = &current->thread;
 699
 700 #ifdef CONFIG_PPC64
 701         /*
 702          * Collect processor utilization data per process
 703          */
 704         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
 705                 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
 706                 long unsigned start_tb, current_tb;
 707                 start_tb = old_thread->start_tb;
 708                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
 709                 old_thread->accum_tb += (current_tb - start_tb);
 710                 new_thread->start_tb = current_tb;
 711         }
 712 #endif /* CONFIG_PPC64 */
 713
 714 #ifdef CONFIG_PPC_BOOK3S_64
 715         batch = &__get_cpu_var(ppc64_tlb_batch);
 716         if (batch->active) {
 717                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
 718                 if (batch->index)
 719                         __flush_tlb_pending(batch);
 720                 batch->active = 0;
 721         }
 722 #endif /* CONFIG_PPC_BOOK3S_64 */
 723
 724         local_irq_save(flags);
 725
 726         /*
 727          * We can't take a PMU exception inside _switch() since there is a
 728          * window where the kernel stack SLB and the kernel stack are out
 729          * of sync. Hard disable here.
 730          */
 731         hard_irq_disable();
 732
 733         tm_recheckpoint_new_task(new);
 734
 735         last = _switch(old_thread, new_thread);
 736
 737 #ifdef CONFIG_PPC_BOOK3S_64
 738         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
 739                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
 740                 batch = &__get_cpu_var(ppc64_tlb_batch);
 741                 batch->active = 1;
 742         }
 743 #endif /* CONFIG_PPC_BOOK3S_64 */
 744
 745         local_irq_restore(flags);
 746
 747         return last;
 748 }
 749
 750 static int instructions_to_print = 16;
 751
 752 static void show_instructions(struct pt_regs *regs)
 753 {
 754         int i;
 755         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
 756                         sizeof(int));
 757
 758         printk("Instruction dump:");
 759
 760         for (i = 0; i < instructions_to_print; i++) {
 761                 int instr;
 762
 763                 if (!(i % 8))
 764                         printk("\n");
 765
 766 #if !defined(CONFIG_BOOKE)
 767                 /* If executing with the IMMU off, adjust pc rather
 768                  * than print XXXXXXXX.
 769                  */
 770                 if (!(regs->msr & MSR_IR))
 771                         pc = (unsigned long)phys_to_virt(pc);
 772 #endif
 773
 774                 /* We use __get_user here *only* to avoid an OOPS on a
 775                  * bad address because the pc *should* only be a
 776                  * kernel address.
 777                  */
 778                 if (!__kernel_text_address(pc) ||
 779                      __get_user(instr, (unsigned int __user *)pc)) {
 780                         printk(KERN_CONT "XXXXXXXX ");
 781                 } else {
 782                         if (regs->nip == pc)
 783                                 printk(KERN_CONT "<%08x> ", instr);
 784                         else
 785                                 printk(KERN_CONT "%08x ", instr);
 786                 }
 787
 788                 pc += sizeof(int);
 789         }
 790
 791         printk("\n");
 792 }
 793
 794 static struct regbit {
 795         unsigned long bit;
 796         const char *name;
 797 } msr_bits[] = {
 798 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
 799         {MSR_SF,        "SF"},
 800         {MSR_HV,        "HV"},
 801 #endif
 802         {MSR_VEC,       "VEC"},
 803         {MSR_VSX,       "VSX"},
 804 #ifdef CONFIG_BOOKE
 805         {MSR_CE,        "CE"},
 806 #endif
 807         {MSR_EE,        "EE"},
 808         {MSR_PR,        "PR"},
 809         {MSR_FP,        "FP"},
 810         {MSR_ME,        "ME"},
 811 #ifdef CONFIG_BOOKE
 812         {MSR_DE,        "DE"},
 813 #else
 814         {MSR_SE,        "SE"},
 815         {MSR_BE,        "BE"},
 816 #endif
 817         {MSR_IR,        "IR"},
 818         {MSR_DR,        "DR"},
 819         {MSR_PMM,       "PMM"},
 820 #ifndef CONFIG_BOOKE
 821         {MSR_RI,        "RI"},
 822         {MSR_LE,        "LE"},
 823 #endif
 824         {0,             NULL}
 825 };
 826
 827 static void printbits(unsigned long val, struct regbit *bits)
 828 {
 829         const char *sep = "";
 830
 831         printk("<");
 832         for (; bits->bit; ++bits)
 833                 if (val & bits->bit) {
 834                         printk("%s%s", sep, bits->name);
 835                         sep = ",";
 836                 }
 837         printk(">");
 838 }
 839
 840 #ifdef CONFIG_PPC64
 841 #define REG             "%016lx"
 842 #define REGS_PER_LINE   4
 843 #define LAST_VOLATILE   13
 844 #else
 845 #define REG             "%08lx"
 846 #define REGS_PER_LINE   8
 847 #define LAST_VOLATILE   12
 848 #endif
 849
 850 void show_regs(struct pt_regs * regs)
 851 {
 852         int i, trap;
 853
 854         show_regs_print_info(KERN_DEFAULT);
 855
 856         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
 857                regs->nip, regs->link, regs->ctr);
 858         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
 859                regs, regs->trap, print_tainted(), init_utsname()->release);
 860         printk("MSR: "REG" ", regs->msr);
 861         printbits(regs->msr, msr_bits);
 862         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
 863 #ifdef CONFIG_PPC64
 864         printk("SOFTE: %ld\n", regs->softe);
 865 #endif
 866         trap = TRAP(regs);
 867         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
 868                 printk("CFAR: "REG"\n", regs->orig_gpr3);
 869         if (trap == 0x300 || trap == 0x600)
 870 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
 871                 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
 872 #else
 873                 printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
 874 #endif
 875
 876         for (i = 0;  i < 32;  i++) {
 877                 if ((i % REGS_PER_LINE) == 0)
 878                         printk("\nGPR%02d: ", i);
 879                 printk(REG " ", regs->gpr[i]);
 880                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
 881                         break;
 882         }
 883         printk("\n");
 884 #ifdef CONFIG_KALLSYMS
 885         /*
 886          * Lookup NIP late so we have the best change of getting the
 887          * above info out without failing
 888          */
 889         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
 890         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
 891 #endif
 892 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 893         printk("PACATMSCRATCH [%llx]\n", get_paca()->tm_scratch);
 894 #endif
 895         show_stack(current, (unsigned long *) regs->gpr[1]);
 896         if (!user_mode(regs))
 897                 show_instructions(regs);
 898 }
 899
 900 void exit_thread(void)
 901 {
 902         discard_lazy_cpu_state();
 903 }
 904
 905 void flush_thread(void)
 906 {
 907         discard_lazy_cpu_state();
 908
 909 #ifdef CONFIG_HAVE_HW_BREAKPOINT
 910         flush_ptrace_hw_breakpoint(current);
 911 #else /* CONFIG_HAVE_HW_BREAKPOINT */
 912         set_debug_reg_defaults(&current->thread);
 913 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 914 }
 915
 916 void
 917 release_thread(struct task_struct *t)
 918 {
 919 }
 920
 921 /*
 922  * this gets called so that we can store coprocessor state into memory and
 923  * copy the current task into the new thread.
 924  */
 925 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
 926 {
 927         flush_fp_to_thread(src);
 928         flush_altivec_to_thread(src);
 929         flush_vsx_to_thread(src);
 930         flush_spe_to_thread(src);
 931
 932         *dst = *src;
 933
 934         clear_task_ebb(dst);
 935
 936         return 0;
 937 }
 938
 939 /*
 940  * Copy a thread..
 941  */
 942 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
 943
 944 int copy_thread(unsigned long clone_flags, unsigned long usp,
 945                 unsigned long arg, struct task_struct *p)
 946 {
 947         struct pt_regs *childregs, *kregs;
 948         extern void ret_from_fork(void);
 949         extern void ret_from_kernel_thread(void);
 950         void (*f)(void);
 951         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
 952
 953         /* Copy registers */
 954         sp -= sizeof(struct pt_regs);
 955         childregs = (struct pt_regs *) sp;
 956         if (unlikely(p->flags & PF_KTHREAD)) {
 957                 struct thread_info *ti = (void *)task_stack_page(p);
 958                 memset(childregs, 0, sizeof(struct pt_regs));
 959                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
 960                 childregs->gpr[14] = usp;       /* function */
 961 #ifdef CONFIG_PPC64
 962                 clear_tsk_thread_flag(p, TIF_32BIT);
 963                 childregs->softe = 1;
 964 #endif
 965                 childregs->gpr[15] = arg;
 966                 p->thread.regs = NULL;  /* no user register state */
 967                 ti->flags |= _TIF_RESTOREALL;
 968                 f = ret_from_kernel_thread;
 969         } else {
 970                 struct pt_regs *regs = current_pt_regs();
 971                 CHECK_FULL_REGS(regs);
 972                 *childregs = *regs;
 973                 if (usp)
 974                         childregs->gpr[1] = usp;
 975                 p->thread.regs = childregs;
 976                 childregs->gpr[3] = 0;  /* Result from fork() */
 977                 if (clone_flags & CLONE_SETTLS) {
 978 #ifdef CONFIG_PPC64
 979                         if (!is_32bit_task())
 980                                 childregs->gpr[13] = childregs->gpr[6];
 981                         else
 982 #endif
 983                                 childregs->gpr[2] = childregs->gpr[6];
 984                 }
 985
 986                 f = ret_from_fork;
 987         }
 988         sp -= STACK_FRAME_OVERHEAD;
 989
 990         /*
 991          * The way this works is that at some point in the future
 992          * some task will call _switch to switch to the new task.
 993          * That will pop off the stack frame created below and start
 994          * the new task running at ret_from_fork.  The new task will
 995          * do some house keeping and then return from the fork or clone
 996          * system call, using the stack frame created above.
 997          */
 998         ((unsigned long *)sp)[0] = 0;
 999         sp -= sizeof(struct pt_regs);
1000         kregs = (struct pt_regs *) sp;
1001         sp -= STACK_FRAME_OVERHEAD;
1002         p->thread.ksp = sp;
1003 #ifdef CONFIG_PPC32
1004         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1005                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1006 #endif
1007 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1008         p->thread.ptrace_bps[0] = NULL;
1009 #endif
1010
1011         p->thread.fp_save_area = NULL;
1012 #ifdef CONFIG_ALTIVEC
1013         p->thread.vr_save_area = NULL;
1014 #endif
1015
1016 #ifdef CONFIG_PPC_STD_MMU_64
1017         if (mmu_has_feature(MMU_FTR_SLB)) {
1018                 unsigned long sp_vsid;
1019                 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1020
1021                 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1022                         sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1023                                 << SLB_VSID_SHIFT_1T;
1024                 else
1025                         sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1026                                 << SLB_VSID_SHIFT;
1027                 sp_vsid |= SLB_VSID_KERNEL | llp;
1028                 p->thread.ksp_vsid = sp_vsid;
1029         }
1030 #endif /* CONFIG_PPC_STD_MMU_64 */
1031 #ifdef CONFIG_PPC64
1032         if (cpu_has_feature(CPU_FTR_DSCR)) {
1033                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1034                 p->thread.dscr = current->thread.dscr;
1035         }
1036         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1037                 p->thread.ppr = INIT_PPR;
1038 #endif
1039         /*
1040          * The PPC64 ABI makes use of a TOC to contain function
1041          * pointers.  The function (ret_from_except) is actually a pointer
1042          * to the TOC entry.  The first entry is a pointer to the actual
1043          * function.
1044          */
1045 #ifdef CONFIG_PPC64
1046         kregs->nip = *((unsigned long *)f);
1047 #else
1048         kregs->nip = (unsigned long)f;
1049 #endif
1050         return 0;
1051 }
1052
1053 /*
1054  * Set up a thread for executing a new program
1055  */
1056 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1057 {
1058 #ifdef CONFIG_PPC64
1059         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1060 #endif
1061
1062         /*
1063          * If we exec out of a kernel thread then thread.regs will not be
1064          * set.  Do it now.
1065          */
1066         if (!current->thread.regs) {
1067                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1068                 current->thread.regs = regs - 1;
1069         }
1070
1071         memset(regs->gpr, 0, sizeof(regs->gpr));
1072         regs->ctr = 0;
1073         regs->link = 0;
1074         regs->xer = 0;
1075         regs->ccr = 0;
1076         regs->gpr[1] = sp;
1077
1078         /*
1079          * We have just cleared all the nonvolatile GPRs, so make
1080          * FULL_REGS(regs) return true.  This is necessary to allow
1081          * ptrace to examine the thread immediately after exec.
1082          */
1083         regs->trap &= ~1UL;
1084
1085 #ifdef CONFIG_PPC32
1086         regs->mq = 0;
1087         regs->nip = start;
1088         regs->msr = MSR_USER;
1089 #else
1090         if (!is_32bit_task()) {
1091                 unsigned long entry, toc;
1092
1093                 /* start is a relocated pointer to the function descriptor for
1094                  * the elf _start routine.  The first entry in the function
1095                  * descriptor is the entry address of _start and the second
1096                  * entry is the TOC value we need to use.
1097                  */
1098                 __get_user(entry, (unsigned long __user *)start);
1099                 __get_user(toc, (unsigned long __user *)start+1);
1100
1101                 /* Check whether the e_entry function descriptor entries
1102                  * need to be relocated before we can use them.
1103                  */
1104                 if (load_addr != 0) {
1105                         entry += load_addr;
1106                         toc   += load_addr;
1107                 }
1108                 regs->nip = entry;
1109                 regs->gpr[2] = toc;
1110                 regs->msr = MSR_USER64;
1111         } else {
1112                 regs->nip = start;
1113                 regs->gpr[2] = 0;
1114                 regs->msr = MSR_USER32;
1115         }
1116 #endif
1117         discard_lazy_cpu_state();
1118 #ifdef CONFIG_VSX
1119         current->thread.used_vsr = 0;
1120 #endif
1121         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1122         current->thread.fp_save_area = NULL;
1123 #ifdef CONFIG_ALTIVEC
1124         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1125         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1126         current->thread.vr_save_area = NULL;
1127         current->thread.vrsave = 0;
1128         current->thread.used_vr = 0;
1129 #endif /* CONFIG_ALTIVEC */
1130 #ifdef CONFIG_SPE
1131         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1132         current->thread.acc = 0;
1133         current->thread.spefscr = 0;
1134         current->thread.used_spe = 0;
1135 #endif /* CONFIG_SPE */
1136 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1137         if (cpu_has_feature(CPU_FTR_TM))
1138                 regs->msr |= MSR_TM;
1139         current->thread.tm_tfhar = 0;
1140         current->thread.tm_texasr = 0;
1141         current->thread.tm_tfiar = 0;
1142 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1143 }
1144
1145 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1146                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1147
1148 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1149 {
1150         struct pt_regs *regs = tsk->thread.regs;
1151
1152         /* This is a bit hairy.  If we are an SPE enabled  processor
1153          * (have embedded fp) we store the IEEE exception enable flags in
1154          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1155          * mode (asyn, precise, disabled) for 'Classic' FP. */
1156         if (val & PR_FP_EXC_SW_ENABLE) {
1157 #ifdef CONFIG_SPE
1158                 if (cpu_has_feature(CPU_FTR_SPE)) {
1159                         tsk->thread.fpexc_mode = val &
1160                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1161                         return 0;
1162                 } else {
1163                         return -EINVAL;
1164                 }
1165 #else
1166                 return -EINVAL;
1167 #endif
1168         }
1169
1170         /* on a CONFIG_SPE this does not hurt us.  The bits that
1171          * __pack_fe01 use do not overlap with bits used for
1172          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1173          * on CONFIG_SPE implementations are reserved so writing to
1174          * them does not change anything */
1175         if (val > PR_FP_EXC_PRECISE)
1176                 return -EINVAL;
1177         tsk->thread.fpexc_mode = __pack_fe01(val);
1178         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1179                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1180                         | tsk->thread.fpexc_mode;
1181         return 0;
1182 }
1183
1184 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1185 {
1186         unsigned int val;
1187
1188         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1189 #ifdef CONFIG_SPE
1190                 if (cpu_has_feature(CPU_FTR_SPE))
1191                         val = tsk->thread.fpexc_mode;
1192                 else
1193                         return -EINVAL;
1194 #else
1195                 return -EINVAL;
1196 #endif
1197         else
1198                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1199         return put_user(val, (unsigned int __user *) adr);
1200 }
1201
1202 int set_endian(struct task_struct *tsk, unsigned int val)
1203 {
1204         struct pt_regs *regs = tsk->thread.regs;
1205
1206         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1207             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1208                 return -EINVAL;
1209
1210         if (regs == NULL)
1211                 return -EINVAL;
1212
1213         if (val == PR_ENDIAN_BIG)
1214                 regs->msr &= ~MSR_LE;
1215         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1216                 regs->msr |= MSR_LE;
1217         else
1218                 return -EINVAL;
1219
1220         return 0;
1221 }
1222
1223 int get_endian(struct task_struct *tsk, unsigned long adr)
1224 {
1225         struct pt_regs *regs = tsk->thread.regs;
1226         unsigned int val;
1227
1228         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1229             !cpu_has_feature(CPU_FTR_REAL_LE))
1230                 return -EINVAL;
1231
1232         if (regs == NULL)
1233                 return -EINVAL;
1234
1235         if (regs->msr & MSR_LE) {
1236                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1237                         val = PR_ENDIAN_LITTLE;
1238                 else
1239                         val = PR_ENDIAN_PPC_LITTLE;
1240         } else
1241                 val = PR_ENDIAN_BIG;
1242
1243         return put_user(val, (unsigned int __user *)adr);
1244 }
1245
1246 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1247 {
1248         tsk->thread.align_ctl = val;
1249         return 0;
1250 }
1251
1252 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1253 {
1254         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1255 }
1256
1257 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1258                                   unsigned long nbytes)
1259 {
1260         unsigned long stack_page;
1261         unsigned long cpu = task_cpu(p);
1262
1263         /*
1264          * Avoid crashing if the stack has overflowed and corrupted
1265          * task_cpu(p), which is in the thread_info struct.
1266          */
1267         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1268                 stack_page = (unsigned long) hardirq_ctx[cpu];
1269                 if (sp >= stack_page + sizeof(struct thread_struct)
1270                     && sp <= stack_page + THREAD_SIZE - nbytes)
1271                         return 1;
1272
1273                 stack_page = (unsigned long) softirq_ctx[cpu];
1274                 if (sp >= stack_page + sizeof(struct thread_struct)
1275                     && sp <= stack_page + THREAD_SIZE - nbytes)
1276                         return 1;
1277         }
1278         return 0;
1279 }
1280
1281 int validate_sp(unsigned long sp, struct task_struct *p,
1282                        unsigned long nbytes)
1283 {
1284         unsigned long stack_page = (unsigned long)task_stack_page(p);
1285
1286         if (sp >= stack_page + sizeof(struct thread_struct)
1287             && sp <= stack_page + THREAD_SIZE - nbytes)
1288                 return 1;
1289
1290         return valid_irq_stack(sp, p, nbytes);
1291 }
1292
1293 EXPORT_SYMBOL(validate_sp);
1294
1295 unsigned long get_wchan(struct task_struct *p)
1296 {
1297         unsigned long ip, sp;
1298         int count = 0;
1299
1300         if (!p || p == current || p->state == TASK_RUNNING)
1301                 return 0;
1302
1303         sp = p->thread.ksp;
1304         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1305                 return 0;
1306
1307         do {
1308                 sp = *(unsigned long *)sp;
1309                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1310                         return 0;
1311                 if (count > 0) {
1312                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1313                         if (!in_sched_functions(ip))
1314                                 return ip;
1315                 }
1316         } while (count++ < 16);
1317         return 0;
1318 }
1319
1320 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1321
1322 void show_stack(struct task_struct *tsk, unsigned long *stack)
1323 {
1324         unsigned long sp, ip, lr, newsp;
1325         int count = 0;
1326         int firstframe = 1;
1327 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1328         int curr_frame = current->curr_ret_stack;
1329         extern void return_to_handler(void);
1330         unsigned long rth = (unsigned long)return_to_handler;
1331         unsigned long mrth = -1;
1332 #ifdef CONFIG_PPC64
1333         extern void mod_return_to_handler(void);
1334         rth = *(unsigned long *)rth;
1335         mrth = (unsigned long)mod_return_to_handler;
1336         mrth = *(unsigned long *)mrth;
1337 #endif
1338 #endif
1339
1340         sp = (unsigned long) stack;
1341         if (tsk == NULL)
1342                 tsk = current;
1343         if (sp == 0) {
1344                 if (tsk == current)
1345                         asm("mr %0,1" : "=r" (sp));
1346                 else
1347                         sp = tsk->thread.ksp;
1348         }
1349
1350         lr = 0;
1351         printk("Call Trace:\n");
1352         do {
1353                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1354                         return;
1355
1356                 stack = (unsigned long *) sp;
1357                 newsp = stack[0];
1358                 ip = stack[STACK_FRAME_LR_SAVE];
1359                 if (!firstframe || ip != lr) {
1360                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1361 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1362                         if ((ip == rth || ip == mrth) && curr_frame >= 0) {
1363                                 printk(" (%pS)",
1364                                        (void *)current->ret_stack[curr_frame].ret);
1365                                 curr_frame--;
1366                         }
1367 #endif
1368                         if (firstframe)
1369                                 printk(" (unreliable)");
1370                         printk("\n");
1371                 }
1372                 firstframe = 0;
1373
1374                 /*
1375                  * See if this is an exception frame.
1376                  * We look for the "regshere" marker in the current frame.
1377                  */
1378                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1379                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1380                         struct pt_regs *regs = (struct pt_regs *)
1381                                 (sp + STACK_FRAME_OVERHEAD);
1382                         lr = regs->link;
1383                         printk("--- Exception: %lx at %pS\n    LR = %pS\n",
1384                                regs->trap, (void *)regs->nip, (void *)lr);
1385                         firstframe = 1;
1386                 }
1387
1388                 sp = newsp;
1389         } while (count++ < kstack_depth_to_print);
1390 }
1391
1392 #ifdef CONFIG_PPC64
1393 /* Called with hard IRQs off */
1394 void notrace __ppc64_runlatch_on(void)
1395 {
1396         struct thread_info *ti = current_thread_info();
1397         unsigned long ctrl;
1398
1399         ctrl = mfspr(SPRN_CTRLF);
1400         ctrl |= CTRL_RUNLATCH;
1401         mtspr(SPRN_CTRLT, ctrl);
1402
1403         ti->local_flags |= _TLF_RUNLATCH;
1404 }
1405
1406 /* Called with hard IRQs off */
1407 void notrace __ppc64_runlatch_off(void)
1408 {
1409         struct thread_info *ti = current_thread_info();
1410         unsigned long ctrl;
1411
1412         ti->local_flags &= ~_TLF_RUNLATCH;
1413
1414         ctrl = mfspr(SPRN_CTRLF);
1415         ctrl &= ~CTRL_RUNLATCH;
1416         mtspr(SPRN_CTRLT, ctrl);
1417 }
1418 #endif /* CONFIG_PPC64 */
1419
1420 unsigned long arch_align_stack(unsigned long sp)
1421 {
1422         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1423                 sp -= get_random_int() & ~PAGE_MASK;
1424         return sp & ~0xf;
1425 }
1426
1427 static inline unsigned long brk_rnd(void)
1428 {
1429         unsigned long rnd = 0;
1430
1431         /* 8MB for 32bit, 1GB for 64bit */
1432         if (is_32bit_task())
1433                 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1434         else
1435                 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1436
1437         return rnd << PAGE_SHIFT;
1438 }
1439
1440 unsigned long arch_randomize_brk(struct mm_struct *mm)
1441 {
1442         unsigned long base = mm->brk;
1443         unsigned long ret;
1444
1445 #ifdef CONFIG_PPC_STD_MMU_64
1446         /*
1447          * If we are using 1TB segments and we are allowed to randomise
1448          * the heap, we can put it above 1TB so it is backed by a 1TB
1449          * segment. Otherwise the heap will be in the bottom 1TB
1450          * which always uses 256MB segments and this may result in a
1451          * performance penalty.
1452          */
1453         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1454                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1455 #endif
1456
1457         ret = PAGE_ALIGN(base + brk_rnd());
1458
1459         if (ret < mm->brk)
1460                 return mm->brk;
1461
1462         return ret;
1463 }
1464
1465 unsigned long randomize_et_dyn(unsigned long base)
1466 {
1467         unsigned long ret = PAGE_ALIGN(base + brk_rnd());
1468
1469         if (ret < base)
1470                 return base;
1471
1472         return ret;
1473 }