2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
33 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
35 #ifdef __LITTLE_ENDIAN__
36 #error Need to fix lppaca and SLB shadow accesses in little endian mode
39 /* Values in HSTATE_NAPPING(r13) */
40 #define NAPPING_CEDE 1
41 #define NAPPING_NOVCPU 2
44 * Call kvmppc_hv_entry in real mode.
45 * Must be called with interrupts hard-disabled.
49 * LR = return address to continue at after eventually re-enabling MMU
51 _GLOBAL(kvmppc_hv_entry_trampoline)
53 std r0, PPC_LR_STKOFF(r1)
56 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
61 mtmsrd r0,1 /* clear RI in MSR */
67 ld r4, HSTATE_KVM_VCPU(r13)
70 /* Back from guest - restore host state and return to caller */
73 /* Restore host DABR and DABRX */
74 ld r5,HSTATE_DABR(r13)
78 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
81 ld r3,PACA_SPRG_VDSO(r13)
82 mtspr SPRN_SPRG_VDSO_WRITE,r3
84 /* Reload the host's PMU registers */
85 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
86 lbz r4, LPPACA_PMCINUSE(r3)
88 beq 23f /* skip if not */
90 ld r3, HSTATE_MMCR(r13)
91 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
94 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
95 lwz r3, HSTATE_PMC(r13)
96 lwz r4, HSTATE_PMC + 4(r13)
97 lwz r5, HSTATE_PMC + 8(r13)
98 lwz r6, HSTATE_PMC + 12(r13)
99 lwz r8, HSTATE_PMC + 16(r13)
100 lwz r9, HSTATE_PMC + 20(r13)
102 lwz r10, HSTATE_PMC + 24(r13)
103 lwz r11, HSTATE_PMC + 28(r13)
104 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
114 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
115 ld r3, HSTATE_MMCR(r13)
116 ld r4, HSTATE_MMCR + 8(r13)
117 ld r5, HSTATE_MMCR + 16(r13)
118 ld r6, HSTATE_MMCR + 24(r13)
119 ld r7, HSTATE_MMCR + 32(r13)
125 ld r8, HSTATE_MMCR + 40(r13)
126 ld r9, HSTATE_MMCR + 48(r13)
129 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
135 * Reload DEC. HDEC interrupts were disabled when
136 * we reloaded the host's LPCR value.
138 ld r3, HSTATE_DECEXP(r13)
144 * For external and machine check interrupts, we need
145 * to call the Linux handler to process the interrupt.
146 * We do that by jumping to absolute address 0x500 for
147 * external interrupts, or the machine_check_fwnmi label
148 * for machine checks (since firmware might have patched
149 * the vector area at 0x200). The [h]rfid at the end of the
150 * handler will return to the book3s_hv_interrupts.S code.
151 * For other interrupts we do the rfid to get back
152 * to the book3s_hv_interrupts.S code here.
154 ld r8, 112+PPC_LR_STKOFF(r1)
156 ld r7, HSTATE_HOST_MSR(r13)
158 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
159 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
162 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
164 /* RFI into the highmem handler, or branch to interrupt handler */
168 mtmsrd r6, 1 /* Clear RI in MSR */
171 beqa 0x500 /* external interrupt (PPC970) */
172 beq cr1, 13f /* machine check */
175 /* On POWER7, we have external interrupts set to use HSRR0/1 */
176 11: mtspr SPRN_HSRR0, r8
180 13: b machine_check_fwnmi
182 kvmppc_primary_no_guest:
183 /* We handle this much like a ceded vcpu */
184 /* set our bit in napping_threads */
185 ld r5, HSTATE_KVM_VCORE(r13)
186 lbz r7, HSTATE_PTID(r13)
189 addi r6, r5, VCORE_NAPPING_THREADS
194 /* order napping_threads update vs testing entry_exit_count */
197 lwz r7, VCORE_ENTRY_EXIT(r5)
199 bge kvm_novcpu_exit /* another thread already exiting */
200 li r3, NAPPING_NOVCPU
201 stb r3, HSTATE_NAPPING(r13)
203 stb r3, HSTATE_HWTHREAD_REQ(r13)
208 ld r1, HSTATE_HOST_R1(r13)
209 ld r5, HSTATE_KVM_VCORE(r13)
211 stb r0, HSTATE_NAPPING(r13)
212 stb r0, HSTATE_HWTHREAD_REQ(r13)
214 /* check the wake reason */
215 bl kvmppc_check_wake_reason
217 /* see if any other thread is already exiting */
218 lwz r0, VCORE_ENTRY_EXIT(r5)
222 /* clear our bit in napping_threads */
223 lbz r7, HSTATE_PTID(r13)
226 addi r6, r5, VCORE_NAPPING_THREADS
232 /* See if the wake reason means we need to exit */
236 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
237 ld r4, HSTATE_KVM_VCPU(r13)
245 * We come in here when wakened from nap mode.
246 * Relocation is off and most register values are lost.
247 * r13 points to the PACA.
249 .globl kvm_start_guest
253 li r0,KVM_HWTHREAD_IN_KVM
254 stb r0,HSTATE_HWTHREAD_STATE(r13)
256 /* NV GPR values from power7_idle() will no longer be valid */
258 stb r0,PACA_NAPSTATELOST(r13)
260 /* were we napping due to cede? */
261 lbz r0,HSTATE_NAPPING(r13)
262 cmpwi r0,NAPPING_CEDE
264 cmpwi r0,NAPPING_NOVCPU
265 beq kvm_novcpu_wakeup
267 ld r1,PACAEMERGSP(r13)
268 subi r1,r1,STACK_FRAME_OVERHEAD
271 * We weren't napping due to cede, so this must be a secondary
272 * thread being woken up to run a guest, or being woken up due
273 * to a stray IPI. (Or due to some machine check or hypervisor
274 * maintenance interrupt while the core is in KVM.)
277 /* Check the wake reason in SRR1 to see why we got here */
278 bl kvmppc_check_wake_reason
282 /* get vcpu pointer, NULL if we have no vcpu to run */
283 ld r4,HSTATE_KVM_VCPU(r13)
285 /* if we have no vcpu to run, go back to sleep */
288 /* Set HSTATE_DSCR(r13) to something sensible */
289 LOAD_REG_ADDR(r6, dscr_default)
291 std r6, HSTATE_DSCR(r13)
295 /* Back from the guest, go back to nap */
296 /* Clear our vcpu pointer so we don't come back in early */
298 std r0, HSTATE_KVM_VCPU(r13)
300 * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing
301 * the nap_count, because once the increment to nap_count is
302 * visible we could be given another vcpu.
306 /* increment the nap count and then go to nap mode */
307 ld r4, HSTATE_KVM_VCORE(r13)
308 addi r4, r4, VCORE_NAP_COUNT
315 li r0, KVM_HWTHREAD_IN_NAP
316 stb r0, HSTATE_HWTHREAD_STATE(r13)
320 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
323 std r0, HSTATE_SCRATCH0(r13)
325 ld r0, HSTATE_SCRATCH0(r13)
331 /******************************************************************************
335 *****************************************************************************/
337 .global kvmppc_hv_entry
342 * R4 = vcpu pointer (or NULL)
346 * all other volatile GPRS = free
349 std r0, PPC_LR_STKOFF(r1)
352 /* Save R1 in the PACA */
353 std r1, HSTATE_HOST_R1(r13)
355 li r6, KVM_GUEST_MODE_HOST_HV
356 stb r6, HSTATE_IN_GUEST(r13)
366 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
368 * POWER7 host -> guest partition switch code.
369 * We don't have to lock against concurrent tlbies,
370 * but we do have to coordinate across hardware threads.
372 /* Increment entry count iff exit count is zero. */
373 ld r5,HSTATE_KVM_VCORE(r13)
374 addi r9,r5,VCORE_ENTRY_EXIT
376 cmpwi r3,0x100 /* any threads starting to exit? */
377 bge secondary_too_late /* if so we're too late to the party */
382 /* Primary thread switches to guest partition. */
383 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
384 lbz r6,HSTATE_PTID(r13)
389 li r0,LPID_RSVD /* switch to reserved LPID */
392 mtspr SPRN_SDR1,r6 /* switch to partition page table */
396 /* See if we need to flush the TLB */
397 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
398 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
399 srdi r6,r6,6 /* doubleword number */
400 sldi r6,r6,3 /* address offset */
402 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
408 23: ldarx r7,0,r6 /* if set, clear the bit */
412 /* Flush the TLB of any entries for this LPID */
413 /* use arch 2.07S as a proxy for POWER8 */
415 li r6,512 /* POWER8 has 512 sets */
417 li r6,128 /* POWER7 has 128 sets */
418 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
420 li r7,0x800 /* IS field = 0b10 */
427 /* Add timebase offset onto timebase */
428 22: ld r8,VCORE_TB_OFFSET(r5)
431 mftb r6 /* current host timebase */
433 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
434 mftb r7 /* check if lower 24 bits overflowed */
439 addis r8,r8,0x100 /* if so, increment upper 40 bits */
442 /* Load guest PCR value to select appropriate compat mode */
443 37: ld r7, VCORE_PCR(r5)
450 /* DPDES is shared between threads */
451 ld r8, VCORE_DPDES(r5)
453 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
456 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
459 /* Secondary threads wait for primary to have done partition switch */
460 20: lbz r0,VCORE_IN_GUEST(r5)
464 /* Set LPCR and RMOR. */
465 10: ld r8,VCORE_LPCR(r5)
471 /* Check if HDEC expires soon */
473 cmpwi r3,512 /* 1 microsecond */
474 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
479 * PPC970 host -> guest partition switch code.
480 * We have to lock against concurrent tlbies,
481 * using native_tlbie_lock to lock against host tlbies
482 * and kvm->arch.tlbie_lock to lock against guest tlbies.
483 * We also have to invalidate the TLB since its
484 * entries aren't tagged with the LPID.
486 30: ld r5,HSTATE_KVM_VCORE(r13)
487 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
489 /* first take native_tlbie_lock */
492 .tc native_tlbie_lock[TC],native_tlbie_lock
494 ld r3,toc_tlbie_lock@toc(2)
495 #ifdef __BIG_ENDIAN__
496 lwz r8,PACA_LOCK_TOKEN(r13)
498 lwz r8,PACAPACAINDEX(r13)
507 ld r5,HSTATE_KVM_VCORE(r13)
508 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
510 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
514 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
517 stw r0,0(r3) /* drop native_tlbie_lock */
519 /* invalidate the whole TLB */
528 /* Take the guest's tlbie_lock */
529 addi r3,r9,KVM_TLBIE_LOCK
537 mtspr SPRN_SDR1,r6 /* switch to partition page table */
539 /* Set up HID4 with the guest's LPID etc. */
544 /* drop the guest's tlbie_lock */
548 /* Check if HDEC expires soon */
551 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
554 /* Enable HDEC interrupts */
557 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
567 /* Do we have a guest vcpu to run? */
569 beq kvmppc_primary_no_guest
572 /* Load up guest SLB entries */
573 lwz r5,VCPU_SLB_MAX(r4)
578 1: ld r8,VCPU_SLB_E(r6)
581 addi r6,r6,VCPU_SLB_SIZE
584 /* Increment yield count if they have a VPA */
588 lwz r5, LPPACA_YIELDCOUNT(r3)
590 stw r5, LPPACA_YIELDCOUNT(r3)
592 stb r6, VCPU_VPA_DIRTY(r4)
596 /* Save purr/spurr */
599 std r5,HSTATE_PURR(r13)
600 std r6,HSTATE_SPURR(r13)
605 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
608 /* Set partition DABR */
609 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
610 lwz r5,VCPU_DABRX(r4)
614 BEGIN_FTR_SECTION_NESTED(89)
616 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
617 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
619 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
622 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
624 /* Turn on TM/FP/VSX/VMX so we can restore them. */
630 oris r5, r5, (MSR_VEC | MSR_VSX)@h
634 * The user may change these outside of a transaction, so they must
635 * always be context switched.
637 ld r5, VCPU_TFHAR(r4)
638 ld r6, VCPU_TFIAR(r4)
639 ld r7, VCPU_TEXASR(r4)
642 mtspr SPRN_TEXASR, r7
645 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
646 beq skip_tm /* TM not active in guest */
648 /* Make sure the failure summary is set, otherwise we'll program check
649 * when we trechkpt. It's possible that this might have been not set
650 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
653 oris r7, r7, (TEXASR_FS)@h
654 mtspr SPRN_TEXASR, r7
657 * We need to load up the checkpointed state for the guest.
658 * We need to do this early as it will blow away any GPRs, VSRs and
663 addi r3, r31, VCPU_FPRS_TM
665 addi r3, r31, VCPU_VRS_TM
668 lwz r7, VCPU_VRSAVE_TM(r4)
669 mtspr SPRN_VRSAVE, r7
671 ld r5, VCPU_LR_TM(r4)
672 lwz r6, VCPU_CR_TM(r4)
673 ld r7, VCPU_CTR_TM(r4)
674 ld r8, VCPU_AMR_TM(r4)
675 ld r9, VCPU_TAR_TM(r4)
683 * Load up PPR and DSCR values but don't put them in the actual SPRs
684 * till the last moment to avoid running with userspace PPR and DSCR for
687 ld r29, VCPU_DSCR_TM(r4)
688 ld r30, VCPU_PPR_TM(r4)
690 std r2, PACATMSCRATCH(r13) /* Save TOC */
692 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
696 /* Load GPRs r0-r28 */
699 ld reg, VCPU_GPRS_TM(reg)(r31)
706 /* Load final GPRs */
707 ld 29, VCPU_GPRS_TM(29)(r31)
708 ld 30, VCPU_GPRS_TM(30)(r31)
709 ld 31, VCPU_GPRS_TM(31)(r31)
711 /* TM checkpointed state is now setup. All GPRs are now volatile. */
714 /* Now let's get back the state we need. */
717 ld r29, HSTATE_DSCR(r13)
719 ld r4, HSTATE_KVM_VCPU(r13)
720 ld r1, HSTATE_HOST_R1(r13)
721 ld r2, PACATMSCRATCH(r13)
723 /* Set the MSR RI since we have our registers back. */
729 /* Load guest PMU registers */
730 /* R4 is live here (vcpu pointer) */
732 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
733 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
737 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
740 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
741 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
742 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
743 lwz r6, VCPU_PMC + 8(r4)
744 lwz r7, VCPU_PMC + 12(r4)
745 lwz r8, VCPU_PMC + 16(r4)
746 lwz r9, VCPU_PMC + 20(r4)
748 lwz r10, VCPU_PMC + 24(r4)
749 lwz r11, VCPU_PMC + 28(r4)
750 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
760 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
762 ld r5, VCPU_MMCR + 8(r4)
763 ld r6, VCPU_MMCR + 16(r4)
771 ld r5, VCPU_MMCR + 24(r4)
773 lwz r7, VCPU_PMC + 24(r4)
774 lwz r8, VCPU_PMC + 28(r4)
775 ld r9, VCPU_MMCR + 32(r4)
781 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
785 /* Load up FP, VMX and VSX registers */
788 ld r14, VCPU_GPR(R14)(r4)
789 ld r15, VCPU_GPR(R15)(r4)
790 ld r16, VCPU_GPR(R16)(r4)
791 ld r17, VCPU_GPR(R17)(r4)
792 ld r18, VCPU_GPR(R18)(r4)
793 ld r19, VCPU_GPR(R19)(r4)
794 ld r20, VCPU_GPR(R20)(r4)
795 ld r21, VCPU_GPR(R21)(r4)
796 ld r22, VCPU_GPR(R22)(r4)
797 ld r23, VCPU_GPR(R23)(r4)
798 ld r24, VCPU_GPR(R24)(r4)
799 ld r25, VCPU_GPR(R25)(r4)
800 ld r26, VCPU_GPR(R26)(r4)
801 ld r27, VCPU_GPR(R27)(r4)
802 ld r28, VCPU_GPR(R28)(r4)
803 ld r29, VCPU_GPR(R29)(r4)
804 ld r30, VCPU_GPR(R30)(r4)
805 ld r31, VCPU_GPR(R31)(r4)
808 /* Switch DSCR to guest value */
811 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
814 /* Skip next section on POWER7 or PPC970 */
816 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
817 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
820 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
823 /* Load up POWER8-specific registers */
825 lwz r6, VCPU_PSPB(r4)
831 ld r6, VCPU_DAWRX(r4)
832 ld r7, VCPU_CIABR(r4)
842 ld r8, VCPU_EBBHR(r4)
844 ld r5, VCPU_EBBRR(r4)
845 ld r6, VCPU_BESCR(r4)
846 ld r7, VCPU_CSIGR(r4)
852 ld r5, VCPU_TCSCR(r4)
854 lwz r7, VCPU_GUEST_PID(r4)
863 * Set the decrementer to the guest decrementer.
865 ld r8,VCPU_DEC_EXPIRES(r4)
866 /* r8 is a host timebase value here, convert to guest TB */
867 ld r5,HSTATE_KVM_VCORE(r13)
868 ld r6,VCORE_TB_OFFSET(r5)
875 ld r5, VCPU_SPRG0(r4)
876 ld r6, VCPU_SPRG1(r4)
877 ld r7, VCPU_SPRG2(r4)
878 ld r8, VCPU_SPRG3(r4)
884 /* Load up DAR and DSISR */
886 lwz r6, VCPU_DSISR(r4)
891 /* Restore AMR and UAMOR, set AMOR to all 1s */
898 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
900 /* Restore state of CTRL run bit; assume 1 on entry */
914 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
922 deliver_guest_interrupt:
923 /* r11 = vcpu->arch.msr & ~MSR_HV */
924 rldicl r11, r11, 63 - MSR_HV_LG, 1
925 rotldi r11, r11, 1 + MSR_HV_LG
928 /* Check if we can deliver an external or decrementer interrupt now */
929 ld r0, VCPU_PENDING_EXC(r4)
930 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
932 andi. r8, r11, MSR_EE
935 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
936 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
939 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
941 li r0, BOOK3S_INTERRUPT_EXTERNAL
945 li r0, BOOK3S_INTERRUPT_DECREMENTER
948 12: mtspr SPRN_SRR0, r10
952 bl kvmppc_msr_interrupt
958 * R10: value for HSRR0
959 * R11: value for HSRR1
964 stb r0,VCPU_CEDED(r4) /* cancel cede */
968 /* Activate guest mode, so faults get handled by KVM */
969 li r9, KVM_GUEST_MODE_GUEST_HV
970 stb r9, HSTATE_IN_GUEST(r13)
977 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
980 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
987 ld r1, VCPU_GPR(R1)(r4)
988 ld r2, VCPU_GPR(R2)(r4)
989 ld r3, VCPU_GPR(R3)(r4)
990 ld r5, VCPU_GPR(R5)(r4)
991 ld r6, VCPU_GPR(R6)(r4)
992 ld r7, VCPU_GPR(R7)(r4)
993 ld r8, VCPU_GPR(R8)(r4)
994 ld r9, VCPU_GPR(R9)(r4)
995 ld r10, VCPU_GPR(R10)(r4)
996 ld r11, VCPU_GPR(R11)(r4)
997 ld r12, VCPU_GPR(R12)(r4)
998 ld r13, VCPU_GPR(R13)(r4)
1002 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1003 ld r0, VCPU_GPR(R0)(r4)
1004 ld r4, VCPU_GPR(R4)(r4)
1009 /******************************************************************************
1013 *****************************************************************************/
1016 * We come here from the first-level interrupt handlers.
1018 .globl kvmppc_interrupt_hv
1019 kvmppc_interrupt_hv:
1021 * Register contents:
1022 * R12 = interrupt vector
1024 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1025 * guest R13 saved in SPRN_SCRATCH0
1027 std r9, HSTATE_SCRATCH2(r13)
1029 lbz r9, HSTATE_IN_GUEST(r13)
1030 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1031 beq kvmppc_bad_host_intr
1032 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1033 cmpwi r9, KVM_GUEST_MODE_GUEST
1034 ld r9, HSTATE_SCRATCH2(r13)
1035 beq kvmppc_interrupt_pr
1037 /* We're now back in the host but in guest MMU context */
1038 li r9, KVM_GUEST_MODE_HOST_HV
1039 stb r9, HSTATE_IN_GUEST(r13)
1041 ld r9, HSTATE_KVM_VCPU(r13)
1043 /* Save registers */
1045 std r0, VCPU_GPR(R0)(r9)
1046 std r1, VCPU_GPR(R1)(r9)
1047 std r2, VCPU_GPR(R2)(r9)
1048 std r3, VCPU_GPR(R3)(r9)
1049 std r4, VCPU_GPR(R4)(r9)
1050 std r5, VCPU_GPR(R5)(r9)
1051 std r6, VCPU_GPR(R6)(r9)
1052 std r7, VCPU_GPR(R7)(r9)
1053 std r8, VCPU_GPR(R8)(r9)
1054 ld r0, HSTATE_SCRATCH2(r13)
1055 std r0, VCPU_GPR(R9)(r9)
1056 std r10, VCPU_GPR(R10)(r9)
1057 std r11, VCPU_GPR(R11)(r9)
1058 ld r3, HSTATE_SCRATCH0(r13)
1059 lwz r4, HSTATE_SCRATCH1(r13)
1060 std r3, VCPU_GPR(R12)(r9)
1063 ld r3, HSTATE_CFAR(r13)
1064 std r3, VCPU_CFAR(r9)
1065 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1067 ld r4, HSTATE_PPR(r13)
1068 std r4, VCPU_PPR(r9)
1069 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1071 /* Restore R1/R2 so we can handle faults */
1072 ld r1, HSTATE_HOST_R1(r13)
1075 mfspr r10, SPRN_SRR0
1076 mfspr r11, SPRN_SRR1
1077 std r10, VCPU_SRR0(r9)
1078 std r11, VCPU_SRR1(r9)
1079 andi. r0, r12, 2 /* need to read HSRR0/1? */
1081 mfspr r10, SPRN_HSRR0
1082 mfspr r11, SPRN_HSRR1
1084 1: std r10, VCPU_PC(r9)
1085 std r11, VCPU_MSR(r9)
1089 std r3, VCPU_GPR(R13)(r9)
1092 stw r12,VCPU_TRAP(r9)
1094 /* Save HEIR (HV emulation assist reg) in last_inst
1095 if this is an HEI (HV emulation interrupt, e40) */
1096 li r3,KVM_INST_FETCH_FAILED
1098 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1101 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1102 11: stw r3,VCPU_LAST_INST(r9)
1104 /* these are volatile across C function calls */
1107 std r3, VCPU_CTR(r9)
1108 stw r4, VCPU_XER(r9)
1111 /* If this is a page table miss then see if it's theirs or ours */
1112 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1114 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1116 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1118 /* See if this is a leftover HDEC interrupt */
1119 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1125 /* See if this is an hcall we can handle in real mode */
1126 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1127 beq hcall_try_real_mode
1129 /* Only handle external interrupts here on arch 206 and later */
1131 b ext_interrupt_to_host
1132 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1134 /* External interrupt ? */
1135 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1136 bne+ ext_interrupt_to_host
1138 /* External interrupt, first check for host_ipi. If this is
1139 * set, we know the host wants us out so let's do it now
1143 bgt ext_interrupt_to_host
1145 /* Check if any CPU is heading out to the host, if so head out too */
1146 ld r5, HSTATE_KVM_VCORE(r13)
1147 lwz r0, VCORE_ENTRY_EXIT(r5)
1149 bge ext_interrupt_to_host
1151 /* Return to guest after delivering any pending interrupt */
1153 b deliver_guest_interrupt
1155 ext_interrupt_to_host:
1157 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1158 /* Save more register state */
1161 std r6, VCPU_DAR(r9)
1162 stw r7, VCPU_DSISR(r9)
1164 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1165 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1167 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1168 std r6, VCPU_FAULT_DAR(r9)
1169 stw r7, VCPU_FAULT_DSISR(r9)
1171 /* See if it is a machine check */
1172 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1173 beq machine_check_realmode
1176 /* Save guest CTRL register, set runlatch to 1 */
1177 6: mfspr r6,SPRN_CTRLF
1178 stw r6,VCPU_CTRL(r9)
1184 /* Read the guest SLB and save it away */
1185 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1191 andis. r0,r8,SLB_ESID_V@h
1193 add r8,r8,r6 /* put index in */
1195 std r8,VCPU_SLB_E(r7)
1196 std r3,VCPU_SLB_V(r7)
1197 addi r7,r7,VCPU_SLB_SIZE
1201 stw r5,VCPU_SLB_MAX(r9)
1204 * Save the guest PURR/SPURR
1210 ld r8,VCPU_SPURR(r9)
1211 std r5,VCPU_PURR(r9)
1212 std r6,VCPU_SPURR(r9)
1217 * Restore host PURR/SPURR and add guest times
1218 * so that the time in the guest gets accounted.
1220 ld r3,HSTATE_PURR(r13)
1221 ld r4,HSTATE_SPURR(r13)
1226 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
1233 /* r5 is a guest timebase value here, convert to host TB */
1234 ld r3,HSTATE_KVM_VCORE(r13)
1235 ld r4,VCORE_TB_OFFSET(r3)
1237 std r5,VCPU_DEC_EXPIRES(r9)
1241 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1242 /* Save POWER8-specific registers */
1246 std r5, VCPU_IAMR(r9)
1247 stw r6, VCPU_PSPB(r9)
1248 std r7, VCPU_FSCR(r9)
1253 std r6, VCPU_VTB(r9)
1254 std r7, VCPU_TAR(r9)
1255 mfspr r8, SPRN_EBBHR
1256 std r8, VCPU_EBBHR(r9)
1257 mfspr r5, SPRN_EBBRR
1258 mfspr r6, SPRN_BESCR
1259 mfspr r7, SPRN_CSIGR
1261 std r5, VCPU_EBBRR(r9)
1262 std r6, VCPU_BESCR(r9)
1263 std r7, VCPU_CSIGR(r9)
1264 std r8, VCPU_TACR(r9)
1265 mfspr r5, SPRN_TCSCR
1269 std r5, VCPU_TCSCR(r9)
1270 std r6, VCPU_ACOP(r9)
1271 stw r7, VCPU_GUEST_PID(r9)
1272 std r8, VCPU_WORT(r9)
1275 /* Save and reset AMR and UAMOR before turning on the MMU */
1280 std r6,VCPU_UAMOR(r9)
1283 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1285 /* Switch DSCR back to host value */
1288 ld r7, HSTATE_DSCR(r13)
1289 std r8, VCPU_DSCR(r9)
1291 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1293 /* Save non-volatile GPRs */
1294 std r14, VCPU_GPR(R14)(r9)
1295 std r15, VCPU_GPR(R15)(r9)
1296 std r16, VCPU_GPR(R16)(r9)
1297 std r17, VCPU_GPR(R17)(r9)
1298 std r18, VCPU_GPR(R18)(r9)
1299 std r19, VCPU_GPR(R19)(r9)
1300 std r20, VCPU_GPR(R20)(r9)
1301 std r21, VCPU_GPR(R21)(r9)
1302 std r22, VCPU_GPR(R22)(r9)
1303 std r23, VCPU_GPR(R23)(r9)
1304 std r24, VCPU_GPR(R24)(r9)
1305 std r25, VCPU_GPR(R25)(r9)
1306 std r26, VCPU_GPR(R26)(r9)
1307 std r27, VCPU_GPR(R27)(r9)
1308 std r28, VCPU_GPR(R28)(r9)
1309 std r29, VCPU_GPR(R29)(r9)
1310 std r30, VCPU_GPR(R30)(r9)
1311 std r31, VCPU_GPR(R31)(r9)
1314 mfspr r3, SPRN_SPRG0
1315 mfspr r4, SPRN_SPRG1
1316 mfspr r5, SPRN_SPRG2
1317 mfspr r6, SPRN_SPRG3
1318 std r3, VCPU_SPRG0(r9)
1319 std r4, VCPU_SPRG1(r9)
1320 std r5, VCPU_SPRG2(r9)
1321 std r6, VCPU_SPRG3(r9)
1327 /* Increment yield count if they have a VPA */
1328 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1331 lwz r3, LPPACA_YIELDCOUNT(r8)
1333 stw r3, LPPACA_YIELDCOUNT(r8)
1335 stb r3, VCPU_VPA_DIRTY(r9)
1337 /* Save PMU registers if requested */
1338 /* r8 and cr0.eq are live here */
1341 * POWER8 seems to have a hardware bug where setting
1342 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1343 * when some counters are already negative doesn't seem
1344 * to cause a performance monitor alert (and hence interrupt).
1345 * The effect of this is that when saving the PMU state,
1346 * if there is no PMU alert pending when we read MMCR0
1347 * before freezing the counters, but one becomes pending
1348 * before we read the counters, we lose it.
1349 * To work around this, we need a way to freeze the counters
1350 * before reading MMCR0. Normally, freezing the counters
1351 * is done by writing MMCR0 (to set MMCR0[FC]) which
1352 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1353 * we can also freeze the counters using MMCR2, by writing
1354 * 1s to all the counter freeze condition bits (there are
1355 * 9 bits each for 6 counters).
1357 li r3, -1 /* set all freeze bits */
1359 mfspr r10, SPRN_MMCR2
1360 mtspr SPRN_MMCR2, r3
1362 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1364 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1365 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1366 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1367 mfspr r6, SPRN_MMCRA
1369 /* On P7, clear MMCRA in order to disable SDAR updates */
1371 mtspr SPRN_MMCRA, r7
1372 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1374 beq 21f /* if no VPA, save PMU stuff anyway */
1375 lbz r7, LPPACA_PMCINUSE(r8)
1376 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1378 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1380 21: mfspr r5, SPRN_MMCR1
1383 std r4, VCPU_MMCR(r9)
1384 std r5, VCPU_MMCR + 8(r9)
1385 std r6, VCPU_MMCR + 16(r9)
1387 std r10, VCPU_MMCR + 24(r9)
1388 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1389 std r7, VCPU_SIAR(r9)
1390 std r8, VCPU_SDAR(r9)
1398 mfspr r10, SPRN_PMC7
1399 mfspr r11, SPRN_PMC8
1400 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1401 stw r3, VCPU_PMC(r9)
1402 stw r4, VCPU_PMC + 4(r9)
1403 stw r5, VCPU_PMC + 8(r9)
1404 stw r6, VCPU_PMC + 12(r9)
1405 stw r7, VCPU_PMC + 16(r9)
1406 stw r8, VCPU_PMC + 20(r9)
1408 stw r10, VCPU_PMC + 24(r9)
1409 stw r11, VCPU_PMC + 28(r9)
1410 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1413 mfspr r6, SPRN_SPMC1
1414 mfspr r7, SPRN_SPMC2
1415 mfspr r8, SPRN_MMCRS
1416 std r5, VCPU_SIER(r9)
1417 stw r6, VCPU_PMC + 24(r9)
1418 stw r7, VCPU_PMC + 28(r9)
1419 std r8, VCPU_MMCR + 32(r9)
1421 mtspr SPRN_MMCRS, r4
1422 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1430 hdec_soon: /* r12 = trap, r13 = paca */
1433 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1435 * POWER7 guest -> host partition switch code.
1436 * We don't have to lock against tlbies but we do
1437 * have to coordinate the hardware threads.
1439 /* Increment the threads-exiting-guest count in the 0xff00
1440 bits of vcore->entry_exit_count */
1441 ld r5,HSTATE_KVM_VCORE(r13)
1442 addi r6,r5,VCORE_ENTRY_EXIT
1447 isync /* order stwcx. vs. reading napping_threads */
1450 * At this point we have an interrupt that we have to pass
1451 * up to the kernel or qemu; we can't handle it in real mode.
1452 * Thus we have to do a partition switch, so we have to
1453 * collect the other threads, if we are the first thread
1454 * to take an interrupt. To do this, we set the HDEC to 0,
1455 * which causes an HDEC interrupt in all threads within 2ns
1456 * because the HDEC register is shared between all 4 threads.
1457 * However, we don't need to bother if this is an HDEC
1458 * interrupt, since the other threads will already be on their
1459 * way here in that case.
1461 cmpwi r3,0x100 /* Are we the first here? */
1463 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1469 * Send an IPI to any napping threads, since an HDEC interrupt
1470 * doesn't wake CPUs up from nap.
1472 lwz r3,VCORE_NAPPING_THREADS(r5)
1473 lbz r4,HSTATE_PTID(r13)
1476 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1478 /* Order entry/exit update vs. IPIs */
1480 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1484 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1487 stbcix r0,r7,r8 /* trigger the IPI */
1489 addi r6,r6,PACA_SIZE
1493 /* Secondary threads wait for primary to do partition switch */
1494 43: ld r5,HSTATE_KVM_VCORE(r13)
1495 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1496 lbz r3,HSTATE_PTID(r13)
1500 13: lbz r3,VCORE_IN_GUEST(r5)
1506 /* Primary thread waits for all the secondaries to exit guest */
1507 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1514 /* Primary thread switches back to host partition */
1515 ld r6,KVM_HOST_SDR1(r4)
1516 lwz r7,KVM_HOST_LPID(r4)
1517 li r8,LPID_RSVD /* switch to reserved LPID */
1520 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1525 /* DPDES is shared between threads */
1526 mfspr r7, SPRN_DPDES
1527 std r7, VCORE_DPDES(r5)
1528 /* clear DPDES so we don't get guest doorbells in the host */
1530 mtspr SPRN_DPDES, r8
1531 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1533 /* Subtract timebase offset from timebase */
1534 ld r8,VCORE_TB_OFFSET(r5)
1537 mftb r6 /* current guest timebase */
1539 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1540 mftb r7 /* check if lower 24 bits overflowed */
1545 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1549 17: ld r0, VCORE_PCR(r5)
1555 /* Signal secondary CPUs to continue */
1556 stb r0,VCORE_IN_GUEST(r5)
1557 lis r8,0x7fff /* MAX_INT@h */
1560 16: ld r8,KVM_HOST_LPCR(r4)
1566 * PPC970 guest -> host partition switch code.
1567 * We have to lock against concurrent tlbies, and
1568 * we have to flush the whole TLB.
1570 32: ld r5,HSTATE_KVM_VCORE(r13)
1571 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1573 /* Take the guest's tlbie_lock */
1574 #ifdef __BIG_ENDIAN__
1575 lwz r8,PACA_LOCK_TOKEN(r13)
1577 lwz r8,PACAPACAINDEX(r13)
1579 addi r3,r4,KVM_TLBIE_LOCK
1587 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1589 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1593 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1596 stw r0,0(r3) /* drop guest tlbie_lock */
1598 /* invalidate the whole TLB */
1607 /* take native_tlbie_lock */
1608 ld r3,toc_tlbie_lock@toc(2)
1616 ld r6,KVM_HOST_SDR1(r4)
1617 mtspr SPRN_SDR1,r6 /* switch to host page table */
1619 /* Set up host HID4 value */
1624 stw r0,0(r3) /* drop native_tlbie_lock */
1626 lis r8,0x7fff /* MAX_INT@h */
1629 /* Disable HDEC interrupts */
1632 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1642 /* load host SLB entries */
1643 33: ld r8,PACA_SLBSHADOWPTR(r13)
1645 .rept SLB_NUM_BOLTED
1646 ld r5,SLBSHADOW_SAVEAREA(r8)
1647 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1648 andis. r7,r5,SLB_ESID_V@h
1654 /* Unset guest mode */
1655 li r0, KVM_GUEST_MODE_NONE
1656 stb r0, HSTATE_IN_GUEST(r13)
1658 ld r0, 112+PPC_LR_STKOFF(r1)
1664 * Check whether an HDSI is an HPTE not found fault or something else.
1665 * If it is an HPTE not found fault that is due to the guest accessing
1666 * a page that they have mapped but which we have paged out, then
1667 * we continue on with the guest exit path. In all other cases,
1668 * reflect the HDSI to the guest as a DSI.
1672 mfspr r6, SPRN_HDSISR
1673 /* HPTE not found fault or protection fault? */
1674 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1675 beq 1f /* if not, send it to the guest */
1676 andi. r0, r11, MSR_DR /* data relocation enabled? */
1679 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1680 bne 1f /* if no SLB entry found */
1681 4: std r4, VCPU_FAULT_DAR(r9)
1682 stw r6, VCPU_FAULT_DSISR(r9)
1684 /* Search the hash table. */
1685 mr r3, r9 /* vcpu pointer */
1686 li r7, 1 /* data fault */
1687 bl .kvmppc_hpte_hv_fault
1688 ld r9, HSTATE_KVM_VCPU(r13)
1690 ld r11, VCPU_MSR(r9)
1691 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1692 cmpdi r3, 0 /* retry the instruction */
1694 cmpdi r3, -1 /* handle in kernel mode */
1696 cmpdi r3, -2 /* MMIO emulation; need instr word */
1699 /* Synthesize a DSI for the guest */
1700 ld r4, VCPU_FAULT_DAR(r9)
1702 1: mtspr SPRN_DAR, r4
1703 mtspr SPRN_DSISR, r6
1704 mtspr SPRN_SRR0, r10
1705 mtspr SPRN_SRR1, r11
1706 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1707 bl kvmppc_msr_interrupt
1708 fast_interrupt_c_return:
1709 6: ld r7, VCPU_CTR(r9)
1710 lwz r8, VCPU_XER(r9)
1716 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1717 ld r5, KVM_VRMA_SLB_V(r5)
1720 /* If this is for emulated MMIO, load the instruction word */
1721 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1723 /* Set guest mode to 'jump over instruction' so if lwz faults
1724 * we'll just continue at the next IP. */
1725 li r0, KVM_GUEST_MODE_SKIP
1726 stb r0, HSTATE_IN_GUEST(r13)
1728 /* Do the access with MSR:DR enabled */
1730 ori r4, r3, MSR_DR /* Enable paging for data */
1735 /* Store the result */
1736 stw r8, VCPU_LAST_INST(r9)
1738 /* Unset guest mode. */
1739 li r0, KVM_GUEST_MODE_HOST_HV
1740 stb r0, HSTATE_IN_GUEST(r13)
1744 * Similarly for an HISI, reflect it to the guest as an ISI unless
1745 * it is an HPTE not found fault for a page that we have paged out.
1748 andis. r0, r11, SRR1_ISI_NOPT@h
1750 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1753 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1754 bne 1f /* if no SLB entry found */
1756 /* Search the hash table. */
1757 mr r3, r9 /* vcpu pointer */
1760 li r7, 0 /* instruction fault */
1761 bl .kvmppc_hpte_hv_fault
1762 ld r9, HSTATE_KVM_VCPU(r13)
1764 ld r11, VCPU_MSR(r9)
1765 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1766 cmpdi r3, 0 /* retry the instruction */
1767 beq fast_interrupt_c_return
1768 cmpdi r3, -1 /* handle in kernel mode */
1771 /* Synthesize an ISI for the guest */
1773 1: mtspr SPRN_SRR0, r10
1774 mtspr SPRN_SRR1, r11
1775 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1776 bl kvmppc_msr_interrupt
1777 b fast_interrupt_c_return
1779 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1780 ld r5, KVM_VRMA_SLB_V(r6)
1784 * Try to handle an hcall in real mode.
1785 * Returns to the guest if we handle it, or continues on up to
1786 * the kernel if we can't (i.e. if we don't have a handler for
1787 * it, or if the handler returns H_TOO_HARD).
1789 .globl hcall_try_real_mode
1790 hcall_try_real_mode:
1791 ld r3,VCPU_GPR(R3)(r9)
1793 /* sc 1 from userspace - reflect to guest syscall */
1794 bne sc_1_fast_return
1796 cmpldi r3,hcall_real_table_end - hcall_real_table
1798 LOAD_REG_ADDR(r4, hcall_real_table)
1804 mr r3,r9 /* get vcpu pointer */
1805 ld r4,VCPU_GPR(R4)(r9)
1808 beq hcall_real_fallback
1809 ld r4,HSTATE_KVM_VCPU(r13)
1810 std r3,VCPU_GPR(R3)(r4)
1818 li r10, BOOK3S_INTERRUPT_SYSCALL
1819 bl kvmppc_msr_interrupt
1823 /* We've attempted a real mode hcall, but it's punted it back
1824 * to userspace. We need to restore some clobbered volatiles
1825 * before resuming the pass-it-to-qemu path */
1826 hcall_real_fallback:
1827 li r12,BOOK3S_INTERRUPT_SYSCALL
1828 ld r9, HSTATE_KVM_VCPU(r13)
1832 .globl hcall_real_table
1834 .long 0 /* 0 - unused */
1835 .long .kvmppc_h_remove - hcall_real_table
1836 .long .kvmppc_h_enter - hcall_real_table
1837 .long .kvmppc_h_read - hcall_real_table
1838 .long 0 /* 0x10 - H_CLEAR_MOD */
1839 .long 0 /* 0x14 - H_CLEAR_REF */
1840 .long .kvmppc_h_protect - hcall_real_table
1841 .long .kvmppc_h_get_tce - hcall_real_table
1842 .long .kvmppc_h_put_tce - hcall_real_table
1843 .long 0 /* 0x24 - H_SET_SPRG0 */
1844 .long .kvmppc_h_set_dabr - hcall_real_table
1859 #ifdef CONFIG_KVM_XICS
1860 .long .kvmppc_rm_h_eoi - hcall_real_table
1861 .long .kvmppc_rm_h_cppr - hcall_real_table
1862 .long .kvmppc_rm_h_ipi - hcall_real_table
1863 .long 0 /* 0x70 - H_IPOLL */
1864 .long .kvmppc_rm_h_xirr - hcall_real_table
1866 .long 0 /* 0x64 - H_EOI */
1867 .long 0 /* 0x68 - H_CPPR */
1868 .long 0 /* 0x6c - H_IPI */
1869 .long 0 /* 0x70 - H_IPOLL */
1870 .long 0 /* 0x74 - H_XIRR */
1898 .long .kvmppc_h_cede - hcall_real_table
1915 .long .kvmppc_h_bulk_remove - hcall_real_table
1919 .long .kvmppc_h_set_xdabr - hcall_real_table
1920 hcall_real_table_end:
1926 _GLOBAL(kvmppc_h_set_xdabr)
1927 andi. r0, r5, DABRX_USER | DABRX_KERNEL
1929 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
1932 6: li r3, H_PARAMETER
1935 _GLOBAL(kvmppc_h_set_dabr)
1936 li r5, DABRX_USER | DABRX_KERNEL
1940 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1941 std r4,VCPU_DABR(r3)
1942 stw r5, VCPU_DABRX(r3)
1943 mtspr SPRN_DABRX, r5
1944 /* Work around P7 bug where DABR can get corrupted on mtspr */
1945 1: mtspr SPRN_DABR,r4
1953 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
1954 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
1955 rlwimi r5, r4, 1, DAWRX_WT
1957 std r4, VCPU_DAWR(r3)
1958 std r5, VCPU_DAWRX(r3)
1960 mtspr SPRN_DAWRX, r5
1964 _GLOBAL(kvmppc_h_cede)
1966 std r11,VCPU_MSR(r3)
1968 stb r0,VCPU_CEDED(r3)
1969 sync /* order setting ceded vs. testing prodded */
1970 lbz r5,VCPU_PRODDED(r3)
1972 bne kvm_cede_prodded
1973 li r0,0 /* set trap to 0 to say hcall is handled */
1974 stw r0,VCPU_TRAP(r3)
1976 std r0,VCPU_GPR(R3)(r3)
1978 b kvm_cede_exit /* just send it up to host on 970 */
1979 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1982 * Set our bit in the bitmask of napping threads unless all the
1983 * other threads are already napping, in which case we send this
1986 ld r5,HSTATE_KVM_VCORE(r13)
1987 lbz r6,HSTATE_PTID(r13)
1988 lwz r8,VCORE_ENTRY_EXIT(r5)
1992 addi r6,r5,VCORE_NAPPING_THREADS
2000 /* order napping_threads update vs testing entry_exit_count */
2003 stb r0,HSTATE_NAPPING(r13)
2004 lwz r7,VCORE_ENTRY_EXIT(r5)
2006 bge 33f /* another thread already exiting */
2009 * Although not specifically required by the architecture, POWER7
2010 * preserves the following registers in nap mode, even if an SMT mode
2011 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2012 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2014 /* Save non-volatile GPRs */
2015 std r14, VCPU_GPR(R14)(r3)
2016 std r15, VCPU_GPR(R15)(r3)
2017 std r16, VCPU_GPR(R16)(r3)
2018 std r17, VCPU_GPR(R17)(r3)
2019 std r18, VCPU_GPR(R18)(r3)
2020 std r19, VCPU_GPR(R19)(r3)
2021 std r20, VCPU_GPR(R20)(r3)
2022 std r21, VCPU_GPR(R21)(r3)
2023 std r22, VCPU_GPR(R22)(r3)
2024 std r23, VCPU_GPR(R23)(r3)
2025 std r24, VCPU_GPR(R24)(r3)
2026 std r25, VCPU_GPR(R25)(r3)
2027 std r26, VCPU_GPR(R26)(r3)
2028 std r27, VCPU_GPR(R27)(r3)
2029 std r28, VCPU_GPR(R28)(r3)
2030 std r29, VCPU_GPR(R29)(r3)
2031 std r30, VCPU_GPR(R30)(r3)
2032 std r31, VCPU_GPR(R31)(r3)
2038 * Take a nap until a decrementer or external or doobell interrupt
2039 * occurs, with PECE1, PECE0 and PECEDP set in LPCR
2042 stb r0,HSTATE_HWTHREAD_REQ(r13)
2044 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2046 oris r5,r5,LPCR_PECEDP@h
2047 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2051 std r0, HSTATE_SCRATCH0(r13)
2053 ld r0, HSTATE_SCRATCH0(r13)
2065 /* get vcpu pointer */
2066 ld r4, HSTATE_KVM_VCPU(r13)
2068 /* Woken by external or decrementer interrupt */
2069 ld r1, HSTATE_HOST_R1(r13)
2071 /* load up FP state */
2075 ld r14, VCPU_GPR(R14)(r4)
2076 ld r15, VCPU_GPR(R15)(r4)
2077 ld r16, VCPU_GPR(R16)(r4)
2078 ld r17, VCPU_GPR(R17)(r4)
2079 ld r18, VCPU_GPR(R18)(r4)
2080 ld r19, VCPU_GPR(R19)(r4)
2081 ld r20, VCPU_GPR(R20)(r4)
2082 ld r21, VCPU_GPR(R21)(r4)
2083 ld r22, VCPU_GPR(R22)(r4)
2084 ld r23, VCPU_GPR(R23)(r4)
2085 ld r24, VCPU_GPR(R24)(r4)
2086 ld r25, VCPU_GPR(R25)(r4)
2087 ld r26, VCPU_GPR(R26)(r4)
2088 ld r27, VCPU_GPR(R27)(r4)
2089 ld r28, VCPU_GPR(R28)(r4)
2090 ld r29, VCPU_GPR(R29)(r4)
2091 ld r30, VCPU_GPR(R30)(r4)
2092 ld r31, VCPU_GPR(R31)(r4)
2094 /* Check the wake reason in SRR1 to see why we got here */
2095 bl kvmppc_check_wake_reason
2097 /* clear our bit in vcore->napping_threads */
2098 34: ld r5,HSTATE_KVM_VCORE(r13)
2099 lbz r7,HSTATE_PTID(r13)
2102 addi r6,r5,VCORE_NAPPING_THREADS
2108 stb r0,HSTATE_NAPPING(r13)
2110 /* See if the wake reason means we need to exit */
2111 stw r12, VCPU_TRAP(r4)
2116 /* see if any other thread is already exiting */
2117 lwz r0,VCORE_ENTRY_EXIT(r5)
2121 b kvmppc_cede_reentry /* if not go back to guest */
2123 /* cede when already previously prodded case */
2126 stb r0,VCPU_PRODDED(r3)
2127 sync /* order testing prodded vs. clearing ceded */
2128 stb r0,VCPU_CEDED(r3)
2132 /* we've ceded but we want to give control to the host */
2134 b hcall_real_fallback
2136 /* Try to handle a machine check in real mode */
2137 machine_check_realmode:
2138 mr r3, r9 /* get vcpu pointer */
2139 bl .kvmppc_realmode_machine_check
2141 cmpdi r3, 0 /* continue exiting from guest? */
2142 ld r9, HSTATE_KVM_VCPU(r13)
2143 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2145 /* If not, deliver a machine check. SRR0/1 are already set */
2146 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2147 bl kvmppc_msr_interrupt
2148 b fast_interrupt_c_return
2151 * Check the reason we woke from nap, and take appropriate action.
2153 * 0 if nothing needs to be done
2154 * 1 if something happened that needs to be handled by the host
2155 * -1 if there was a guest wakeup (IPI)
2157 * Also sets r12 to the interrupt vector for any interrupt that needs
2158 * to be handled now by the host (0x500 for external interrupt), or zero.
2160 kvmppc_check_wake_reason:
2163 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2165 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2166 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2167 cmpwi r6, 8 /* was it an external interrupt? */
2168 li r12, BOOK3S_INTERRUPT_EXTERNAL
2169 beq kvmppc_read_intr /* if so, see what it was */
2172 cmpwi r6, 6 /* was it the decrementer? */
2175 cmpwi r6, 5 /* privileged doorbell? */
2177 cmpwi r6, 3 /* hypervisor doorbell? */
2179 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2180 li r3, 1 /* anything else, return 1 */
2183 /* hypervisor doorbell */
2184 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2189 * Determine what sort of external interrupt is pending (if any).
2191 * 0 if no interrupt is pending
2192 * 1 if an interrupt is pending that needs to be handled by the host
2193 * -1 if there was a guest wakeup IPI (which has now been cleared)
2196 /* see if a host IPI is pending */
2198 lbz r0, HSTATE_HOST_IPI(r13)
2202 /* Now read the interrupt from the ICP */
2203 ld r6, HSTATE_XICS_PHYS(r13)
2208 rlwinm. r3, r0, 0, 0xffffff
2210 beq 1f /* if nothing pending in the ICP */
2212 /* We found something in the ICP...
2214 * If it's not an IPI, stash it in the PACA and return to
2215 * the host, we don't (yet) handle directing real external
2216 * interrupts directly to the guest
2218 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2221 /* It's an IPI, clear the MFRR and EOI it */
2224 stbcix r3, r6, r8 /* clear the IPI */
2225 stwcix r0, r6, r7 /* EOI it */
2228 /* We need to re-check host IPI now in case it got set in the
2229 * meantime. If it's clear, we bounce the interrupt to the
2232 lbz r0, HSTATE_HOST_IPI(r13)
2236 /* OK, it's an IPI for us */
2240 42: /* It's not an IPI and it's for the host, stash it in the PACA
2241 * before exit, it will be picked up by the host ICP driver
2243 stw r0, HSTATE_SAVED_XIRR(r13)
2247 43: /* We raced with the host, we need to resend that IPI, bummer */
2249 stbcix r0, r6, r8 /* set the IPI */
2255 * Save away FP, VMX and VSX registers.
2257 * N.B. r30 and r31 are volatile across this function,
2258 * thus it is not callable from C.
2265 #ifdef CONFIG_ALTIVEC
2267 oris r8,r8,MSR_VEC@h
2268 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2272 oris r8,r8,MSR_VSX@h
2273 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2277 addi r3,r3,VCPU_FPRS
2279 #ifdef CONFIG_ALTIVEC
2281 addi r3,r31,VCPU_VRS
2283 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2285 mfspr r6,SPRN_VRSAVE
2286 stw r6,VCPU_VRSAVE(r31)
2291 * Load up FP, VMX and VSX registers
2293 * N.B. r30 and r31 are volatile across this function,
2294 * thus it is not callable from C.
2301 #ifdef CONFIG_ALTIVEC
2303 oris r8,r8,MSR_VEC@h
2304 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2308 oris r8,r8,MSR_VSX@h
2309 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2313 addi r3,r4,VCPU_FPRS
2315 #ifdef CONFIG_ALTIVEC
2317 addi r3,r31,VCPU_VRS
2319 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2321 lwz r7,VCPU_VRSAVE(r31)
2322 mtspr SPRN_VRSAVE,r7
2328 * We come here if we get any exception or interrupt while we are
2329 * executing host real mode code while in guest MMU context.
2330 * For now just spin, but we should do something better.
2332 kvmppc_bad_host_intr:
2336 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2337 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2338 * r11 has the guest MSR value (in/out)
2339 * r9 has a vcpu pointer (in)
2340 * r0 is used as a scratch register
2342 kvmppc_msr_interrupt:
2343 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2344 cmpwi r0, 2 /* Check if we are in transactional state.. */
2345 ld r11, VCPU_INTR_MSR(r9)
2347 /* ... if transactional, change to suspended */
2349 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2353 * This works around a hardware bug on POWER8E processors, where
2354 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2355 * performance monitor interrupt. Instead, when we need to have
2356 * an interrupt pending, we have to arrange for a counter to overflow.
2360 mtspr SPRN_MMCR2, r3
2361 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2362 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2363 mtspr SPRN_MMCR0, r3