2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
33 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
35 /* Values in HSTATE_NAPPING(r13) */
36 #define NAPPING_CEDE 1
37 #define NAPPING_NOVCPU 2
40 * Call kvmppc_hv_entry in real mode.
41 * Must be called with interrupts hard-disabled.
45 * LR = return address to continue at after eventually re-enabling MMU
47 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
49 std r0, PPC_LR_STKOFF(r1)
52 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
57 mtmsrd r0,1 /* clear RI in MSR */
63 ld r4, HSTATE_KVM_VCPU(r13)
66 /* Back from guest - restore host state and return to caller */
69 /* Restore host DABR and DABRX */
70 ld r5,HSTATE_DABR(r13)
74 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
77 ld r3,PACA_SPRG_VDSO(r13)
78 mtspr SPRN_SPRG_VDSO_WRITE,r3
80 /* Reload the host's PMU registers */
81 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
82 lbz r4, LPPACA_PMCINUSE(r3)
84 beq 23f /* skip if not */
86 ld r3, HSTATE_MMCR0(r13)
87 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
90 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
91 lwz r3, HSTATE_PMC1(r13)
92 lwz r4, HSTATE_PMC2(r13)
93 lwz r5, HSTATE_PMC3(r13)
94 lwz r6, HSTATE_PMC4(r13)
95 lwz r8, HSTATE_PMC5(r13)
96 lwz r9, HSTATE_PMC6(r13)
103 ld r3, HSTATE_MMCR0(r13)
104 ld r4, HSTATE_MMCR1(r13)
105 ld r5, HSTATE_MMCRA(r13)
106 ld r6, HSTATE_SIAR(r13)
107 ld r7, HSTATE_SDAR(r13)
113 ld r8, HSTATE_MMCR2(r13)
114 ld r9, HSTATE_SIER(r13)
117 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
123 * Reload DEC. HDEC interrupts were disabled when
124 * we reloaded the host's LPCR value.
126 ld r3, HSTATE_DECEXP(r13)
131 /* hwthread_req may have got set by cede or no vcpu, so clear it */
133 stb r0, HSTATE_HWTHREAD_REQ(r13)
136 * For external and machine check interrupts, we need
137 * to call the Linux handler to process the interrupt.
138 * We do that by jumping to absolute address 0x500 for
139 * external interrupts, or the machine_check_fwnmi label
140 * for machine checks (since firmware might have patched
141 * the vector area at 0x200). The [h]rfid at the end of the
142 * handler will return to the book3s_hv_interrupts.S code.
143 * For other interrupts we do the rfid to get back
144 * to the book3s_hv_interrupts.S code here.
146 ld r8, 112+PPC_LR_STKOFF(r1)
148 ld r7, HSTATE_HOST_MSR(r13)
150 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
151 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
153 cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI
154 beq cr2, 14f /* HMI check */
156 /* RFI into the highmem handler, or branch to interrupt handler */
160 mtmsrd r6, 1 /* Clear RI in MSR */
163 beq cr1, 13f /* machine check */
166 /* On POWER7, we have external interrupts set to use HSRR0/1 */
167 11: mtspr SPRN_HSRR0, r8
171 13: b machine_check_fwnmi
173 14: mtspr SPRN_HSRR0, r8
175 b hmi_exception_after_realmode
177 kvmppc_primary_no_guest:
178 /* We handle this much like a ceded vcpu */
179 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
183 * Make sure the primary has finished the MMU switch.
184 * We should never get here on a secondary thread, but
185 * check it for robustness' sake.
187 ld r5, HSTATE_KVM_VCORE(r13)
188 65: lbz r0, VCORE_IN_GUEST(r5)
195 /* set our bit in napping_threads */
196 ld r5, HSTATE_KVM_VCORE(r13)
197 lbz r7, HSTATE_PTID(r13)
200 addi r6, r5, VCORE_NAPPING_THREADS
205 /* order napping_threads update vs testing entry_exit_map */
208 lwz r7, VCORE_ENTRY_EXIT(r5)
210 bge kvm_novcpu_exit /* another thread already exiting */
211 li r3, NAPPING_NOVCPU
212 stb r3, HSTATE_NAPPING(r13)
214 li r3, 0 /* Don't wake on privileged (OS) doorbell */
218 ld r1, HSTATE_HOST_R1(r13)
219 ld r5, HSTATE_KVM_VCORE(r13)
221 stb r0, HSTATE_NAPPING(r13)
223 /* check the wake reason */
224 bl kvmppc_check_wake_reason
226 /* see if any other thread is already exiting */
227 lwz r0, VCORE_ENTRY_EXIT(r5)
231 /* clear our bit in napping_threads */
232 lbz r7, HSTATE_PTID(r13)
235 addi r6, r5, VCORE_NAPPING_THREADS
241 /* See if the wake reason means we need to exit */
245 /* See if our timeslice has expired (HDEC is negative) */
247 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
251 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
252 ld r4, HSTATE_KVM_VCPU(r13)
254 beq kvmppc_primary_no_guest
256 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
257 addi r3, r4, VCPU_TB_RMENTRY
258 bl kvmhv_start_timing
263 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
264 ld r4, HSTATE_KVM_VCPU(r13)
267 addi r3, r4, VCPU_TB_RMEXIT
268 bl kvmhv_accumulate_time
272 bl kvmhv_commence_exit
275 b kvmhv_switch_to_host
278 * We come in here when wakened from nap mode.
279 * Relocation is off and most register values are lost.
280 * r13 points to the PACA.
282 .globl kvm_start_guest
285 /* Set runlatch bit the minute you wake up from nap */
292 li r0,KVM_HWTHREAD_IN_KVM
293 stb r0,HSTATE_HWTHREAD_STATE(r13)
295 /* NV GPR values from power7_idle() will no longer be valid */
297 stb r0,PACA_NAPSTATELOST(r13)
299 /* were we napping due to cede? */
300 lbz r0,HSTATE_NAPPING(r13)
301 cmpwi r0,NAPPING_CEDE
303 cmpwi r0,NAPPING_NOVCPU
304 beq kvm_novcpu_wakeup
306 ld r1,PACAEMERGSP(r13)
307 subi r1,r1,STACK_FRAME_OVERHEAD
310 * We weren't napping due to cede, so this must be a secondary
311 * thread being woken up to run a guest, or being woken up due
312 * to a stray IPI. (Or due to some machine check or hypervisor
313 * maintenance interrupt while the core is in KVM.)
316 /* Check the wake reason in SRR1 to see why we got here */
317 bl kvmppc_check_wake_reason
321 /* get vcore pointer, NULL if we have nothing to run */
322 ld r5,HSTATE_KVM_VCORE(r13)
324 /* if we have no vcore to run, go back to sleep */
327 kvm_secondary_got_guest:
329 /* Set HSTATE_DSCR(r13) to something sensible */
330 ld r6, PACA_DSCR_DEFAULT(r13)
331 std r6, HSTATE_DSCR(r13)
333 /* On thread 0 of a subcore, set HDEC to max */
334 lbz r4, HSTATE_PTID(r13)
340 /* and set per-LPAR registers, if doing dynamic micro-threading */
341 ld r6, HSTATE_SPLIT_MODE(r13)
344 ld r0, KVM_SPLIT_RPR(r6)
346 ld r0, KVM_SPLIT_PMMAR(r6)
348 ld r0, KVM_SPLIT_LDBAR(r6)
352 /* Order load of vcpu after load of vcore */
354 ld r4, HSTATE_KVM_VCPU(r13)
357 /* Back from the guest, go back to nap */
358 /* Clear our vcpu and vcore pointers so we don't come back in early */
360 std r0, HSTATE_KVM_VCPU(r13)
362 * Once we clear HSTATE_KVM_VCORE(r13), the code in
363 * kvmppc_run_core() is going to assume that all our vcpu
364 * state is visible in memory. This lwsync makes sure
368 std r0, HSTATE_KVM_VCORE(r13)
371 * At this point we have finished executing in the guest.
372 * We need to wait for hwthread_req to become zero, since
373 * we may not turn on the MMU while hwthread_req is non-zero.
374 * While waiting we also need to check if we get given a vcpu to run.
377 lbz r3, HSTATE_HWTHREAD_REQ(r13)
381 li r0, KVM_HWTHREAD_IN_KERNEL
382 stb r0, HSTATE_HWTHREAD_STATE(r13)
383 /* need to recheck hwthread_req after a barrier, to avoid race */
385 lbz r3, HSTATE_HWTHREAD_REQ(r13)
389 * We jump to power7_wakeup_loss, which will return to the caller
390 * of power7_nap in the powernv cpu offline loop. The value we
391 * put in r3 becomes the return value for power7_nap.
395 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
401 ld r5, HSTATE_KVM_VCORE(r13)
404 ld r3, HSTATE_SPLIT_MODE(r13)
407 lbz r0, KVM_SPLIT_DO_NAP(r3)
413 b kvm_secondary_got_guest
415 54: li r0, KVM_HWTHREAD_IN_KVM
416 stb r0, HSTATE_HWTHREAD_STATE(r13)
420 * Here the primary thread is trying to return the core to
421 * whole-core mode, so we need to nap.
424 /* clear any pending message */
426 lis r6, (PPC_DBELL_SERVER << (63-36))@h
428 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
429 /* Set kvm_split_mode.napped[tid] = 1 */
430 ld r3, HSTATE_SPLIT_MODE(r13)
432 lhz r4, PACAPACAINDEX(r13)
433 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
434 addi r4, r4, KVM_SPLIT_NAPPED
436 /* Check the do_nap flag again after setting napped[] */
438 lbz r0, KVM_SPLIT_DO_NAP(r3)
441 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
443 rlwimi r4, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
446 std r0, HSTATE_SCRATCH0(r13)
448 ld r0, HSTATE_SCRATCH0(r13)
458 /******************************************************************************
462 *****************************************************************************/
464 .global kvmppc_hv_entry
469 * R4 = vcpu pointer (or NULL)
474 * all other volatile GPRS = free
477 std r0, PPC_LR_STKOFF(r1)
480 /* Save R1 in the PACA */
481 std r1, HSTATE_HOST_R1(r13)
483 li r6, KVM_GUEST_MODE_HOST_HV
484 stb r6, HSTATE_IN_GUEST(r13)
486 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
487 /* Store initial timestamp */
490 addi r3, r4, VCPU_TB_RMENTRY
491 bl kvmhv_start_timing
501 * POWER7/POWER8 host -> guest partition switch code.
502 * We don't have to lock against concurrent tlbies,
503 * but we do have to coordinate across hardware threads.
505 /* Set bit in entry map iff exit map is zero. */
506 ld r5, HSTATE_KVM_VCORE(r13)
508 lbz r6, HSTATE_PTID(r13)
510 addi r9, r5, VCORE_ENTRY_EXIT
512 cmpwi r3, 0x100 /* any threads starting to exit? */
513 bge secondary_too_late /* if so we're too late to the party */
518 /* Primary thread switches to guest partition. */
519 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
524 li r0,LPID_RSVD /* switch to reserved LPID */
527 mtspr SPRN_SDR1,r6 /* switch to partition page table */
531 /* See if we need to flush the TLB */
532 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
533 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
534 srdi r6,r6,6 /* doubleword number */
535 sldi r6,r6,3 /* address offset */
537 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
543 23: ldarx r7,0,r6 /* if set, clear the bit */
547 /* Flush the TLB of any entries for this LPID */
548 /* use arch 2.07S as a proxy for POWER8 */
550 li r6,512 /* POWER8 has 512 sets */
552 li r6,128 /* POWER7 has 128 sets */
553 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
555 li r7,0x800 /* IS field = 0b10 */
562 /* Add timebase offset onto timebase */
563 22: ld r8,VCORE_TB_OFFSET(r5)
566 mftb r6 /* current host timebase */
568 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
569 mftb r7 /* check if lower 24 bits overflowed */
574 addis r8,r8,0x100 /* if so, increment upper 40 bits */
577 /* Load guest PCR value to select appropriate compat mode */
578 37: ld r7, VCORE_PCR(r5)
585 /* DPDES is shared between threads */
586 ld r8, VCORE_DPDES(r5)
588 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
591 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
593 /* Do we have a guest vcpu to run? */
595 beq kvmppc_primary_no_guest
598 /* Load up guest SLB entries */
599 lwz r5,VCPU_SLB_MAX(r4)
604 1: ld r8,VCPU_SLB_E(r6)
607 addi r6,r6,VCPU_SLB_SIZE
610 /* Increment yield count if they have a VPA */
614 li r6, LPPACA_YIELDCOUNT
619 stb r6, VCPU_VPA_DIRTY(r4)
622 /* Save purr/spurr */
625 std r5,HSTATE_PURR(r13)
626 std r6,HSTATE_SPURR(r13)
633 /* Set partition DABR */
634 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
635 lwz r5,VCPU_DABRX(r4)
640 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
642 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
645 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
647 /* Turn on TM/FP/VSX/VMX so we can restore them. */
653 oris r5, r5, (MSR_VEC | MSR_VSX)@h
657 * The user may change these outside of a transaction, so they must
658 * always be context switched.
660 ld r5, VCPU_TFHAR(r4)
661 ld r6, VCPU_TFIAR(r4)
662 ld r7, VCPU_TEXASR(r4)
665 mtspr SPRN_TEXASR, r7
668 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
669 beq skip_tm /* TM not active in guest */
671 /* Make sure the failure summary is set, otherwise we'll program check
672 * when we trechkpt. It's possible that this might have been not set
673 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
676 oris r7, r7, (TEXASR_FS)@h
677 mtspr SPRN_TEXASR, r7
680 * We need to load up the checkpointed state for the guest.
681 * We need to do this early as it will blow away any GPRs, VSRs and
686 addi r3, r31, VCPU_FPRS_TM
688 addi r3, r31, VCPU_VRS_TM
691 lwz r7, VCPU_VRSAVE_TM(r4)
692 mtspr SPRN_VRSAVE, r7
694 ld r5, VCPU_LR_TM(r4)
695 lwz r6, VCPU_CR_TM(r4)
696 ld r7, VCPU_CTR_TM(r4)
697 ld r8, VCPU_AMR_TM(r4)
698 ld r9, VCPU_TAR_TM(r4)
706 * Load up PPR and DSCR values but don't put them in the actual SPRs
707 * till the last moment to avoid running with userspace PPR and DSCR for
710 ld r29, VCPU_DSCR_TM(r4)
711 ld r30, VCPU_PPR_TM(r4)
713 std r2, PACATMSCRATCH(r13) /* Save TOC */
715 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
719 /* Load GPRs r0-r28 */
722 ld reg, VCPU_GPRS_TM(reg)(r31)
729 /* Load final GPRs */
730 ld 29, VCPU_GPRS_TM(29)(r31)
731 ld 30, VCPU_GPRS_TM(30)(r31)
732 ld 31, VCPU_GPRS_TM(31)(r31)
734 /* TM checkpointed state is now setup. All GPRs are now volatile. */
737 /* Now let's get back the state we need. */
740 ld r29, HSTATE_DSCR(r13)
742 ld r4, HSTATE_KVM_VCPU(r13)
743 ld r1, HSTATE_HOST_R1(r13)
744 ld r2, PACATMSCRATCH(r13)
746 /* Set the MSR RI since we have our registers back. */
752 /* Load guest PMU registers */
753 /* R4 is live here (vcpu pointer) */
755 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
756 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
760 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
763 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
764 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
765 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
766 lwz r6, VCPU_PMC + 8(r4)
767 lwz r7, VCPU_PMC + 12(r4)
768 lwz r8, VCPU_PMC + 16(r4)
769 lwz r9, VCPU_PMC + 20(r4)
777 ld r5, VCPU_MMCR + 8(r4)
778 ld r6, VCPU_MMCR + 16(r4)
786 ld r5, VCPU_MMCR + 24(r4)
788 lwz r7, VCPU_PMC + 24(r4)
789 lwz r8, VCPU_PMC + 28(r4)
790 ld r9, VCPU_MMCR + 32(r4)
796 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
800 /* Load up FP, VMX and VSX registers */
803 ld r14, VCPU_GPR(R14)(r4)
804 ld r15, VCPU_GPR(R15)(r4)
805 ld r16, VCPU_GPR(R16)(r4)
806 ld r17, VCPU_GPR(R17)(r4)
807 ld r18, VCPU_GPR(R18)(r4)
808 ld r19, VCPU_GPR(R19)(r4)
809 ld r20, VCPU_GPR(R20)(r4)
810 ld r21, VCPU_GPR(R21)(r4)
811 ld r22, VCPU_GPR(R22)(r4)
812 ld r23, VCPU_GPR(R23)(r4)
813 ld r24, VCPU_GPR(R24)(r4)
814 ld r25, VCPU_GPR(R25)(r4)
815 ld r26, VCPU_GPR(R26)(r4)
816 ld r27, VCPU_GPR(R27)(r4)
817 ld r28, VCPU_GPR(R28)(r4)
818 ld r29, VCPU_GPR(R29)(r4)
819 ld r30, VCPU_GPR(R30)(r4)
820 ld r31, VCPU_GPR(R31)(r4)
822 /* Switch DSCR to guest value */
827 /* Skip next section on POWER7 */
829 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
830 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
833 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
836 /* Load up POWER8-specific registers */
838 lwz r6, VCPU_PSPB(r4)
844 ld r6, VCPU_DAWRX(r4)
845 ld r7, VCPU_CIABR(r4)
855 ld r8, VCPU_EBBHR(r4)
857 ld r5, VCPU_EBBRR(r4)
858 ld r6, VCPU_BESCR(r4)
859 ld r7, VCPU_CSIGR(r4)
865 ld r5, VCPU_TCSCR(r4)
867 lwz r7, VCPU_GUEST_PID(r4)
876 * Set the decrementer to the guest decrementer.
878 ld r8,VCPU_DEC_EXPIRES(r4)
879 /* r8 is a host timebase value here, convert to guest TB */
880 ld r5,HSTATE_KVM_VCORE(r13)
881 ld r6,VCORE_TB_OFFSET(r5)
888 ld r5, VCPU_SPRG0(r4)
889 ld r6, VCPU_SPRG1(r4)
890 ld r7, VCPU_SPRG2(r4)
891 ld r8, VCPU_SPRG3(r4)
897 /* Load up DAR and DSISR */
899 lwz r6, VCPU_DSISR(r4)
903 /* Restore AMR and UAMOR, set AMOR to all 1s */
911 /* Restore state of CTRL run bit; assume 1 on entry */
919 /* Secondary threads wait for primary to have done partition switch */
920 ld r5, HSTATE_KVM_VCORE(r13)
921 lbz r6, HSTATE_PTID(r13)
924 lbz r0, VCORE_IN_GUEST(r5)
928 20: lwz r3, VCORE_ENTRY_EXIT(r5)
931 lbz r0, VCORE_IN_GUEST(r5)
941 /* Check if HDEC expires soon */
943 cmpwi r3, 512 /* 1 microsecond */
952 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
960 deliver_guest_interrupt:
961 /* r11 = vcpu->arch.msr & ~MSR_HV */
962 rldicl r11, r11, 63 - MSR_HV_LG, 1
963 rotldi r11, r11, 1 + MSR_HV_LG
966 /* Check if we can deliver an external or decrementer interrupt now */
967 ld r0, VCPU_PENDING_EXC(r4)
968 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
970 andi. r8, r11, MSR_EE
972 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
973 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
977 li r0, BOOK3S_INTERRUPT_EXTERNAL
981 li r0, BOOK3S_INTERRUPT_DECREMENTER
984 12: mtspr SPRN_SRR0, r10
988 bl kvmppc_msr_interrupt
994 * R10: value for HSRR0
995 * R11: value for HSRR1
1000 stb r0,VCPU_CEDED(r4) /* cancel cede */
1001 mtspr SPRN_HSRR0,r10
1002 mtspr SPRN_HSRR1,r11
1004 /* Activate guest mode, so faults get handled by KVM */
1005 li r9, KVM_GUEST_MODE_GUEST_HV
1006 stb r9, HSTATE_IN_GUEST(r13)
1008 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1009 /* Accumulate timing */
1010 addi r3, r4, VCPU_TB_GUEST
1011 bl kvmhv_accumulate_time
1017 ld r5, VCPU_CFAR(r4)
1019 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1022 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1029 ld r1, VCPU_GPR(R1)(r4)
1030 ld r2, VCPU_GPR(R2)(r4)
1031 ld r3, VCPU_GPR(R3)(r4)
1032 ld r5, VCPU_GPR(R5)(r4)
1033 ld r6, VCPU_GPR(R6)(r4)
1034 ld r7, VCPU_GPR(R7)(r4)
1035 ld r8, VCPU_GPR(R8)(r4)
1036 ld r9, VCPU_GPR(R9)(r4)
1037 ld r10, VCPU_GPR(R10)(r4)
1038 ld r11, VCPU_GPR(R11)(r4)
1039 ld r12, VCPU_GPR(R12)(r4)
1040 ld r13, VCPU_GPR(R13)(r4)
1044 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1045 ld r0, VCPU_GPR(R0)(r4)
1046 ld r4, VCPU_GPR(R4)(r4)
1055 stw r12, VCPU_TRAP(r4)
1056 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1057 addi r3, r4, VCPU_TB_RMEXIT
1058 bl kvmhv_accumulate_time
1060 11: b kvmhv_switch_to_host
1067 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1068 12: stw r12, VCPU_TRAP(r4)
1070 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1071 addi r3, r4, VCPU_TB_RMEXIT
1072 bl kvmhv_accumulate_time
1076 /******************************************************************************
1080 *****************************************************************************/
1083 * We come here from the first-level interrupt handlers.
1085 .globl kvmppc_interrupt_hv
1086 kvmppc_interrupt_hv:
1088 * Register contents:
1089 * R12 = interrupt vector
1091 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1092 * guest R13 saved in SPRN_SCRATCH0
1094 std r9, HSTATE_SCRATCH2(r13)
1096 lbz r9, HSTATE_IN_GUEST(r13)
1097 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1098 beq kvmppc_bad_host_intr
1099 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1100 cmpwi r9, KVM_GUEST_MODE_GUEST
1101 ld r9, HSTATE_SCRATCH2(r13)
1102 beq kvmppc_interrupt_pr
1104 /* We're now back in the host but in guest MMU context */
1105 li r9, KVM_GUEST_MODE_HOST_HV
1106 stb r9, HSTATE_IN_GUEST(r13)
1108 ld r9, HSTATE_KVM_VCPU(r13)
1110 /* Save registers */
1112 std r0, VCPU_GPR(R0)(r9)
1113 std r1, VCPU_GPR(R1)(r9)
1114 std r2, VCPU_GPR(R2)(r9)
1115 std r3, VCPU_GPR(R3)(r9)
1116 std r4, VCPU_GPR(R4)(r9)
1117 std r5, VCPU_GPR(R5)(r9)
1118 std r6, VCPU_GPR(R6)(r9)
1119 std r7, VCPU_GPR(R7)(r9)
1120 std r8, VCPU_GPR(R8)(r9)
1121 ld r0, HSTATE_SCRATCH2(r13)
1122 std r0, VCPU_GPR(R9)(r9)
1123 std r10, VCPU_GPR(R10)(r9)
1124 std r11, VCPU_GPR(R11)(r9)
1125 ld r3, HSTATE_SCRATCH0(r13)
1126 lwz r4, HSTATE_SCRATCH1(r13)
1127 std r3, VCPU_GPR(R12)(r9)
1130 ld r3, HSTATE_CFAR(r13)
1131 std r3, VCPU_CFAR(r9)
1132 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1134 ld r4, HSTATE_PPR(r13)
1135 std r4, VCPU_PPR(r9)
1136 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1138 /* Restore R1/R2 so we can handle faults */
1139 ld r1, HSTATE_HOST_R1(r13)
1142 mfspr r10, SPRN_SRR0
1143 mfspr r11, SPRN_SRR1
1144 std r10, VCPU_SRR0(r9)
1145 std r11, VCPU_SRR1(r9)
1146 andi. r0, r12, 2 /* need to read HSRR0/1? */
1148 mfspr r10, SPRN_HSRR0
1149 mfspr r11, SPRN_HSRR1
1151 1: std r10, VCPU_PC(r9)
1152 std r11, VCPU_MSR(r9)
1156 std r3, VCPU_GPR(R13)(r9)
1159 stw r12,VCPU_TRAP(r9)
1161 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1162 addi r3, r9, VCPU_TB_RMINTR
1164 bl kvmhv_accumulate_time
1165 ld r5, VCPU_GPR(R5)(r9)
1166 ld r6, VCPU_GPR(R6)(r9)
1167 ld r7, VCPU_GPR(R7)(r9)
1168 ld r8, VCPU_GPR(R8)(r9)
1171 /* Save HEIR (HV emulation assist reg) in emul_inst
1172 if this is an HEI (HV emulation interrupt, e40) */
1173 li r3,KVM_INST_FETCH_FAILED
1174 stw r3,VCPU_LAST_INST(r9)
1175 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1178 11: stw r3,VCPU_HEIR(r9)
1180 /* these are volatile across C function calls */
1183 std r3, VCPU_CTR(r9)
1184 stw r4, VCPU_XER(r9)
1186 /* If this is a page table miss then see if it's theirs or ours */
1187 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1189 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1192 /* See if this is a leftover HDEC interrupt */
1193 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1198 bge fast_guest_return
1200 /* See if this is an hcall we can handle in real mode */
1201 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1202 beq hcall_try_real_mode
1204 /* Hypervisor doorbell - exit only if host IPI flag set */
1205 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1207 lbz r0, HSTATE_HOST_IPI(r13)
1211 /* External interrupt ? */
1212 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1213 bne+ guest_exit_cont
1215 /* External interrupt, first check for host_ipi. If this is
1216 * set, we know the host wants us out so let's do it now
1222 /* Check if any CPU is heading out to the host, if so head out too */
1223 4: ld r5, HSTATE_KVM_VCORE(r13)
1224 lwz r0, VCORE_ENTRY_EXIT(r5)
1227 blt deliver_guest_interrupt
1229 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1230 /* Save more register state */
1233 std r6, VCPU_DAR(r9)
1234 stw r7, VCPU_DSISR(r9)
1235 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1236 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1238 std r6, VCPU_FAULT_DAR(r9)
1239 stw r7, VCPU_FAULT_DSISR(r9)
1241 /* See if it is a machine check */
1242 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1243 beq machine_check_realmode
1245 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1246 addi r3, r9, VCPU_TB_RMEXIT
1248 bl kvmhv_accumulate_time
1251 /* Increment exit count, poke other threads to exit */
1252 bl kvmhv_commence_exit
1254 ld r9, HSTATE_KVM_VCPU(r13)
1255 lwz r12, VCPU_TRAP(r9)
1257 /* Stop others sending VCPU interrupts to this physical CPU */
1259 stw r0, VCPU_CPU(r9)
1260 stw r0, VCPU_THREAD_CPU(r9)
1262 /* Save guest CTRL register, set runlatch to 1 */
1264 stw r6,VCPU_CTRL(r9)
1270 /* Read the guest SLB and save it away */
1271 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1277 andis. r0,r8,SLB_ESID_V@h
1279 add r8,r8,r6 /* put index in */
1281 std r8,VCPU_SLB_E(r7)
1282 std r3,VCPU_SLB_V(r7)
1283 addi r7,r7,VCPU_SLB_SIZE
1287 stw r5,VCPU_SLB_MAX(r9)
1290 * Save the guest PURR/SPURR
1295 ld r8,VCPU_SPURR(r9)
1296 std r5,VCPU_PURR(r9)
1297 std r6,VCPU_SPURR(r9)
1302 * Restore host PURR/SPURR and add guest times
1303 * so that the time in the guest gets accounted.
1305 ld r3,HSTATE_PURR(r13)
1306 ld r4,HSTATE_SPURR(r13)
1317 /* r5 is a guest timebase value here, convert to host TB */
1318 ld r3,HSTATE_KVM_VCORE(r13)
1319 ld r4,VCORE_TB_OFFSET(r3)
1321 std r5,VCPU_DEC_EXPIRES(r9)
1325 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1326 /* Save POWER8-specific registers */
1330 std r5, VCPU_IAMR(r9)
1331 stw r6, VCPU_PSPB(r9)
1332 std r7, VCPU_FSCR(r9)
1337 std r6, VCPU_VTB(r9)
1338 std r7, VCPU_TAR(r9)
1339 mfspr r8, SPRN_EBBHR
1340 std r8, VCPU_EBBHR(r9)
1341 mfspr r5, SPRN_EBBRR
1342 mfspr r6, SPRN_BESCR
1343 mfspr r7, SPRN_CSIGR
1345 std r5, VCPU_EBBRR(r9)
1346 std r6, VCPU_BESCR(r9)
1347 std r7, VCPU_CSIGR(r9)
1348 std r8, VCPU_TACR(r9)
1349 mfspr r5, SPRN_TCSCR
1353 std r5, VCPU_TCSCR(r9)
1354 std r6, VCPU_ACOP(r9)
1355 stw r7, VCPU_GUEST_PID(r9)
1356 std r8, VCPU_WORT(r9)
1359 /* Save and reset AMR and UAMOR before turning on the MMU */
1363 std r6,VCPU_UAMOR(r9)
1367 /* Switch DSCR back to host value */
1369 ld r7, HSTATE_DSCR(r13)
1370 std r8, VCPU_DSCR(r9)
1373 /* Save non-volatile GPRs */
1374 std r14, VCPU_GPR(R14)(r9)
1375 std r15, VCPU_GPR(R15)(r9)
1376 std r16, VCPU_GPR(R16)(r9)
1377 std r17, VCPU_GPR(R17)(r9)
1378 std r18, VCPU_GPR(R18)(r9)
1379 std r19, VCPU_GPR(R19)(r9)
1380 std r20, VCPU_GPR(R20)(r9)
1381 std r21, VCPU_GPR(R21)(r9)
1382 std r22, VCPU_GPR(R22)(r9)
1383 std r23, VCPU_GPR(R23)(r9)
1384 std r24, VCPU_GPR(R24)(r9)
1385 std r25, VCPU_GPR(R25)(r9)
1386 std r26, VCPU_GPR(R26)(r9)
1387 std r27, VCPU_GPR(R27)(r9)
1388 std r28, VCPU_GPR(R28)(r9)
1389 std r29, VCPU_GPR(R29)(r9)
1390 std r30, VCPU_GPR(R30)(r9)
1391 std r31, VCPU_GPR(R31)(r9)
1394 mfspr r3, SPRN_SPRG0
1395 mfspr r4, SPRN_SPRG1
1396 mfspr r5, SPRN_SPRG2
1397 mfspr r6, SPRN_SPRG3
1398 std r3, VCPU_SPRG0(r9)
1399 std r4, VCPU_SPRG1(r9)
1400 std r5, VCPU_SPRG2(r9)
1401 std r6, VCPU_SPRG3(r9)
1407 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1410 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
1414 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1418 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
1419 beq 1f /* TM not active in guest. */
1421 li r3, TM_CAUSE_KVM_RESCHED
1423 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
1427 /* All GPRs are volatile at this point. */
1430 /* Temporarily store r13 and r9 so we have some regs to play with */
1433 std r9, PACATMSCRATCH(r13)
1434 ld r9, HSTATE_KVM_VCPU(r13)
1436 /* Get a few more GPRs free. */
1437 std r29, VCPU_GPRS_TM(29)(r9)
1438 std r30, VCPU_GPRS_TM(30)(r9)
1439 std r31, VCPU_GPRS_TM(31)(r9)
1441 /* Save away PPR and DSCR soon so don't run with user values. */
1444 mfspr r30, SPRN_DSCR
1445 ld r29, HSTATE_DSCR(r13)
1446 mtspr SPRN_DSCR, r29
1448 /* Save all but r9, r13 & r29-r31 */
1451 .if (reg != 9) && (reg != 13)
1452 std reg, VCPU_GPRS_TM(reg)(r9)
1456 /* ... now save r13 */
1458 std r4, VCPU_GPRS_TM(13)(r9)
1459 /* ... and save r9 */
1460 ld r4, PACATMSCRATCH(r13)
1461 std r4, VCPU_GPRS_TM(9)(r9)
1463 /* Reload stack pointer and TOC. */
1464 ld r1, HSTATE_HOST_R1(r13)
1467 /* Set MSR RI now we have r1 and r13 back. */
1471 /* Save away checkpinted SPRs. */
1472 std r31, VCPU_PPR_TM(r9)
1473 std r30, VCPU_DSCR_TM(r9)
1479 std r5, VCPU_LR_TM(r9)
1480 stw r6, VCPU_CR_TM(r9)
1481 std r7, VCPU_CTR_TM(r9)
1482 std r8, VCPU_AMR_TM(r9)
1483 std r10, VCPU_TAR_TM(r9)
1485 /* Restore r12 as trap number. */
1486 lwz r12, VCPU_TRAP(r9)
1489 addi r3, r9, VCPU_FPRS_TM
1491 addi r3, r9, VCPU_VRS_TM
1493 mfspr r6, SPRN_VRSAVE
1494 stw r6, VCPU_VRSAVE_TM(r9)
1497 * We need to save these SPRs after the treclaim so that the software
1498 * error code is recorded correctly in the TEXASR. Also the user may
1499 * change these outside of a transaction, so they must always be
1502 mfspr r5, SPRN_TFHAR
1503 mfspr r6, SPRN_TFIAR
1504 mfspr r7, SPRN_TEXASR
1505 std r5, VCPU_TFHAR(r9)
1506 std r6, VCPU_TFIAR(r9)
1507 std r7, VCPU_TEXASR(r9)
1511 /* Increment yield count if they have a VPA */
1512 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1515 li r4, LPPACA_YIELDCOUNT
1520 stb r3, VCPU_VPA_DIRTY(r9)
1522 /* Save PMU registers if requested */
1523 /* r8 and cr0.eq are live here */
1526 * POWER8 seems to have a hardware bug where setting
1527 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1528 * when some counters are already negative doesn't seem
1529 * to cause a performance monitor alert (and hence interrupt).
1530 * The effect of this is that when saving the PMU state,
1531 * if there is no PMU alert pending when we read MMCR0
1532 * before freezing the counters, but one becomes pending
1533 * before we read the counters, we lose it.
1534 * To work around this, we need a way to freeze the counters
1535 * before reading MMCR0. Normally, freezing the counters
1536 * is done by writing MMCR0 (to set MMCR0[FC]) which
1537 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1538 * we can also freeze the counters using MMCR2, by writing
1539 * 1s to all the counter freeze condition bits (there are
1540 * 9 bits each for 6 counters).
1542 li r3, -1 /* set all freeze bits */
1544 mfspr r10, SPRN_MMCR2
1545 mtspr SPRN_MMCR2, r3
1547 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1549 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1550 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1551 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1552 mfspr r6, SPRN_MMCRA
1553 /* Clear MMCRA in order to disable SDAR updates */
1555 mtspr SPRN_MMCRA, r7
1557 beq 21f /* if no VPA, save PMU stuff anyway */
1558 lbz r7, LPPACA_PMCINUSE(r8)
1559 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1561 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1563 21: mfspr r5, SPRN_MMCR1
1566 std r4, VCPU_MMCR(r9)
1567 std r5, VCPU_MMCR + 8(r9)
1568 std r6, VCPU_MMCR + 16(r9)
1570 std r10, VCPU_MMCR + 24(r9)
1571 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1572 std r7, VCPU_SIAR(r9)
1573 std r8, VCPU_SDAR(r9)
1580 stw r3, VCPU_PMC(r9)
1581 stw r4, VCPU_PMC + 4(r9)
1582 stw r5, VCPU_PMC + 8(r9)
1583 stw r6, VCPU_PMC + 12(r9)
1584 stw r7, VCPU_PMC + 16(r9)
1585 stw r8, VCPU_PMC + 20(r9)
1588 mfspr r6, SPRN_SPMC1
1589 mfspr r7, SPRN_SPMC2
1590 mfspr r8, SPRN_MMCRS
1591 std r5, VCPU_SIER(r9)
1592 stw r6, VCPU_PMC + 24(r9)
1593 stw r7, VCPU_PMC + 28(r9)
1594 std r8, VCPU_MMCR + 32(r9)
1596 mtspr SPRN_MMCRS, r4
1597 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1606 * POWER7/POWER8 guest -> host partition switch code.
1607 * We don't have to lock against tlbies but we do
1608 * have to coordinate the hardware threads.
1610 kvmhv_switch_to_host:
1611 /* Secondary threads wait for primary to do partition switch */
1612 ld r5,HSTATE_KVM_VCORE(r13)
1613 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1614 lbz r3,HSTATE_PTID(r13)
1618 13: lbz r3,VCORE_IN_GUEST(r5)
1624 /* Primary thread waits for all the secondaries to exit guest */
1625 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1626 rlwinm r0,r3,32-8,0xff
1632 /* Did we actually switch to the guest at all? */
1633 lbz r6, VCORE_IN_GUEST(r5)
1637 /* Primary thread switches back to host partition */
1638 ld r6,KVM_HOST_SDR1(r4)
1639 lwz r7,KVM_HOST_LPID(r4)
1640 li r8,LPID_RSVD /* switch to reserved LPID */
1643 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1648 /* DPDES is shared between threads */
1649 mfspr r7, SPRN_DPDES
1650 std r7, VCORE_DPDES(r5)
1651 /* clear DPDES so we don't get guest doorbells in the host */
1653 mtspr SPRN_DPDES, r8
1654 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1656 /* Subtract timebase offset from timebase */
1657 ld r8,VCORE_TB_OFFSET(r5)
1660 mftb r6 /* current guest timebase */
1662 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1663 mftb r7 /* check if lower 24 bits overflowed */
1668 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1672 17: ld r0, VCORE_PCR(r5)
1678 /* Signal secondary CPUs to continue */
1679 stb r0,VCORE_IN_GUEST(r5)
1680 19: lis r8,0x7fff /* MAX_INT@h */
1683 16: ld r8,KVM_HOST_LPCR(r4)
1687 /* load host SLB entries */
1688 ld r8,PACA_SLBSHADOWPTR(r13)
1690 .rept SLB_NUM_BOLTED
1691 li r3, SLBSHADOW_SAVEAREA
1695 andis. r7,r5,SLB_ESID_V@h
1701 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1702 /* Finish timing, if we have a vcpu */
1703 ld r4, HSTATE_KVM_VCPU(r13)
1707 bl kvmhv_accumulate_time
1710 /* Unset guest mode */
1711 li r0, KVM_GUEST_MODE_NONE
1712 stb r0, HSTATE_IN_GUEST(r13)
1714 ld r0, 112+PPC_LR_STKOFF(r1)
1720 * Check whether an HDSI is an HPTE not found fault or something else.
1721 * If it is an HPTE not found fault that is due to the guest accessing
1722 * a page that they have mapped but which we have paged out, then
1723 * we continue on with the guest exit path. In all other cases,
1724 * reflect the HDSI to the guest as a DSI.
1728 mfspr r6, SPRN_HDSISR
1729 /* HPTE not found fault or protection fault? */
1730 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1731 beq 1f /* if not, send it to the guest */
1732 andi. r0, r11, MSR_DR /* data relocation enabled? */
1735 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1736 bne 1f /* if no SLB entry found */
1737 4: std r4, VCPU_FAULT_DAR(r9)
1738 stw r6, VCPU_FAULT_DSISR(r9)
1740 /* Search the hash table. */
1741 mr r3, r9 /* vcpu pointer */
1742 li r7, 1 /* data fault */
1743 bl kvmppc_hpte_hv_fault
1744 ld r9, HSTATE_KVM_VCPU(r13)
1746 ld r11, VCPU_MSR(r9)
1747 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1748 cmpdi r3, 0 /* retry the instruction */
1750 cmpdi r3, -1 /* handle in kernel mode */
1752 cmpdi r3, -2 /* MMIO emulation; need instr word */
1755 /* Synthesize a DSI for the guest */
1756 ld r4, VCPU_FAULT_DAR(r9)
1758 1: mtspr SPRN_DAR, r4
1759 mtspr SPRN_DSISR, r6
1760 mtspr SPRN_SRR0, r10
1761 mtspr SPRN_SRR1, r11
1762 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1763 bl kvmppc_msr_interrupt
1764 fast_interrupt_c_return:
1765 6: ld r7, VCPU_CTR(r9)
1766 lwz r8, VCPU_XER(r9)
1772 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1773 ld r5, KVM_VRMA_SLB_V(r5)
1776 /* If this is for emulated MMIO, load the instruction word */
1777 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1779 /* Set guest mode to 'jump over instruction' so if lwz faults
1780 * we'll just continue at the next IP. */
1781 li r0, KVM_GUEST_MODE_SKIP
1782 stb r0, HSTATE_IN_GUEST(r13)
1784 /* Do the access with MSR:DR enabled */
1786 ori r4, r3, MSR_DR /* Enable paging for data */
1791 /* Store the result */
1792 stw r8, VCPU_LAST_INST(r9)
1794 /* Unset guest mode. */
1795 li r0, KVM_GUEST_MODE_HOST_HV
1796 stb r0, HSTATE_IN_GUEST(r13)
1800 * Similarly for an HISI, reflect it to the guest as an ISI unless
1801 * it is an HPTE not found fault for a page that we have paged out.
1804 andis. r0, r11, SRR1_ISI_NOPT@h
1806 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1809 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1810 bne 1f /* if no SLB entry found */
1812 /* Search the hash table. */
1813 mr r3, r9 /* vcpu pointer */
1816 li r7, 0 /* instruction fault */
1817 bl kvmppc_hpte_hv_fault
1818 ld r9, HSTATE_KVM_VCPU(r13)
1820 ld r11, VCPU_MSR(r9)
1821 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1822 cmpdi r3, 0 /* retry the instruction */
1823 beq fast_interrupt_c_return
1824 cmpdi r3, -1 /* handle in kernel mode */
1827 /* Synthesize an ISI for the guest */
1829 1: mtspr SPRN_SRR0, r10
1830 mtspr SPRN_SRR1, r11
1831 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1832 bl kvmppc_msr_interrupt
1833 b fast_interrupt_c_return
1835 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1836 ld r5, KVM_VRMA_SLB_V(r6)
1840 * Try to handle an hcall in real mode.
1841 * Returns to the guest if we handle it, or continues on up to
1842 * the kernel if we can't (i.e. if we don't have a handler for
1843 * it, or if the handler returns H_TOO_HARD).
1845 * r5 - r8 contain hcall args,
1846 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
1848 hcall_try_real_mode:
1849 ld r3,VCPU_GPR(R3)(r9)
1851 /* sc 1 from userspace - reflect to guest syscall */
1852 bne sc_1_fast_return
1854 cmpldi r3,hcall_real_table_end - hcall_real_table
1856 /* See if this hcall is enabled for in-kernel handling */
1858 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1859 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1861 ld r0, KVM_ENABLED_HCALLS(r4)
1862 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1866 /* Get pointer to handler, if any, and call it */
1867 LOAD_REG_ADDR(r4, hcall_real_table)
1873 mr r3,r9 /* get vcpu pointer */
1874 ld r4,VCPU_GPR(R4)(r9)
1877 beq hcall_real_fallback
1878 ld r4,HSTATE_KVM_VCPU(r13)
1879 std r3,VCPU_GPR(R3)(r4)
1887 li r10, BOOK3S_INTERRUPT_SYSCALL
1888 bl kvmppc_msr_interrupt
1892 /* We've attempted a real mode hcall, but it's punted it back
1893 * to userspace. We need to restore some clobbered volatiles
1894 * before resuming the pass-it-to-qemu path */
1895 hcall_real_fallback:
1896 li r12,BOOK3S_INTERRUPT_SYSCALL
1897 ld r9, HSTATE_KVM_VCPU(r13)
1901 .globl hcall_real_table
1903 .long 0 /* 0 - unused */
1904 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1905 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1906 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1907 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
1908 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
1909 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1910 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1911 .long DOTSYM(kvmppc_h_put_tce) - hcall_real_table
1912 .long 0 /* 0x24 - H_SET_SPRG0 */
1913 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1928 #ifdef CONFIG_KVM_XICS
1929 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
1930 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
1931 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
1932 .long 0 /* 0x70 - H_IPOLL */
1933 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
1935 .long 0 /* 0x64 - H_EOI */
1936 .long 0 /* 0x68 - H_CPPR */
1937 .long 0 /* 0x6c - H_IPI */
1938 .long 0 /* 0x70 - H_IPOLL */
1939 .long 0 /* 0x74 - H_XIRR */
1967 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
1968 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
1984 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
1988 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2103 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2104 .globl hcall_real_table_end
2105 hcall_real_table_end:
2107 _GLOBAL(kvmppc_h_set_xdabr)
2108 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2110 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2113 6: li r3, H_PARAMETER
2116 _GLOBAL(kvmppc_h_set_dabr)
2117 li r5, DABRX_USER | DABRX_KERNEL
2121 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2122 std r4,VCPU_DABR(r3)
2123 stw r5, VCPU_DABRX(r3)
2124 mtspr SPRN_DABRX, r5
2125 /* Work around P7 bug where DABR can get corrupted on mtspr */
2126 1: mtspr SPRN_DABR,r4
2134 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2135 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2136 rlwimi r5, r4, 1, DAWRX_WT
2138 std r4, VCPU_DAWR(r3)
2139 std r5, VCPU_DAWRX(r3)
2141 mtspr SPRN_DAWRX, r5
2145 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2147 std r11,VCPU_MSR(r3)
2149 stb r0,VCPU_CEDED(r3)
2150 sync /* order setting ceded vs. testing prodded */
2151 lbz r5,VCPU_PRODDED(r3)
2153 bne kvm_cede_prodded
2154 li r12,0 /* set trap to 0 to say hcall is handled */
2155 stw r12,VCPU_TRAP(r3)
2157 std r0,VCPU_GPR(R3)(r3)
2160 * Set our bit in the bitmask of napping threads unless all the
2161 * other threads are already napping, in which case we send this
2164 ld r5,HSTATE_KVM_VCORE(r13)
2165 lbz r6,HSTATE_PTID(r13)
2166 lwz r8,VCORE_ENTRY_EXIT(r5)
2170 addi r6,r5,VCORE_NAPPING_THREADS
2177 /* order napping_threads update vs testing entry_exit_map */
2180 stb r0,HSTATE_NAPPING(r13)
2181 lwz r7,VCORE_ENTRY_EXIT(r5)
2183 bge 33f /* another thread already exiting */
2186 * Although not specifically required by the architecture, POWER7
2187 * preserves the following registers in nap mode, even if an SMT mode
2188 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2189 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2191 /* Save non-volatile GPRs */
2192 std r14, VCPU_GPR(R14)(r3)
2193 std r15, VCPU_GPR(R15)(r3)
2194 std r16, VCPU_GPR(R16)(r3)
2195 std r17, VCPU_GPR(R17)(r3)
2196 std r18, VCPU_GPR(R18)(r3)
2197 std r19, VCPU_GPR(R19)(r3)
2198 std r20, VCPU_GPR(R20)(r3)
2199 std r21, VCPU_GPR(R21)(r3)
2200 std r22, VCPU_GPR(R22)(r3)
2201 std r23, VCPU_GPR(R23)(r3)
2202 std r24, VCPU_GPR(R24)(r3)
2203 std r25, VCPU_GPR(R25)(r3)
2204 std r26, VCPU_GPR(R26)(r3)
2205 std r27, VCPU_GPR(R27)(r3)
2206 std r28, VCPU_GPR(R28)(r3)
2207 std r29, VCPU_GPR(R29)(r3)
2208 std r30, VCPU_GPR(R30)(r3)
2209 std r31, VCPU_GPR(R31)(r3)
2215 * Set DEC to the smaller of DEC and HDEC, so that we wake
2216 * no later than the end of our timeslice (HDEC interrupts
2217 * don't wake us from nap).
2226 /* save expiry time of guest decrementer */
2229 ld r4, HSTATE_KVM_VCPU(r13)
2230 ld r5, HSTATE_KVM_VCORE(r13)
2231 ld r6, VCORE_TB_OFFSET(r5)
2232 subf r3, r6, r3 /* convert to host TB value */
2233 std r3, VCPU_DEC_EXPIRES(r4)
2235 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2236 ld r4, HSTATE_KVM_VCPU(r13)
2237 addi r3, r4, VCPU_TB_CEDE
2238 bl kvmhv_accumulate_time
2241 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2244 * Take a nap until a decrementer or external or doobell interrupt
2245 * occurs, with PECE1 and PECE0 set in LPCR.
2246 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2247 * Also clear the runlatch bit before napping.
2250 mfspr r0, SPRN_CTRLF
2252 mtspr SPRN_CTRLT, r0
2255 stb r0,HSTATE_HWTHREAD_REQ(r13)
2257 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2259 ori r5, r5, LPCR_PECEDH
2260 rlwimi r5, r3, 0, LPCR_PECEDP
2261 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2265 std r0, HSTATE_SCRATCH0(r13)
2267 ld r0, HSTATE_SCRATCH0(r13)
2279 /* get vcpu pointer */
2280 ld r4, HSTATE_KVM_VCPU(r13)
2282 /* Woken by external or decrementer interrupt */
2283 ld r1, HSTATE_HOST_R1(r13)
2285 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2286 addi r3, r4, VCPU_TB_RMINTR
2287 bl kvmhv_accumulate_time
2290 /* load up FP state */
2293 /* Restore guest decrementer */
2294 ld r3, VCPU_DEC_EXPIRES(r4)
2295 ld r5, HSTATE_KVM_VCORE(r13)
2296 ld r6, VCORE_TB_OFFSET(r5)
2297 add r3, r3, r6 /* convert host TB to guest TB value */
2303 ld r14, VCPU_GPR(R14)(r4)
2304 ld r15, VCPU_GPR(R15)(r4)
2305 ld r16, VCPU_GPR(R16)(r4)
2306 ld r17, VCPU_GPR(R17)(r4)
2307 ld r18, VCPU_GPR(R18)(r4)
2308 ld r19, VCPU_GPR(R19)(r4)
2309 ld r20, VCPU_GPR(R20)(r4)
2310 ld r21, VCPU_GPR(R21)(r4)
2311 ld r22, VCPU_GPR(R22)(r4)
2312 ld r23, VCPU_GPR(R23)(r4)
2313 ld r24, VCPU_GPR(R24)(r4)
2314 ld r25, VCPU_GPR(R25)(r4)
2315 ld r26, VCPU_GPR(R26)(r4)
2316 ld r27, VCPU_GPR(R27)(r4)
2317 ld r28, VCPU_GPR(R28)(r4)
2318 ld r29, VCPU_GPR(R29)(r4)
2319 ld r30, VCPU_GPR(R30)(r4)
2320 ld r31, VCPU_GPR(R31)(r4)
2322 /* Check the wake reason in SRR1 to see why we got here */
2323 bl kvmppc_check_wake_reason
2325 /* clear our bit in vcore->napping_threads */
2326 34: ld r5,HSTATE_KVM_VCORE(r13)
2327 lbz r7,HSTATE_PTID(r13)
2330 addi r6,r5,VCORE_NAPPING_THREADS
2336 stb r0,HSTATE_NAPPING(r13)
2338 /* See if the wake reason means we need to exit */
2339 stw r12, VCPU_TRAP(r4)
2344 /* see if any other thread is already exiting */
2345 lwz r0,VCORE_ENTRY_EXIT(r5)
2349 b kvmppc_cede_reentry /* if not go back to guest */
2351 /* cede when already previously prodded case */
2354 stb r0,VCPU_PRODDED(r3)
2355 sync /* order testing prodded vs. clearing ceded */
2356 stb r0,VCPU_CEDED(r3)
2360 /* we've ceded but we want to give control to the host */
2362 ld r9, HSTATE_KVM_VCPU(r13)
2365 /* Try to handle a machine check in real mode */
2366 machine_check_realmode:
2367 mr r3, r9 /* get vcpu pointer */
2368 bl kvmppc_realmode_machine_check
2370 cmpdi r3, 0 /* Did we handle MCE ? */
2371 ld r9, HSTATE_KVM_VCPU(r13)
2372 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2374 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through
2375 * machine check interrupt (set HSRR0 to 0x200). And for handled
2376 * errors (no-fatal), just go back to guest execution with current
2377 * HSRR0 instead of exiting guest. This new approach will inject
2378 * machine check to guest for fatal error causing guest to crash.
2380 * The old code used to return to host for unhandled errors which
2381 * was causing guest to hang with soft lockups inside guest and
2382 * makes it difficult to recover guest instance.
2385 ld r11, VCPU_MSR(r9)
2386 bne 2f /* Continue guest execution. */
2387 /* If not, deliver a machine check. SRR0/1 are already set */
2388 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2389 ld r11, VCPU_MSR(r9)
2390 bl kvmppc_msr_interrupt
2391 2: b fast_interrupt_c_return
2394 * Check the reason we woke from nap, and take appropriate action.
2396 * 0 if nothing needs to be done
2397 * 1 if something happened that needs to be handled by the host
2398 * -1 if there was a guest wakeup (IPI or msgsnd)
2400 * Also sets r12 to the interrupt vector for any interrupt that needs
2401 * to be handled now by the host (0x500 for external interrupt), or zero.
2402 * Modifies r0, r6, r7, r8.
2404 kvmppc_check_wake_reason:
2407 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2409 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2410 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2411 cmpwi r6, 8 /* was it an external interrupt? */
2412 li r12, BOOK3S_INTERRUPT_EXTERNAL
2413 beq kvmppc_read_intr /* if so, see what it was */
2416 cmpwi r6, 6 /* was it the decrementer? */
2419 cmpwi r6, 5 /* privileged doorbell? */
2421 cmpwi r6, 3 /* hypervisor doorbell? */
2423 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2424 li r3, 1 /* anything else, return 1 */
2427 /* hypervisor doorbell */
2428 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2429 /* see if it's a host IPI */
2431 lbz r0, HSTATE_HOST_IPI(r13)
2434 /* if not, clear it and return -1 */
2435 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2441 * Determine what sort of external interrupt is pending (if any).
2443 * 0 if no interrupt is pending
2444 * 1 if an interrupt is pending that needs to be handled by the host
2445 * -1 if there was a guest wakeup IPI (which has now been cleared)
2446 * Modifies r0, r6, r7, r8, returns value in r3.
2449 /* see if a host IPI is pending */
2451 lbz r0, HSTATE_HOST_IPI(r13)
2455 /* Now read the interrupt from the ICP */
2456 ld r6, HSTATE_XICS_PHYS(r13)
2462 * Save XIRR for later. Since we get in in reverse endian on LE
2463 * systems, save it byte reversed and fetch it back in host endian.
2465 li r3, HSTATE_SAVED_XIRR
2467 #ifdef __LITTLE_ENDIAN__
2468 lwz r3, HSTATE_SAVED_XIRR(r13)
2472 rlwinm. r3, r3, 0, 0xffffff
2474 beq 1f /* if nothing pending in the ICP */
2476 /* We found something in the ICP...
2478 * If it's not an IPI, stash it in the PACA and return to
2479 * the host, we don't (yet) handle directing real external
2480 * interrupts directly to the guest
2482 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2485 /* It's an IPI, clear the MFRR and EOI it */
2488 stbcix r3, r6, r8 /* clear the IPI */
2489 stwcix r0, r6, r7 /* EOI it */
2492 /* We need to re-check host IPI now in case it got set in the
2493 * meantime. If it's clear, we bounce the interrupt to the
2496 lbz r0, HSTATE_HOST_IPI(r13)
2500 /* OK, it's an IPI for us */
2505 42: /* It's not an IPI and it's for the host. We saved a copy of XIRR in
2506 * the PACA earlier, it will be picked up by the host ICP driver
2511 43: /* We raced with the host, we need to resend that IPI, bummer */
2513 stbcix r0, r6, r8 /* set the IPI */
2519 * Save away FP, VMX and VSX registers.
2521 * N.B. r30 and r31 are volatile across this function,
2522 * thus it is not callable from C.
2529 #ifdef CONFIG_ALTIVEC
2531 oris r8,r8,MSR_VEC@h
2532 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2536 oris r8,r8,MSR_VSX@h
2537 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2540 addi r3,r3,VCPU_FPRS
2542 #ifdef CONFIG_ALTIVEC
2544 addi r3,r31,VCPU_VRS
2546 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2548 mfspr r6,SPRN_VRSAVE
2549 stw r6,VCPU_VRSAVE(r31)
2554 * Load up FP, VMX and VSX registers
2556 * N.B. r30 and r31 are volatile across this function,
2557 * thus it is not callable from C.
2564 #ifdef CONFIG_ALTIVEC
2566 oris r8,r8,MSR_VEC@h
2567 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2571 oris r8,r8,MSR_VSX@h
2572 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2575 addi r3,r4,VCPU_FPRS
2577 #ifdef CONFIG_ALTIVEC
2579 addi r3,r31,VCPU_VRS
2581 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2583 lwz r7,VCPU_VRSAVE(r31)
2584 mtspr SPRN_VRSAVE,r7
2590 * We come here if we get any exception or interrupt while we are
2591 * executing host real mode code while in guest MMU context.
2592 * For now just spin, but we should do something better.
2594 kvmppc_bad_host_intr:
2598 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2599 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2600 * r11 has the guest MSR value (in/out)
2601 * r9 has a vcpu pointer (in)
2602 * r0 is used as a scratch register
2604 kvmppc_msr_interrupt:
2605 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2606 cmpwi r0, 2 /* Check if we are in transactional state.. */
2607 ld r11, VCPU_INTR_MSR(r9)
2609 /* ... if transactional, change to suspended */
2611 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2615 * This works around a hardware bug on POWER8E processors, where
2616 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2617 * performance monitor interrupt. Instead, when we need to have
2618 * an interrupt pending, we have to arrange for a counter to overflow.
2622 mtspr SPRN_MMCR2, r3
2623 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2624 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2625 mtspr SPRN_MMCR0, r3
2632 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2634 * Start timing an activity
2635 * r3 = pointer to time accumulation struct, r4 = vcpu
2638 ld r5, HSTATE_KVM_VCORE(r13)
2639 lbz r6, VCORE_IN_GUEST(r5)
2641 beq 5f /* if in guest, need to */
2642 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2645 std r3, VCPU_CUR_ACTIVITY(r4)
2646 std r5, VCPU_ACTIVITY_START(r4)
2650 * Accumulate time to one activity and start another.
2651 * r3 = pointer to new time accumulation struct, r4 = vcpu
2653 kvmhv_accumulate_time:
2654 ld r5, HSTATE_KVM_VCORE(r13)
2655 lbz r8, VCORE_IN_GUEST(r5)
2657 beq 4f /* if in guest, need to */
2658 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2659 4: ld r5, VCPU_CUR_ACTIVITY(r4)
2660 ld r6, VCPU_ACTIVITY_START(r4)
2661 std r3, VCPU_CUR_ACTIVITY(r4)
2664 std r7, VCPU_ACTIVITY_START(r4)
2668 ld r8, TAS_SEQCOUNT(r5)
2671 std r8, TAS_SEQCOUNT(r5)
2673 ld r7, TAS_TOTAL(r5)
2675 std r7, TAS_TOTAL(r5)
2681 3: std r3, TAS_MIN(r5)
2687 std r8, TAS_SEQCOUNT(r5)