2 * native hashtable management.
4 * SMP scalability work:
5 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
18 #include <linux/threads.h>
19 #include <linux/smp.h>
21 #include <asm/machdep.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
25 #include <asm/tlbflush.h>
27 #include <asm/cputable.h>
29 #include <asm/kexec.h>
30 #include <asm/ppc-opcode.h>
32 #include <misc/cxl-base.h>
35 #define DBG_LOW(fmt...) udbg_printf(fmt)
37 #define DBG_LOW(fmt...)
41 #define HPTE_LOCK_BIT 3
43 #define HPTE_LOCK_BIT (56+3)
46 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
48 static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
55 * We need 14 to 65 bits of va for a tlibe of 4K page
56 * With vpn we ignore the lower VPN_SHIFT bits already.
57 * And top two bits are already ignored because we can
58 * only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT
61 va = vpn << VPN_SHIFT;
63 * clear top 16 bits of 64bit va, non SLS segment
64 * Older versions of the architecture (2.02 and earler) require the
65 * masking of the top 16 bits.
67 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
68 va &= ~(0xffffULL << 48);
72 /* clear out bits after (52) [0....52.....63] */
73 va &= ~((1ul << (64 - 52)) - 1);
75 sllp = get_sllp_encoding(apsize);
77 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
78 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
82 /* We need 14 to 14 + i bits of va */
83 penc = mmu_psize_defs[psize].penc[apsize];
84 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
89 * We don't need all the bits, but rest of the bits
90 * must be ignored by the processor.
91 * vpn cover upto 65 bits of va. (0...65) and we need
94 va |= (vpn & 0xfe); /* AVAL */
96 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
97 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
103 static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
109 /* VPN_SHIFT can be atmost 12 */
110 va = vpn << VPN_SHIFT;
112 * clear top 16 bits of 64 bit va, non SLS segment
113 * Older versions of the architecture (2.02 and earler) require the
114 * masking of the top 16 bits.
116 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
117 va &= ~(0xffffULL << 48);
121 /* clear out bits after(52) [0....52.....63] */
122 va &= ~((1ul << (64 - 52)) - 1);
124 sllp = get_sllp_encoding(apsize);
126 asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
127 : : "r"(va) : "memory");
130 /* We need 14 to 14 + i bits of va */
131 penc = mmu_psize_defs[psize].penc[apsize];
132 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
137 * We don't need all the bits, but rest of the bits
138 * must be ignored by the processor.
139 * vpn cover upto 65 bits of va. (0...65) and we need
144 asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
145 : : "r"(va) : "memory");
151 static inline void tlbie(unsigned long vpn, int psize, int apsize,
152 int ssize, int local)
154 unsigned int use_local;
155 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
157 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use();
160 use_local = mmu_psize_defs[psize].tlbiel;
161 if (lock_tlbie && !use_local)
162 raw_spin_lock(&native_tlbie_lock);
163 asm volatile("ptesync": : :"memory");
165 __tlbiel(vpn, psize, apsize, ssize);
166 asm volatile("ptesync": : :"memory");
168 __tlbie(vpn, psize, apsize, ssize);
169 asm volatile("eieio; tlbsync; ptesync": : :"memory");
171 if (lock_tlbie && !use_local)
172 raw_spin_unlock(&native_tlbie_lock);
175 static inline void native_lock_hpte(struct hash_pte *hptep)
177 unsigned long *word = (unsigned long *)&hptep->v;
180 if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
182 while(test_bit(HPTE_LOCK_BIT, word))
187 static inline void native_unlock_hpte(struct hash_pte *hptep)
189 unsigned long *word = (unsigned long *)&hptep->v;
191 clear_bit_unlock(HPTE_LOCK_BIT, word);
194 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
195 unsigned long pa, unsigned long rflags,
196 unsigned long vflags, int psize, int apsize, int ssize)
198 struct hash_pte *hptep = htab_address + hpte_group;
199 unsigned long hpte_v, hpte_r;
202 if (!(vflags & HPTE_V_BOLTED)) {
203 DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
204 " rflags=%lx, vflags=%lx, psize=%d)\n",
205 hpte_group, vpn, pa, rflags, vflags, psize);
208 for (i = 0; i < HPTES_PER_GROUP; i++) {
209 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) {
210 /* retry with lock held */
211 native_lock_hpte(hptep);
212 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID))
214 native_unlock_hpte(hptep);
220 if (i == HPTES_PER_GROUP)
223 hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
224 hpte_r = hpte_encode_r(pa, psize, apsize, ssize) | rflags;
226 if (!(vflags & HPTE_V_BOLTED)) {
227 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
231 hptep->r = cpu_to_be64(hpte_r);
232 /* Guarantee the second dword is visible before the valid bit */
235 * Now set the first dword including the valid bit
236 * NOTE: this also unlocks the hpte
238 hptep->v = cpu_to_be64(hpte_v);
240 __asm__ __volatile__ ("ptesync" : : : "memory");
242 return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
245 static long native_hpte_remove(unsigned long hpte_group)
247 struct hash_pte *hptep;
250 unsigned long hpte_v;
252 DBG_LOW(" remove(group=%lx)\n", hpte_group);
254 /* pick a random entry to start at */
255 slot_offset = mftb() & 0x7;
257 for (i = 0; i < HPTES_PER_GROUP; i++) {
258 hptep = htab_address + hpte_group + slot_offset;
259 hpte_v = be64_to_cpu(hptep->v);
261 if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
262 /* retry with lock held */
263 native_lock_hpte(hptep);
264 hpte_v = be64_to_cpu(hptep->v);
265 if ((hpte_v & HPTE_V_VALID)
266 && !(hpte_v & HPTE_V_BOLTED))
268 native_unlock_hpte(hptep);
275 if (i == HPTES_PER_GROUP)
278 /* Invalidate the hpte. NOTE: this also unlocks it */
284 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
285 unsigned long vpn, int bpsize,
286 int apsize, int ssize, unsigned long flags)
288 struct hash_pte *hptep = htab_address + slot;
289 unsigned long hpte_v, want_v;
290 int ret = 0, local = 0;
292 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
294 DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
295 vpn, want_v & HPTE_V_AVPN, slot, newpp);
297 hpte_v = be64_to_cpu(hptep->v);
299 * We need to invalidate the TLB always because hpte_remove doesn't do
300 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
301 * random entry from it. When we do that we don't invalidate the TLB
302 * (hpte_remove) because we assume the old translation is still
303 * technically "valid".
305 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
306 DBG_LOW(" -> miss\n");
309 native_lock_hpte(hptep);
310 /* recheck with locks held */
311 hpte_v = be64_to_cpu(hptep->v);
312 if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) ||
313 !(hpte_v & HPTE_V_VALID))) {
316 DBG_LOW(" -> hit\n");
317 /* Update the HPTE */
318 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
319 ~(HPTE_R_PPP | HPTE_R_N)) |
320 (newpp & (HPTE_R_PPP | HPTE_R_N |
323 native_unlock_hpte(hptep);
326 if (flags & HPTE_LOCAL_UPDATE)
329 * Ensure it is out of the tlb too if it is not a nohpte fault
331 if (!(flags & HPTE_NOHPTE_UPDATE))
332 tlbie(vpn, bpsize, apsize, ssize, local);
337 static long native_hpte_find(unsigned long vpn, int psize, int ssize)
339 struct hash_pte *hptep;
343 unsigned long want_v, hpte_v;
345 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
346 want_v = hpte_encode_avpn(vpn, psize, ssize);
348 /* Bolted mappings are only ever in the primary group */
349 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
350 for (i = 0; i < HPTES_PER_GROUP; i++) {
351 hptep = htab_address + slot;
352 hpte_v = be64_to_cpu(hptep->v);
354 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
364 * Update the page protection bits. Intended to be used to create
365 * guard pages for kernel data structures on pages which are bolted
366 * in the HPT. Assumes pages being operated on will not be stolen.
368 * No need to lock here because we should be the only user.
370 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
371 int psize, int ssize)
376 struct hash_pte *hptep;
378 vsid = get_kernel_vsid(ea, ssize);
379 vpn = hpt_vpn(ea, vsid, ssize);
381 slot = native_hpte_find(vpn, psize, ssize);
383 panic("could not find page to bolt\n");
384 hptep = htab_address + slot;
386 /* Update the HPTE */
387 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
388 ~(HPTE_R_PPP | HPTE_R_N)) |
389 (newpp & (HPTE_R_PPP | HPTE_R_N)));
391 * Ensure it is out of the tlb too. Bolted entries base and
392 * actual page size will be same.
394 tlbie(vpn, psize, psize, ssize, 0);
397 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
398 int bpsize, int apsize, int ssize, int local)
400 struct hash_pte *hptep = htab_address + slot;
401 unsigned long hpte_v;
402 unsigned long want_v;
405 local_irq_save(flags);
407 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
409 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
410 native_lock_hpte(hptep);
411 hpte_v = be64_to_cpu(hptep->v);
414 * We need to invalidate the TLB always because hpte_remove doesn't do
415 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
416 * random entry from it. When we do that we don't invalidate the TLB
417 * (hpte_remove) because we assume the old translation is still
418 * technically "valid".
420 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
421 native_unlock_hpte(hptep);
423 /* Invalidate the hpte. NOTE: this also unlocks it */
426 /* Invalidate the TLB */
427 tlbie(vpn, bpsize, apsize, ssize, local);
429 local_irq_restore(flags);
432 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
433 static void native_hugepage_invalidate(unsigned long vsid,
435 unsigned char *hpte_slot_array,
436 int psize, int ssize, int local)
439 struct hash_pte *hptep;
440 int actual_psize = MMU_PAGE_16M;
441 unsigned int max_hpte_count, valid;
442 unsigned long flags, s_addr = addr;
443 unsigned long hpte_v, want_v, shift;
444 unsigned long hidx, vpn = 0, hash, slot;
446 shift = mmu_psize_defs[psize].shift;
447 max_hpte_count = 1U << (PMD_SHIFT - shift);
449 local_irq_save(flags);
450 for (i = 0; i < max_hpte_count; i++) {
451 valid = hpte_valid(hpte_slot_array, i);
454 hidx = hpte_hash_index(hpte_slot_array, i);
457 addr = s_addr + (i * (1ul << shift));
458 vpn = hpt_vpn(addr, vsid, ssize);
459 hash = hpt_hash(vpn, shift, ssize);
460 if (hidx & _PTEIDX_SECONDARY)
463 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
464 slot += hidx & _PTEIDX_GROUP_IX;
466 hptep = htab_address + slot;
467 want_v = hpte_encode_avpn(vpn, psize, ssize);
468 native_lock_hpte(hptep);
469 hpte_v = be64_to_cpu(hptep->v);
471 /* Even if we miss, we need to invalidate the TLB */
472 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
473 native_unlock_hpte(hptep);
475 /* Invalidate the hpte. NOTE: this also unlocks it */
478 * We need to do tlb invalidate for all the address, tlbie
479 * instruction compares entry_VA in tlb with the VA specified
482 tlbie(vpn, psize, actual_psize, ssize, local);
484 local_irq_restore(flags);
487 static void native_hugepage_invalidate(unsigned long vsid,
489 unsigned char *hpte_slot_array,
490 int psize, int ssize, int local)
492 WARN(1, "%s called without THP support\n", __func__);
496 static inline int __hpte_actual_psize(unsigned int lp, int psize)
501 /* start from 1 ignoring MMU_PAGE_4K */
502 for (i = 1; i < MMU_PAGE_COUNT; i++) {
505 if (mmu_psize_defs[psize].penc[i] == -1)
508 * encoding bits per actual page size
509 * PTE LP actual page size
516 shift = mmu_psize_defs[i].shift - LP_SHIFT;
519 mask = (1 << shift) - 1;
520 if ((lp & mask) == mmu_psize_defs[psize].penc[i])
526 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
527 int *psize, int *apsize, int *ssize, unsigned long *vpn)
529 unsigned long avpn, pteg, vpi;
530 unsigned long hpte_v = be64_to_cpu(hpte->v);
531 unsigned long hpte_r = be64_to_cpu(hpte->r);
532 unsigned long vsid, seg_off;
533 int size, a_size, shift;
534 /* Look at the 8 bit LP value */
535 unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
537 if (!(hpte_v & HPTE_V_LARGE)) {
539 a_size = MMU_PAGE_4K;
541 for (size = 0; size < MMU_PAGE_COUNT; size++) {
543 /* valid entries have a shift value */
544 if (!mmu_psize_defs[size].shift)
547 a_size = __hpte_actual_psize(lp, size);
552 /* This works for all page sizes, and for 256M and 1T segments */
553 if (cpu_has_feature(CPU_FTR_ARCH_300))
554 *ssize = hpte_r >> HPTE_R_3_0_SSIZE_SHIFT;
556 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
558 shift = mmu_psize_defs[size].shift;
560 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
561 pteg = slot / HPTES_PER_GROUP;
562 if (hpte_v & HPTE_V_SECONDARY)
566 case MMU_SEGSIZE_256M:
567 /* We only have 28 - 23 bits of seg_off in avpn */
568 seg_off = (avpn & 0x1f) << 23;
570 /* We can find more bits from the pteg value */
572 vpi = (vsid ^ pteg) & htab_hash_mask;
573 seg_off |= vpi << shift;
575 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
578 /* We only have 40 - 23 bits of seg_off in avpn */
579 seg_off = (avpn & 0x1ffff) << 23;
582 vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
583 seg_off |= vpi << shift;
585 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
595 * clear all mappings on kexec. All cpus are in real mode (or they will
596 * be when they isi), and we are the only one left. We rely on our kernel
597 * mapping being 0xC0's and the hardware ignoring those two real bits.
599 * This must be called with interrupts disabled.
601 * Taking the native_tlbie_lock is unsafe here due to the possibility of
602 * lockdep being on. On pre POWER5 hardware, not taking the lock could
603 * cause deadlock. POWER5 and newer not taking the lock is fine. This only
604 * gets called during boot before secondary CPUs have come up and during
605 * crashdump and all bets are off anyway.
607 * TODO: add batching support when enabled. remember, no dynamic memory here,
608 * although there is the control page available...
610 static void native_hpte_clear(void)
612 unsigned long vpn = 0;
613 unsigned long slot, slots;
614 struct hash_pte *hptep = htab_address;
615 unsigned long hpte_v;
616 unsigned long pteg_count;
617 int psize, apsize, ssize;
619 pteg_count = htab_hash_mask + 1;
621 slots = pteg_count * HPTES_PER_GROUP;
623 for (slot = 0; slot < slots; slot++, hptep++) {
625 * we could lock the pte here, but we are the only cpu
626 * running, right? and for crash dump, we probably
627 * don't want to wait for a maybe bad cpu.
629 hpte_v = be64_to_cpu(hptep->v);
632 * Call __tlbie() here rather than tlbie() since we can't take the
635 if (hpte_v & HPTE_V_VALID) {
636 hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
638 __tlbie(vpn, psize, apsize, ssize);
642 asm volatile("eieio; tlbsync; ptesync":::"memory");
646 * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
647 * the lock all the time
649 static void native_flush_hash_range(unsigned long number, int local)
652 unsigned long hash, index, hidx, shift, slot;
653 struct hash_pte *hptep;
654 unsigned long hpte_v;
655 unsigned long want_v;
658 struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);
659 unsigned long psize = batch->psize;
660 int ssize = batch->ssize;
663 local_irq_save(flags);
665 for (i = 0; i < number; i++) {
669 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
670 hash = hpt_hash(vpn, shift, ssize);
671 hidx = __rpte_to_hidx(pte, index);
672 if (hidx & _PTEIDX_SECONDARY)
674 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
675 slot += hidx & _PTEIDX_GROUP_IX;
676 hptep = htab_address + slot;
677 want_v = hpte_encode_avpn(vpn, psize, ssize);
678 native_lock_hpte(hptep);
679 hpte_v = be64_to_cpu(hptep->v);
680 if (!HPTE_V_COMPARE(hpte_v, want_v) ||
681 !(hpte_v & HPTE_V_VALID))
682 native_unlock_hpte(hptep);
685 } pte_iterate_hashed_end();
688 if (mmu_has_feature(MMU_FTR_TLBIEL) &&
689 mmu_psize_defs[psize].tlbiel && local) {
690 asm volatile("ptesync":::"memory");
691 for (i = 0; i < number; i++) {
695 pte_iterate_hashed_subpages(pte, psize,
697 __tlbiel(vpn, psize, psize, ssize);
698 } pte_iterate_hashed_end();
700 asm volatile("ptesync":::"memory");
702 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
705 raw_spin_lock(&native_tlbie_lock);
707 asm volatile("ptesync":::"memory");
708 for (i = 0; i < number; i++) {
712 pte_iterate_hashed_subpages(pte, psize,
714 __tlbie(vpn, psize, psize, ssize);
715 } pte_iterate_hashed_end();
717 asm volatile("eieio; tlbsync; ptesync":::"memory");
720 raw_spin_unlock(&native_tlbie_lock);
723 local_irq_restore(flags);
726 static int native_register_proc_table(unsigned long base, unsigned long page_size,
727 unsigned long table_size)
729 unsigned long patb1 = base << 25; /* VSID */
731 patb1 |= (page_size << 5); /* sllp */
734 partition_tb->patb1 = cpu_to_be64(patb1);
738 void __init hpte_init_native(void)
740 mmu_hash_ops.hpte_invalidate = native_hpte_invalidate;
741 mmu_hash_ops.hpte_updatepp = native_hpte_updatepp;
742 mmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;
743 mmu_hash_ops.hpte_insert = native_hpte_insert;
744 mmu_hash_ops.hpte_remove = native_hpte_remove;
745 mmu_hash_ops.hpte_clear_all = native_hpte_clear;
746 mmu_hash_ops.flush_hash_range = native_flush_hash_range;
747 mmu_hash_ops.hugepage_invalidate = native_hugepage_invalidate;
749 if (cpu_has_feature(CPU_FTR_ARCH_300))
750 register_process_table = native_register_proc_table;