2 * Page table handling routines for radix page table.
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/sched/mm.h>
12 #include <linux/memblock.h>
13 #include <linux/of_fdt.h>
16 #include <asm/pgtable.h>
17 #include <asm/pgalloc.h>
19 #include <asm/machdep.h>
21 #include <asm/firmware.h>
22 #include <asm/powernv.h>
23 #include <asm/sections.h>
24 #include <asm/trace.h>
26 #include <trace/events/thp.h>
28 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
29 unsigned long table_size)
31 unsigned long patb1 = base | table_size | PATB_GR;
33 partition_tb->patb1 = cpu_to_be64(patb1);
37 static __ref void *early_alloc_pgtable(unsigned long size)
41 pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
47 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
49 unsigned int map_page_size)
56 * Make sure task size is correct as per the max adddr
58 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
59 if (slab_is_available()) {
60 pgdp = pgd_offset_k(ea);
61 pudp = pud_alloc(&init_mm, pgdp, ea);
64 if (map_page_size == PUD_SIZE) {
68 pmdp = pmd_alloc(&init_mm, pudp, ea);
71 if (map_page_size == PMD_SIZE) {
72 ptep = pmdp_ptep(pmdp);
75 ptep = pte_alloc_kernel(pmdp, ea);
79 pgdp = pgd_offset_k(ea);
80 if (pgd_none(*pgdp)) {
81 pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
83 pgd_populate(&init_mm, pgdp, pudp);
85 pudp = pud_offset(pgdp, ea);
86 if (map_page_size == PUD_SIZE) {
90 if (pud_none(*pudp)) {
91 pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
93 pud_populate(&init_mm, pudp, pmdp);
95 pmdp = pmd_offset(pudp, ea);
96 if (map_page_size == PMD_SIZE) {
97 ptep = pmdp_ptep(pmdp);
100 if (!pmd_present(*pmdp)) {
101 ptep = early_alloc_pgtable(PAGE_SIZE);
102 BUG_ON(ptep == NULL);
103 pmd_populate_kernel(&init_mm, pmdp, ptep);
105 ptep = pte_offset_kernel(pmdp, ea);
109 set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
114 #ifdef CONFIG_STRICT_KERNEL_RWX
115 void radix__change_memory_range(unsigned long start, unsigned long end,
124 start = ALIGN_DOWN(start, PAGE_SIZE);
125 end = PAGE_ALIGN(end); // aligns up
127 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
130 for (idx = start; idx < end; idx += PAGE_SIZE) {
131 pgdp = pgd_offset_k(idx);
132 pudp = pud_alloc(&init_mm, pgdp, idx);
135 if (pud_huge(*pudp)) {
136 ptep = (pte_t *)pudp;
139 pmdp = pmd_alloc(&init_mm, pudp, idx);
142 if (pmd_huge(*pmdp)) {
143 ptep = pmdp_ptep(pmdp);
146 ptep = pte_alloc_kernel(pmdp, idx);
150 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
153 radix__flush_tlb_kernel_range(start, end);
156 void radix__mark_rodata_ro(void)
158 unsigned long start, end;
160 start = (unsigned long)_stext;
161 end = (unsigned long)__init_begin;
163 radix__change_memory_range(start, end, _PAGE_WRITE);
166 void radix__mark_initmem_nx(void)
168 unsigned long start = (unsigned long)__init_begin;
169 unsigned long end = (unsigned long)__init_end;
171 radix__change_memory_range(start, end, _PAGE_EXEC);
173 #endif /* CONFIG_STRICT_KERNEL_RWX */
175 static inline void __meminit print_mapping(unsigned long start,
182 pr_info("Mapped range 0x%lx - 0x%lx with 0x%lx\n", start, end, size);
185 static int __meminit create_physical_mapping(unsigned long start,
188 unsigned long vaddr, addr, mapping_size = 0;
190 unsigned long max_mapping_size;
191 #ifdef CONFIG_STRICT_KERNEL_RWX
192 int split_text_mapping = 1;
194 int split_text_mapping = 0;
197 start = _ALIGN_UP(start, PAGE_SIZE);
198 for (addr = start; addr < end; addr += mapping_size) {
199 unsigned long gap, previous_size;
203 previous_size = mapping_size;
204 max_mapping_size = PUD_SIZE;
207 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
208 mmu_psize_defs[MMU_PAGE_1G].shift &&
209 PUD_SIZE <= max_mapping_size)
210 mapping_size = PUD_SIZE;
211 else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
212 mmu_psize_defs[MMU_PAGE_2M].shift)
213 mapping_size = PMD_SIZE;
215 mapping_size = PAGE_SIZE;
217 if (split_text_mapping && (mapping_size == PUD_SIZE) &&
218 (addr <= __pa_symbol(__init_begin)) &&
219 (addr + mapping_size) >= __pa_symbol(_stext)) {
220 max_mapping_size = PMD_SIZE;
224 if (split_text_mapping && (mapping_size == PMD_SIZE) &&
225 (addr <= __pa_symbol(__init_begin)) &&
226 (addr + mapping_size) >= __pa_symbol(_stext))
227 mapping_size = PAGE_SIZE;
229 if (mapping_size != previous_size) {
230 print_mapping(start, addr, previous_size);
234 vaddr = (unsigned long)__va(addr);
236 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
237 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size))
238 prot = PAGE_KERNEL_X;
242 rc = radix__map_kernel_page(vaddr, addr, prot, mapping_size);
247 print_mapping(start, addr, mapping_size);
251 static void __init radix_init_pgtable(void)
253 unsigned long rts_field;
254 struct memblock_region *reg;
256 /* We don't support slb for radix */
259 * Create the linear mapping, using standard page size for now
261 for_each_memblock(memory, reg)
262 WARN_ON(create_physical_mapping(reg->base,
263 reg->base + reg->size));
265 * Allocate Partition table and process table for the
268 BUILD_BUG_ON_MSG((PRTB_SIZE_SHIFT > 36), "Process table size too large.");
269 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
271 * Fill in the process table.
273 rts_field = radix__get_tree_size();
274 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
276 * Fill in the partition table. We are suppose to use effective address
277 * of process table here. But our linear mapping also enable us to use
278 * physical address here.
280 register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
281 pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
282 asm volatile("ptesync" : : : "memory");
283 asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
284 "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
285 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
286 trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
289 static void __init radix_init_partition_table(void)
291 unsigned long rts_field, dw0;
293 mmu_partition_table_init();
294 rts_field = radix__get_tree_size();
295 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
296 mmu_partition_table_set_entry(0, dw0, 0);
298 pr_info("Initializing Radix MMU\n");
299 pr_info("Partition table %p\n", partition_tb);
302 void __init radix_init_native(void)
304 register_process_table = native_register_process_table;
307 static int __init get_idx_from_shift(unsigned int shift)
328 static int __init radix_dt_scan_page_sizes(unsigned long node,
329 const char *uname, int depth,
336 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
338 /* We are scanning "cpu" nodes only */
339 if (type == NULL || strcmp(type, "cpu") != 0)
342 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
346 pr_info("Page sizes from device-tree:\n");
347 for (; size >= 4; size -= 4, ++prop) {
349 struct mmu_psize_def *def;
351 /* top 3 bit is AP encoding */
352 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
353 ap = be32_to_cpu(prop[0]) >> 29;
354 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
356 idx = get_idx_from_shift(shift);
360 def = &mmu_psize_defs[idx];
366 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
370 void __init radix__early_init_devtree(void)
375 * Try to find the available page sizes in the device-tree
377 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
378 if (rc != 0) /* Found */
381 * let's assume we have page 4k and 64k support
383 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
384 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
386 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
387 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
389 #ifdef CONFIG_SPARSEMEM_VMEMMAP
390 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
392 * map vmemmap using 2M if available
394 mmu_vmemmap_psize = MMU_PAGE_2M;
396 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
400 static void update_hid_for_radix(void)
403 unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
405 asm volatile("ptesync": : :"memory");
406 /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
407 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
408 : : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
409 /* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
410 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
411 : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
412 asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
413 trace_tlbie(0, 0, rb, 0, 2, 0, 1);
414 trace_tlbie(0, 0, rb, 0, 2, 1, 1);
419 hid0 = mfspr(SPRN_HID0);
420 hid0 |= HID0_POWER9_RADIX;
421 mtspr(SPRN_HID0, hid0);
422 asm volatile("isync": : :"memory");
424 /* Wait for it to happen */
425 while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
429 static void radix_init_amor(void)
432 * In HV mode, we init AMOR (Authority Mask Override Register) so that
433 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
434 * Register), enable key 0 and set it to 1.
436 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
438 mtspr(SPRN_AMOR, (3ul << 62));
441 static void radix_init_iamr(void)
446 * The IAMR should set to 0 on DD1.
448 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
454 * Radix always uses key0 of the IAMR to determine if an access is
455 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
458 mtspr(SPRN_IAMR, iamr);
461 void __init radix__early_init_mmu(void)
465 #ifdef CONFIG_PPC_64K_PAGES
466 /* PAGE_SIZE mappings */
467 mmu_virtual_psize = MMU_PAGE_64K;
469 mmu_virtual_psize = MMU_PAGE_4K;
472 #ifdef CONFIG_SPARSEMEM_VMEMMAP
473 /* vmemmap mapping */
474 mmu_vmemmap_psize = mmu_virtual_psize;
477 * initialize page table size
479 __pte_index_size = RADIX_PTE_INDEX_SIZE;
480 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
481 __pud_index_size = RADIX_PUD_INDEX_SIZE;
482 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
483 __pmd_cache_index = RADIX_PMD_INDEX_SIZE;
484 __pte_table_size = RADIX_PTE_TABLE_SIZE;
485 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
486 __pud_table_size = RADIX_PUD_TABLE_SIZE;
487 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
489 __pmd_val_bits = RADIX_PMD_VAL_BITS;
490 __pud_val_bits = RADIX_PUD_VAL_BITS;
491 __pgd_val_bits = RADIX_PGD_VAL_BITS;
493 __kernel_virt_start = RADIX_KERN_VIRT_START;
494 __kernel_virt_size = RADIX_KERN_VIRT_SIZE;
495 __vmalloc_start = RADIX_VMALLOC_START;
496 __vmalloc_end = RADIX_VMALLOC_END;
497 vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
498 ioremap_bot = IOREMAP_BASE;
501 pci_io_base = ISA_IO_BASE;
505 * For now radix also use the same frag size
507 __pte_frag_nr = H_PTE_FRAG_NR;
508 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
510 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
512 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
513 update_hid_for_radix();
514 lpcr = mfspr(SPRN_LPCR);
515 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
516 radix_init_partition_table();
519 radix_init_pseries();
522 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
525 radix_init_pgtable();
528 void radix__early_init_mmu_secondary(void)
532 * update partition table control register and UPRT
534 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
536 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
537 update_hid_for_radix();
539 lpcr = mfspr(SPRN_LPCR);
540 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
543 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
549 void radix__mmu_cleanup_all(void)
553 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
554 lpcr = mfspr(SPRN_LPCR);
555 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
557 powernv_set_nmmu_ptcr(0);
558 radix__flush_tlb_all();
562 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
563 phys_addr_t first_memblock_size)
565 /* We don't currently support the first MEMBLOCK not mapping 0
566 * physical on those processors
568 BUG_ON(first_memblock_base != 0);
570 * We limit the allocation that depend on ppc64_rma_size
571 * to first_memblock_size. We also clamp it to 1GB to
572 * avoid some funky things such as RTAS bugs.
574 * On radix config we really don't have a limitation
575 * on real mode access. But keeping it as above works
578 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
580 * Finally limit subsequent allocations. We really don't want
581 * to limit the memblock allocations to rma_size. FIXME!! should
582 * we even limit at all ?
584 memblock_set_current_limit(first_memblock_base + first_memblock_size);
587 #ifdef CONFIG_MEMORY_HOTPLUG
588 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
593 for (i = 0; i < PTRS_PER_PTE; i++) {
599 pte_free_kernel(&init_mm, pte_start);
603 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
608 for (i = 0; i < PTRS_PER_PMD; i++) {
614 pmd_free(&init_mm, pmd_start);
618 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
624 pte = pte_start + pte_index(addr);
625 for (; addr < end; addr = next, pte++) {
626 next = (addr + PAGE_SIZE) & PAGE_MASK;
630 if (!pte_present(*pte))
633 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
635 * The vmemmap_free() and remove_section_mapping()
636 * codepaths call us with aligned addresses.
638 WARN_ONCE(1, "%s: unaligned range\n", __func__);
642 pte_clear(&init_mm, addr, pte);
646 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
653 pmd = pmd_start + pmd_index(addr);
654 for (; addr < end; addr = next, pmd++) {
655 next = pmd_addr_end(addr, end);
657 if (!pmd_present(*pmd))
660 if (pmd_huge(*pmd)) {
661 if (!IS_ALIGNED(addr, PMD_SIZE) ||
662 !IS_ALIGNED(next, PMD_SIZE)) {
663 WARN_ONCE(1, "%s: unaligned range\n", __func__);
667 pte_clear(&init_mm, addr, (pte_t *)pmd);
671 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
672 remove_pte_table(pte_base, addr, next);
673 free_pte_table(pte_base, pmd);
677 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
684 pud = pud_start + pud_index(addr);
685 for (; addr < end; addr = next, pud++) {
686 next = pud_addr_end(addr, end);
688 if (!pud_present(*pud))
691 if (pud_huge(*pud)) {
692 if (!IS_ALIGNED(addr, PUD_SIZE) ||
693 !IS_ALIGNED(next, PUD_SIZE)) {
694 WARN_ONCE(1, "%s: unaligned range\n", __func__);
698 pte_clear(&init_mm, addr, (pte_t *)pud);
702 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
703 remove_pmd_table(pmd_base, addr, next);
704 free_pmd_table(pmd_base, pud);
708 static void remove_pagetable(unsigned long start, unsigned long end)
710 unsigned long addr, next;
714 spin_lock(&init_mm.page_table_lock);
716 for (addr = start; addr < end; addr = next) {
717 next = pgd_addr_end(addr, end);
719 pgd = pgd_offset_k(addr);
720 if (!pgd_present(*pgd))
723 if (pgd_huge(*pgd)) {
724 if (!IS_ALIGNED(addr, PGDIR_SIZE) ||
725 !IS_ALIGNED(next, PGDIR_SIZE)) {
726 WARN_ONCE(1, "%s: unaligned range\n", __func__);
730 pte_clear(&init_mm, addr, (pte_t *)pgd);
734 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
735 remove_pud_table(pud_base, addr, next);
738 spin_unlock(&init_mm.page_table_lock);
739 radix__flush_tlb_kernel_range(start, end);
742 int __ref radix__create_section_mapping(unsigned long start, unsigned long end)
744 return create_physical_mapping(start, end);
747 int radix__remove_section_mapping(unsigned long start, unsigned long end)
749 remove_pagetable(start, end);
752 #endif /* CONFIG_MEMORY_HOTPLUG */
754 #ifdef CONFIG_SPARSEMEM_VMEMMAP
755 int __meminit radix__vmemmap_create_mapping(unsigned long start,
756 unsigned long page_size,
759 /* Create a PTE encoding */
760 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
762 BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
766 #ifdef CONFIG_MEMORY_HOTPLUG
767 void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
769 remove_pagetable(start, start + page_size);
774 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
776 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
777 pmd_t *pmdp, unsigned long clr,
782 #ifdef CONFIG_DEBUG_VM
783 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
784 assert_spin_locked(&mm->page_table_lock);
787 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
788 trace_hugepage_update(addr, old, clr, set);
793 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
799 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
800 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
801 VM_BUG_ON(pmd_devmap(*pmdp));
803 * khugepaged calls this for normal pmd
807 /*FIXME!! Verify whether we need this kick below */
808 kick_all_cpus_sync();
809 flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
814 * For us pgtable_t is pte_t *. Inorder to save the deposisted
815 * page table, we consider the allocated page table as a list
816 * head. On withdraw we need to make sure we zero out the used
817 * list_head memory area.
819 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
822 struct list_head *lh = (struct list_head *) pgtable;
824 assert_spin_locked(pmd_lockptr(mm, pmdp));
827 if (!pmd_huge_pte(mm, pmdp))
830 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
831 pmd_huge_pte(mm, pmdp) = pgtable;
834 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
838 struct list_head *lh;
840 assert_spin_locked(pmd_lockptr(mm, pmdp));
843 pgtable = pmd_huge_pte(mm, pmdp);
844 lh = (struct list_head *) pgtable;
846 pmd_huge_pte(mm, pmdp) = NULL;
848 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
851 ptep = (pte_t *) pgtable;
859 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
860 unsigned long addr, pmd_t *pmdp)
865 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
866 old_pmd = __pmd(old);
868 * Serialize against find_linux_pte_or_hugepte which does lock-less
869 * lookup in page tables with local interrupts disabled. For huge pages
870 * it casts pmd_t to pte_t. Since format of pte_t is different from
871 * pmd_t we want to prevent transit from pmd pointing to page table
872 * to pmd pointing to huge page (and back) while interrupts are disabled.
873 * We clear pmd to possibly replace it with page table pointer in
874 * different code paths. So make sure we wait for the parallel
875 * find_linux_pte_or_hugepage to finish.
877 kick_all_cpus_sync();
881 int radix__has_transparent_hugepage(void)
883 /* For radix 2M at PMD level means thp */
884 if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
888 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */