2 * TLB flush routines for radix kernels.
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
13 #include <linux/hugetlb.h>
14 #include <linux/memblock.h>
15 #include <asm/ppc-opcode.h>
18 #include <asm/tlbflush.h>
20 static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
22 #define RIC_FLUSH_TLB 0
23 #define RIC_FLUSH_PWC 1
24 #define RIC_FLUSH_ALL 2
26 static inline void __tlbiel_pid(unsigned long pid, int set,
29 unsigned long rb,rs,prs,r;
31 rb = PPC_BIT(53); /* IS = 1 */
32 rb |= set << PPC_BITLSHIFT(51);
33 rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
34 prs = 1; /* process scoped */
35 r = 1; /* raidx format */
37 asm volatile("ptesync": : :"memory");
38 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
39 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
40 asm volatile("ptesync": : :"memory");
44 * We use 128 set in radix mode and 256 set in hpt mode.
46 static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
50 for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
51 __tlbiel_pid(pid, set, ric);
53 asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
56 static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
58 unsigned long rb,rs,prs,r;
60 rb = PPC_BIT(53); /* IS = 1 */
61 rs = pid << PPC_BITLSHIFT(31);
62 prs = 1; /* process scoped */
63 r = 1; /* raidx format */
65 asm volatile("ptesync": : :"memory");
66 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
67 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
68 asm volatile("eieio; tlbsync; ptesync": : :"memory");
71 static inline void _tlbiel_va(unsigned long va, unsigned long pid,
72 unsigned long ap, unsigned long ric)
74 unsigned long rb,rs,prs,r;
76 rb = va & ~(PPC_BITMASK(52, 63));
77 rb |= ap << PPC_BITLSHIFT(58);
78 rs = pid << PPC_BITLSHIFT(31);
79 prs = 1; /* process scoped */
80 r = 1; /* raidx format */
82 asm volatile("ptesync": : :"memory");
83 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
84 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
85 asm volatile("ptesync": : :"memory");
88 static inline void _tlbie_va(unsigned long va, unsigned long pid,
89 unsigned long ap, unsigned long ric)
91 unsigned long rb,rs,prs,r;
93 rb = va & ~(PPC_BITMASK(52, 63));
94 rb |= ap << PPC_BITLSHIFT(58);
95 rs = pid << PPC_BITLSHIFT(31);
96 prs = 1; /* process scoped */
97 r = 1; /* raidx format */
99 asm volatile("ptesync": : :"memory");
100 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
101 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
102 asm volatile("eieio; tlbsync; ptesync": : :"memory");
106 * Base TLB flushing operations:
108 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
109 * - flush_tlb_page(vma, vmaddr) flushes one page
110 * - flush_tlb_range(vma, start, end) flushes a range of pages
111 * - flush_tlb_kernel_range(start, end) flushes kernel pages
113 * - local_* variants of page and mm only apply to the current
116 void radix__local_flush_tlb_mm(struct mm_struct *mm)
121 pid = mm->context.id;
122 if (pid != MMU_NO_CONTEXT)
123 _tlbiel_pid(pid, RIC_FLUSH_ALL);
126 EXPORT_SYMBOL(radix__local_flush_tlb_mm);
128 void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
131 struct mm_struct *mm = tlb->mm;
133 * If we are doing a full mm flush, we will do a tlb flush
134 * with RIC_FLUSH_ALL later.
141 pid = mm->context.id;
142 if (pid != MMU_NO_CONTEXT)
143 _tlbiel_pid(pid, RIC_FLUSH_PWC);
147 EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
149 void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
153 unsigned long ap = mmu_get_ap(psize);
156 pid = mm ? mm->context.id : 0;
157 if (pid != MMU_NO_CONTEXT)
158 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
162 void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
164 #ifdef CONFIG_HUGETLB_PAGE
165 /* need the return fix for nohash.c */
166 if (vma && is_vm_hugetlb_page(vma))
167 return __local_flush_hugetlb_page(vma, vmaddr);
169 radix__local_flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
172 EXPORT_SYMBOL(radix__local_flush_tlb_page);
175 void radix__flush_tlb_mm(struct mm_struct *mm)
180 pid = mm->context.id;
181 if (unlikely(pid == MMU_NO_CONTEXT))
184 if (!mm_is_thread_local(mm)) {
185 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
188 raw_spin_lock(&native_tlbie_lock);
189 _tlbie_pid(pid, RIC_FLUSH_ALL);
191 raw_spin_unlock(&native_tlbie_lock);
193 _tlbiel_pid(pid, RIC_FLUSH_ALL);
197 EXPORT_SYMBOL(radix__flush_tlb_mm);
199 void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
202 struct mm_struct *mm = tlb->mm;
205 * If we are doing a full mm flush, we will do a tlb flush
206 * with RIC_FLUSH_ALL later.
212 pid = mm->context.id;
213 if (unlikely(pid == MMU_NO_CONTEXT))
216 if (!mm_is_thread_local(mm)) {
217 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
220 raw_spin_lock(&native_tlbie_lock);
221 _tlbie_pid(pid, RIC_FLUSH_PWC);
223 raw_spin_unlock(&native_tlbie_lock);
225 _tlbiel_pid(pid, RIC_FLUSH_PWC);
229 EXPORT_SYMBOL(radix__flush_tlb_pwc);
231 void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
235 unsigned long ap = mmu_get_ap(psize);
238 pid = mm ? mm->context.id : 0;
239 if (unlikely(pid == MMU_NO_CONTEXT))
241 if (!mm_is_thread_local(mm)) {
242 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
245 raw_spin_lock(&native_tlbie_lock);
246 _tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
248 raw_spin_unlock(&native_tlbie_lock);
250 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
255 void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
257 #ifdef CONFIG_HUGETLB_PAGE
258 if (vma && is_vm_hugetlb_page(vma))
259 return flush_hugetlb_page(vma, vmaddr);
261 radix__flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
264 EXPORT_SYMBOL(radix__flush_tlb_page);
266 #endif /* CONFIG_SMP */
268 void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
270 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
273 raw_spin_lock(&native_tlbie_lock);
274 _tlbie_pid(0, RIC_FLUSH_ALL);
276 raw_spin_unlock(&native_tlbie_lock);
278 EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
281 * Currently, for range flushing, we just do a full mm flush. Because
282 * we use this in code path where we don' track the page size.
284 void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
288 struct mm_struct *mm = vma->vm_mm;
289 radix__flush_tlb_mm(mm);
291 EXPORT_SYMBOL(radix__flush_tlb_range);
293 static int radix_get_mmu_psize(int page_size)
297 if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
298 psize = mmu_virtual_psize;
299 else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
301 else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
308 void radix__tlb_flush(struct mmu_gather *tlb)
311 struct mm_struct *mm = tlb->mm;
312 int page_size = tlb->page_size;
314 psize = radix_get_mmu_psize(page_size);
316 * if page size is not something we understand, do a full mm flush
318 if (psize != -1 && !tlb->fullmm && !tlb->need_flush_all)
319 radix__flush_tlb_range_psize(mm, tlb->start, tlb->end, psize);
321 radix__flush_tlb_mm(mm);
324 #define TLB_FLUSH_ALL -1UL
326 * Number of pages above which we will do a bcast tlbie. Just a
327 * number at this point copied from x86
329 static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
331 void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
332 unsigned long end, int psize)
336 int local = mm_is_thread_local(mm);
337 unsigned long ap = mmu_get_ap(psize);
338 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
339 unsigned long page_size = 1UL << mmu_psize_defs[psize].shift;
343 pid = mm ? mm->context.id : 0;
344 if (unlikely(pid == MMU_NO_CONTEXT))
347 if (end == TLB_FLUSH_ALL ||
348 (end - start) > tlb_single_page_flush_ceiling * page_size) {
350 _tlbiel_pid(pid, RIC_FLUSH_TLB);
352 _tlbie_pid(pid, RIC_FLUSH_TLB);
355 for (addr = start; addr < end; addr += page_size) {
358 _tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
361 raw_spin_lock(&native_tlbie_lock);
362 _tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
364 raw_spin_unlock(&native_tlbie_lock);
371 void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
372 unsigned long page_size)
374 unsigned long rb,rs,prs,r;
376 unsigned long ric = RIC_FLUSH_TLB;
378 ap = mmu_get_ap(radix_get_mmu_psize(page_size));
379 rb = gpa & ~(PPC_BITMASK(52, 63));
380 rb |= ap << PPC_BITLSHIFT(58);
381 rs = lpid & ((1UL << 32) - 1);
382 prs = 0; /* process scoped */
383 r = 1; /* raidx format */
385 asm volatile("ptesync": : :"memory");
386 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
387 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
388 asm volatile("eieio; tlbsync; ptesync": : :"memory");
390 EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
392 void radix__flush_tlb_lpid(unsigned long lpid)
394 unsigned long rb,rs,prs,r;
395 unsigned long ric = RIC_FLUSH_ALL;
397 rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
398 rs = lpid & ((1UL << 32) - 1);
399 prs = 0; /* partition scoped */
400 r = 1; /* raidx format */
402 asm volatile("ptesync": : :"memory");
403 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
404 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
405 asm volatile("eieio; tlbsync; ptesync": : :"memory");
407 EXPORT_SYMBOL(radix__flush_tlb_lpid);
409 void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
410 unsigned long start, unsigned long end)
412 radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
414 EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
416 void radix__flush_tlb_all(void)
418 unsigned long rb,prs,r,rs;
419 unsigned long ric = RIC_FLUSH_ALL;
421 rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
422 prs = 0; /* partition scoped */
423 r = 1; /* raidx format */
424 rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */
426 asm volatile("ptesync": : :"memory");
428 * now flush guest entries by passing PRS = 1 and LPID != 0
430 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
431 : : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
433 * now flush host entires by passing PRS = 0 and LPID == 0
435 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
436 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
437 asm volatile("eieio; tlbsync; ptesync": : :"memory");
440 void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
441 unsigned long address)
444 * We track page size in pte only for DD1, So we can
445 * call this only on DD1.
447 if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) {
452 if (old_pte & R_PAGE_LARGE)
453 radix__flush_tlb_page_psize(mm, address, MMU_PAGE_2M);
455 radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);