arch/powerpc/platforms/85xx/xes_mpc85xx.c

   1 /*
   2  * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
   3  *
   4  * X-ES board-specific functionality
   5  *
   6  * Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
   7  *
   8  * Author: Nate Case <ncase@xes-inc.com>
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/delay.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/of_platform.h>
  23
  24 #include <asm/system.h>
  25 #include <asm/time.h>
  26 #include <asm/machdep.h>
  27 #include <asm/pci-bridge.h>
  28 #include <mm/mmu_decl.h>
  29 #include <asm/prom.h>
  30 #include <asm/udbg.h>
  31 #include <asm/mpic.h>
  32
  33 #include <sysdev/fsl_soc.h>
  34 #include <sysdev/fsl_pci.h>
  35
  36 #include "mpc85xx.h"
  37
  38 /* A few bit definitions needed for fixups on some boards */
  39 #define MPC85xx_L2CTL_L2E               0x80000000 /* L2 enable */
  40 #define MPC85xx_L2CTL_L2I               0x40000000 /* L2 flash invalidate */
  41 #define MPC85xx_L2CTL_L2SIZ_MASK        0x30000000 /* L2 SRAM size (R/O) */
  42
  43 void __init xes_mpc85xx_pic_init(void)
  44 {
  45         struct mpic *mpic;
  46         struct resource r;
  47         struct device_node *np;
  48
  49         np = of_find_node_by_type(NULL, "open-pic");
  50         if (np == NULL) {
  51                 printk(KERN_ERR "Could not find open-pic node\n");
  52                 return;
  53         }
  54
  55         if (of_address_to_resource(np, 0, &r)) {
  56                 printk(KERN_ERR "Failed to map mpic register space\n");
  57                 of_node_put(np);
  58                 return;
  59         }
  60
  61         mpic = mpic_alloc(np, r.start,
  62                           MPIC_PRIMARY | MPIC_WANTS_RESET |
  63                           MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
  64                         0, 256, " OpenPIC  ");
  65         BUG_ON(mpic == NULL);
  66         of_node_put(np);
  67
  68         mpic_init(mpic);
  69 }
  70
  71 static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
  72 {
  73         volatile uint32_t ctl, tmp;
  74
  75         asm volatile("msync; isync");
  76         tmp = in_be32(l2_base);
  77
  78         /*
  79          * xMon may have enabled part of L2 as SRAM, so we need to set it
  80          * up for all cache mode just to be safe.
  81          */
  82         printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
  83
  84         ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
  85         if (of_machine_is_compatible("MPC8540") ||
  86             of_machine_is_compatible("MPC8560"))
  87                 /*
  88                  * Assume L2 SRAM is used fully for cache, so set
  89                  * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
  90                  */
  91                 ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
  92
  93         asm volatile("msync; isync");
  94         out_be32(l2_base, ctl);
  95         asm volatile("msync; isync");
  96 }
  97
  98 static void xes_mpc85xx_fixups(void)
  99 {
 100         struct device_node *np;
 101         int err;
 102
 103         /*
 104          * Legacy xMon firmware on some X-ES boards does not enable L2
 105          * as cache.  We must ensure that they get enabled here.
 106          */
 107         for_each_node_by_name(np, "l2-cache-controller") {
 108                 struct resource r[2];
 109                 void __iomem *l2_base;
 110
 111                 /* Only MPC8548, MPC8540, and MPC8560 boards are affected */
 112                 if (!of_device_is_compatible(np,
 113                                     "fsl,mpc8548-l2-cache-controller") &&
 114                     !of_device_is_compatible(np,
 115                                     "fsl,mpc8540-l2-cache-controller") &&
 116                     !of_device_is_compatible(np,
 117                                     "fsl,mpc8560-l2-cache-controller"))
 118                         continue;
 119
 120                 err = of_address_to_resource(np, 0, &r[0]);
 121                 if (err) {
 122                         printk(KERN_WARNING "xes_mpc85xx: Could not get "
 123                                "resource for device tree node '%s'",
 124                                np->full_name);
 125                         continue;
 126                 }
 127
 128                 l2_base = ioremap(r[0].start, resource_size(&r[0]));
 129
 130                 xes_mpc85xx_configure_l2(l2_base);
 131         }
 132 }
 133
 134 #ifdef CONFIG_PCI
 135 static int primary_phb_addr;
 136 #endif
 137
 138 /*
 139  * Setup the architecture
 140  */
 141 #ifdef CONFIG_SMP
 142 extern void __init mpc85xx_smp_init(void);
 143 #endif
 144 static void __init xes_mpc85xx_setup_arch(void)
 145 {
 146 #ifdef CONFIG_PCI
 147         struct device_node *np;
 148 #endif
 149         struct device_node *root;
 150         const char *model = "Unknown";
 151
 152         root = of_find_node_by_path("/");
 153         if (root == NULL)
 154                 return;
 155
 156         model = of_get_property(root, "model", NULL);
 157
 158         printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
 159                model + strlen("xes,"));
 160
 161         xes_mpc85xx_fixups();
 162
 163 #ifdef CONFIG_PCI
 164         for_each_node_by_type(np, "pci") {
 165                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 166                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 167                         struct resource rsrc;
 168                         of_address_to_resource(np, 0, &rsrc);
 169                         if ((rsrc.start & 0xfffff) == primary_phb_addr)
 170                                 fsl_add_bridge(np, 1);
 171                         else
 172                                 fsl_add_bridge(np, 0);
 173                 }
 174         }
 175 #endif
 176
 177 #ifdef CONFIG_SMP
 178         mpc85xx_smp_init();
 179 #endif
 180 }
 181
 182 machine_device_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
 183 machine_device_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
 184 machine_device_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
 185
 186 /*
 187  * Called very early, device-tree isn't unflattened
 188  */
 189 static int __init xes_mpc8572_probe(void)
 190 {
 191         unsigned long root = of_get_flat_dt_root();
 192
 193         if (of_flat_dt_is_compatible(root, "xes,MPC8572")) {
 194 #ifdef CONFIG_PCI
 195                 primary_phb_addr = 0x8000;
 196 #endif
 197                 return 1;
 198         } else {
 199                 return 0;
 200         }
 201 }
 202
 203 static int __init xes_mpc8548_probe(void)
 204 {
 205         unsigned long root = of_get_flat_dt_root();
 206
 207         if (of_flat_dt_is_compatible(root, "xes,MPC8548")) {
 208 #ifdef CONFIG_PCI
 209                 primary_phb_addr = 0xb000;
 210 #endif
 211                 return 1;
 212         } else {
 213                 return 0;
 214         }
 215 }
 216
 217 static int __init xes_mpc8540_probe(void)
 218 {
 219         unsigned long root = of_get_flat_dt_root();
 220
 221         if (of_flat_dt_is_compatible(root, "xes,MPC8540")) {
 222 #ifdef CONFIG_PCI
 223                 primary_phb_addr = 0xb000;
 224 #endif
 225                 return 1;
 226         } else {
 227                 return 0;
 228         }
 229 }
 230
 231 define_machine(xes_mpc8572) {
 232         .name                   = "X-ES MPC8572",
 233         .probe                  = xes_mpc8572_probe,
 234         .setup_arch             = xes_mpc85xx_setup_arch,
 235         .init_IRQ               = xes_mpc85xx_pic_init,
 236 #ifdef CONFIG_PCI
 237         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 238 #endif
 239         .get_irq                = mpic_get_irq,
 240         .restart                = fsl_rstcr_restart,
 241         .calibrate_decr         = generic_calibrate_decr,
 242         .progress               = udbg_progress,
 243 };
 244
 245 define_machine(xes_mpc8548) {
 246         .name                   = "X-ES MPC8548",
 247         .probe                  = xes_mpc8548_probe,
 248         .setup_arch             = xes_mpc85xx_setup_arch,
 249         .init_IRQ               = xes_mpc85xx_pic_init,
 250 #ifdef CONFIG_PCI
 251         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 252 #endif
 253         .get_irq                = mpic_get_irq,
 254         .restart                = fsl_rstcr_restart,
 255         .calibrate_decr         = generic_calibrate_decr,
 256         .progress               = udbg_progress,
 257 };
 258
 259 define_machine(xes_mpc8540) {
 260         .name                   = "X-ES MPC8540",
 261         .probe                  = xes_mpc8540_probe,
 262         .setup_arch             = xes_mpc85xx_setup_arch,
 263         .init_IRQ               = xes_mpc85xx_pic_init,
 264 #ifdef CONFIG_PCI
 265         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 266 #endif
 267         .get_irq                = mpic_get_irq,
 268         .restart                = fsl_rstcr_restart,
 269         .calibrate_decr         = generic_calibrate_decr,
 270         .progress               = udbg_progress,
 271 };