2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
21 #include <linux/irq.h>
23 #include <linux/msi.h>
24 #include <linux/memblock.h>
25 #include <linux/iommu.h>
26 #include <linux/rculist.h>
27 #include <linux/sizes.h>
29 #include <asm/sections.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/machdep.h>
34 #include <asm/msi_bitmap.h>
35 #include <asm/ppc-pci.h>
37 #include <asm/iommu.h>
40 #include <asm/debugfs.h>
41 #include <asm/firmware.h>
42 #include <asm/pnv-pci.h>
43 #include <asm/mmzone.h>
45 #include <misc/cxl-base.h>
50 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
51 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
54 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
55 #define POWERNV_IOMMU_MAX_LEVELS 5
57 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
60 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
72 if (pe->flags & PNV_IODA_PE_DEV)
73 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
74 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
75 sprintf(pfix, "%04x:%02x ",
76 pci_domain_nr(pe->pbus), pe->pbus->number);
78 else if (pe->flags & PNV_IODA_PE_VF)
79 sprintf(pfix, "%04x:%02x:%2x.%d",
80 pci_domain_nr(pe->parent_dev->bus),
81 (pe->rid & 0xff00) >> 8,
82 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
83 #endif /* CONFIG_PCI_IOV*/
85 printk("%spci %s: [PE# %.2x] %pV",
86 level, pfix, pe->pe_number, &vaf);
91 static bool pnv_iommu_bypass_disabled __read_mostly;
93 static int __init iommu_setup(char *str)
99 if (!strncmp(str, "nobypass", 8)) {
100 pnv_iommu_bypass_disabled = true;
101 pr_info("PowerNV: IOMMU bypass window disabled.\n");
104 str += strcspn(str, ",");
111 early_param("iommu", iommu_setup);
113 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
116 * WARNING: We cannot rely on the resource flags. The Linux PCI
117 * allocation code sometimes decides to put a 64-bit prefetchable
118 * BAR in the 32-bit window, so we have to compare the addresses.
120 * For simplicity we only test resource start.
122 return (r->start >= phb->ioda.m64_base &&
123 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
126 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
128 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
130 return (resource_flags & flags) == flags;
133 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
137 phb->ioda.pe_array[pe_no].phb = phb;
138 phb->ioda.pe_array[pe_no].pe_number = pe_no;
141 * Clear the PE frozen state as it might be put into frozen state
142 * in the last PCI remove path. It's not harmful to do so when the
143 * PE is already in unfrozen state.
145 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
146 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
147 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
148 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
149 __func__, rc, phb->hose->global_number, pe_no);
151 return &phb->ioda.pe_array[pe_no];
154 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
156 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
157 pr_warn("%s: Invalid PE %x on PHB#%x\n",
158 __func__, pe_no, phb->hose->global_number);
162 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
163 pr_debug("%s: PE %x was reserved on PHB#%x\n",
164 __func__, pe_no, phb->hose->global_number);
166 pnv_ioda_init_pe(phb, pe_no);
169 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
173 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
174 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
175 return pnv_ioda_init_pe(phb, pe);
181 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
183 struct pnv_phb *phb = pe->phb;
184 unsigned int pe_num = pe->pe_number;
188 memset(pe, 0, sizeof(struct pnv_ioda_pe));
189 clear_bit(pe_num, phb->ioda.pe_alloc);
192 /* The default M64 BAR is shared by all PEs */
193 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
199 /* Configure the default M64 BAR */
200 rc = opal_pci_set_phb_mem_window(phb->opal_id,
201 OPAL_M64_WINDOW_TYPE,
202 phb->ioda.m64_bar_idx,
206 if (rc != OPAL_SUCCESS) {
207 desc = "configuring";
211 /* Enable the default M64 BAR */
212 rc = opal_pci_phb_mmio_enable(phb->opal_id,
213 OPAL_M64_WINDOW_TYPE,
214 phb->ioda.m64_bar_idx,
215 OPAL_ENABLE_M64_SPLIT);
216 if (rc != OPAL_SUCCESS) {
222 * Exclude the segments for reserved and root bus PE, which
223 * are first or last two PEs.
225 r = &phb->hose->mem_resources[1];
226 if (phb->ioda.reserved_pe_idx == 0)
227 r->start += (2 * phb->ioda.m64_segsize);
228 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
229 r->end -= (2 * phb->ioda.m64_segsize);
231 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
232 phb->ioda.reserved_pe_idx);
237 pr_warn(" Failure %lld %s M64 BAR#%d\n",
238 rc, desc, phb->ioda.m64_bar_idx);
239 opal_pci_phb_mmio_enable(phb->opal_id,
240 OPAL_M64_WINDOW_TYPE,
241 phb->ioda.m64_bar_idx,
246 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
247 unsigned long *pe_bitmap)
249 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
250 struct pnv_phb *phb = hose->private_data;
252 resource_size_t base, sgsz, start, end;
255 base = phb->ioda.m64_base;
256 sgsz = phb->ioda.m64_segsize;
257 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
258 r = &pdev->resource[i];
259 if (!r->parent || !pnv_pci_is_m64(phb, r))
262 start = _ALIGN_DOWN(r->start - base, sgsz);
263 end = _ALIGN_UP(r->end - base, sgsz);
264 for (segno = start / sgsz; segno < end / sgsz; segno++) {
266 set_bit(segno, pe_bitmap);
268 pnv_ioda_reserve_pe(phb, segno);
273 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
279 * There are 16 M64 BARs, each of which has 8 segments. So
280 * there are as many M64 segments as the maximum number of
283 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
284 unsigned long base, segsz = phb->ioda.m64_segsize;
287 base = phb->ioda.m64_base +
288 index * PNV_IODA1_M64_SEGS * segsz;
289 rc = opal_pci_set_phb_mem_window(phb->opal_id,
290 OPAL_M64_WINDOW_TYPE, index, base, 0,
291 PNV_IODA1_M64_SEGS * segsz);
292 if (rc != OPAL_SUCCESS) {
293 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
294 rc, phb->hose->global_number, index);
298 rc = opal_pci_phb_mmio_enable(phb->opal_id,
299 OPAL_M64_WINDOW_TYPE, index,
300 OPAL_ENABLE_M64_SPLIT);
301 if (rc != OPAL_SUCCESS) {
302 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
303 rc, phb->hose->global_number, index);
309 * Exclude the segments for reserved and root bus PE, which
310 * are first or last two PEs.
312 r = &phb->hose->mem_resources[1];
313 if (phb->ioda.reserved_pe_idx == 0)
314 r->start += (2 * phb->ioda.m64_segsize);
315 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
316 r->end -= (2 * phb->ioda.m64_segsize);
318 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
319 phb->ioda.reserved_pe_idx, phb->hose->global_number);
324 for ( ; index >= 0; index--)
325 opal_pci_phb_mmio_enable(phb->opal_id,
326 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
331 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
332 unsigned long *pe_bitmap,
335 struct pci_dev *pdev;
337 list_for_each_entry(pdev, &bus->devices, bus_list) {
338 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
340 if (all && pdev->subordinate)
341 pnv_ioda_reserve_m64_pe(pdev->subordinate,
346 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
348 struct pci_controller *hose = pci_bus_to_host(bus);
349 struct pnv_phb *phb = hose->private_data;
350 struct pnv_ioda_pe *master_pe, *pe;
351 unsigned long size, *pe_alloc;
354 /* Root bus shouldn't use M64 */
355 if (pci_is_root_bus(bus))
358 /* Allocate bitmap */
359 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
360 pe_alloc = kzalloc(size, GFP_KERNEL);
362 pr_warn("%s: Out of memory !\n",
367 /* Figure out reserved PE numbers by the PE */
368 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
371 * the current bus might not own M64 window and that's all
372 * contributed by its child buses. For the case, we needn't
373 * pick M64 dependent PE#.
375 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
381 * Figure out the master PE and put all slave PEs to master
382 * PE's list to form compound PE.
386 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
387 phb->ioda.total_pe_num) {
388 pe = &phb->ioda.pe_array[i];
390 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
392 pe->flags |= PNV_IODA_PE_MASTER;
393 INIT_LIST_HEAD(&pe->slaves);
396 pe->flags |= PNV_IODA_PE_SLAVE;
397 pe->master = master_pe;
398 list_add_tail(&pe->list, &master_pe->slaves);
402 * P7IOC supports M64DT, which helps mapping M64 segment
403 * to one particular PE#. However, PHB3 has fixed mapping
404 * between M64 segment and PE#. In order to have same logic
405 * for P7IOC and PHB3, we enforce fixed mapping between M64
406 * segment and PE# on P7IOC.
408 if (phb->type == PNV_PHB_IODA1) {
411 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
412 pe->pe_number, OPAL_M64_WINDOW_TYPE,
413 pe->pe_number / PNV_IODA1_M64_SEGS,
414 pe->pe_number % PNV_IODA1_M64_SEGS);
415 if (rc != OPAL_SUCCESS)
416 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
417 __func__, rc, phb->hose->global_number,
426 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
428 struct pci_controller *hose = phb->hose;
429 struct device_node *dn = hose->dn;
430 struct resource *res;
435 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
436 pr_info(" Not support M64 window\n");
440 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
441 pr_info(" Firmware too old to support M64 window\n");
445 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
447 pr_info(" No <ibm,opal-m64-window> on %s\n",
453 * Find the available M64 BAR range and pickup the last one for
454 * covering the whole 64-bits space. We support only one range.
456 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
458 /* In absence of the property, assume 0..15 */
462 /* We only support 64 bits in our allocator */
463 if (m64_range[1] > 63) {
464 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
465 __func__, m64_range[1], phb->hose->global_number);
468 /* Empty range, no m64 */
469 if (m64_range[1] <= m64_range[0]) {
470 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
471 __func__, phb->hose->global_number);
475 /* Configure M64 informations */
476 res = &hose->mem_resources[1];
477 res->name = dn->full_name;
478 res->start = of_translate_address(dn, r + 2);
479 res->end = res->start + of_read_number(r + 4, 2) - 1;
480 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
481 pci_addr = of_read_number(r, 2);
482 hose->mem_offset[1] = res->start - pci_addr;
484 phb->ioda.m64_size = resource_size(res);
485 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
486 phb->ioda.m64_base = pci_addr;
488 /* This lines up nicely with the display from processing OF ranges */
489 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
490 res->start, res->end, pci_addr, m64_range[0],
491 m64_range[0] + m64_range[1] - 1);
493 /* Mark all M64 used up by default */
494 phb->ioda.m64_bar_alloc = (unsigned long)-1;
496 /* Use last M64 BAR to cover M64 window */
498 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
500 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
502 /* Mark remaining ones free */
503 for (i = m64_range[0]; i < m64_range[1]; i++)
504 clear_bit(i, &phb->ioda.m64_bar_alloc);
507 * Setup init functions for M64 based on IODA version, IODA3 uses
510 if (phb->type == PNV_PHB_IODA1)
511 phb->init_m64 = pnv_ioda1_init_m64;
513 phb->init_m64 = pnv_ioda2_init_m64;
514 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
515 phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
518 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
520 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
521 struct pnv_ioda_pe *slave;
524 /* Fetch master PE */
525 if (pe->flags & PNV_IODA_PE_SLAVE) {
527 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
530 pe_no = pe->pe_number;
533 /* Freeze master PE */
534 rc = opal_pci_eeh_freeze_set(phb->opal_id,
536 OPAL_EEH_ACTION_SET_FREEZE_ALL);
537 if (rc != OPAL_SUCCESS) {
538 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
539 __func__, rc, phb->hose->global_number, pe_no);
543 /* Freeze slave PEs */
544 if (!(pe->flags & PNV_IODA_PE_MASTER))
547 list_for_each_entry(slave, &pe->slaves, list) {
548 rc = opal_pci_eeh_freeze_set(phb->opal_id,
550 OPAL_EEH_ACTION_SET_FREEZE_ALL);
551 if (rc != OPAL_SUCCESS)
552 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
553 __func__, rc, phb->hose->global_number,
558 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
560 struct pnv_ioda_pe *pe, *slave;
564 pe = &phb->ioda.pe_array[pe_no];
565 if (pe->flags & PNV_IODA_PE_SLAVE) {
567 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
568 pe_no = pe->pe_number;
571 /* Clear frozen state for master PE */
572 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
573 if (rc != OPAL_SUCCESS) {
574 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
575 __func__, rc, opt, phb->hose->global_number, pe_no);
579 if (!(pe->flags & PNV_IODA_PE_MASTER))
582 /* Clear frozen state for slave PEs */
583 list_for_each_entry(slave, &pe->slaves, list) {
584 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
587 if (rc != OPAL_SUCCESS) {
588 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
589 __func__, rc, opt, phb->hose->global_number,
598 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
600 struct pnv_ioda_pe *slave, *pe;
605 /* Sanity check on PE number */
606 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
607 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
610 * Fetch the master PE and the PE instance might be
611 * not initialized yet.
613 pe = &phb->ioda.pe_array[pe_no];
614 if (pe->flags & PNV_IODA_PE_SLAVE) {
616 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
617 pe_no = pe->pe_number;
620 /* Check the master PE */
621 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
622 &state, &pcierr, NULL);
623 if (rc != OPAL_SUCCESS) {
624 pr_warn("%s: Failure %lld getting "
625 "PHB#%x-PE#%x state\n",
627 phb->hose->global_number, pe_no);
628 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
631 /* Check the slave PE */
632 if (!(pe->flags & PNV_IODA_PE_MASTER))
635 list_for_each_entry(slave, &pe->slaves, list) {
636 rc = opal_pci_eeh_freeze_status(phb->opal_id,
641 if (rc != OPAL_SUCCESS) {
642 pr_warn("%s: Failure %lld getting "
643 "PHB#%x-PE#%x state\n",
645 phb->hose->global_number, slave->pe_number);
646 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
650 * Override the result based on the ascending
660 /* Currently those 2 are only used when MSIs are enabled, this will change
661 * but in the meantime, we need to protect them to avoid warnings
663 #ifdef CONFIG_PCI_MSI
664 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
666 struct pci_controller *hose = pci_bus_to_host(dev->bus);
667 struct pnv_phb *phb = hose->private_data;
668 struct pci_dn *pdn = pci_get_pdn(dev);
672 if (pdn->pe_number == IODA_INVALID_PE)
674 return &phb->ioda.pe_array[pdn->pe_number];
676 #endif /* CONFIG_PCI_MSI */
678 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
679 struct pnv_ioda_pe *parent,
680 struct pnv_ioda_pe *child,
683 const char *desc = is_add ? "adding" : "removing";
684 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
685 OPAL_REMOVE_PE_FROM_DOMAIN;
686 struct pnv_ioda_pe *slave;
689 /* Parent PE affects child PE */
690 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
691 child->pe_number, op);
692 if (rc != OPAL_SUCCESS) {
693 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
698 if (!(child->flags & PNV_IODA_PE_MASTER))
701 /* Compound case: parent PE affects slave PEs */
702 list_for_each_entry(slave, &child->slaves, list) {
703 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
704 slave->pe_number, op);
705 if (rc != OPAL_SUCCESS) {
706 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
715 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
716 struct pnv_ioda_pe *pe,
719 struct pnv_ioda_pe *slave;
720 struct pci_dev *pdev = NULL;
724 * Clear PE frozen state. If it's master PE, we need
725 * clear slave PE frozen state as well.
728 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
729 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
730 if (pe->flags & PNV_IODA_PE_MASTER) {
731 list_for_each_entry(slave, &pe->slaves, list)
732 opal_pci_eeh_freeze_clear(phb->opal_id,
734 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
739 * Associate PE in PELT. We need add the PE into the
740 * corresponding PELT-V as well. Otherwise, the error
741 * originated from the PE might contribute to other
744 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
748 /* For compound PEs, any one affects all of them */
749 if (pe->flags & PNV_IODA_PE_MASTER) {
750 list_for_each_entry(slave, &pe->slaves, list) {
751 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
757 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
758 pdev = pe->pbus->self;
759 else if (pe->flags & PNV_IODA_PE_DEV)
760 pdev = pe->pdev->bus->self;
761 #ifdef CONFIG_PCI_IOV
762 else if (pe->flags & PNV_IODA_PE_VF)
763 pdev = pe->parent_dev;
764 #endif /* CONFIG_PCI_IOV */
766 struct pci_dn *pdn = pci_get_pdn(pdev);
767 struct pnv_ioda_pe *parent;
769 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
770 parent = &phb->ioda.pe_array[pdn->pe_number];
771 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
776 pdev = pdev->bus->self;
782 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
784 struct pci_dev *parent;
785 uint8_t bcomp, dcomp, fcomp;
789 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
793 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
794 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
795 parent = pe->pbus->self;
796 if (pe->flags & PNV_IODA_PE_BUS_ALL)
797 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
802 case 1: bcomp = OpalPciBusAll; break;
803 case 2: bcomp = OpalPciBus7Bits; break;
804 case 4: bcomp = OpalPciBus6Bits; break;
805 case 8: bcomp = OpalPciBus5Bits; break;
806 case 16: bcomp = OpalPciBus4Bits; break;
807 case 32: bcomp = OpalPciBus3Bits; break;
809 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
811 /* Do an exact match only */
812 bcomp = OpalPciBusAll;
814 rid_end = pe->rid + (count << 8);
816 #ifdef CONFIG_PCI_IOV
817 if (pe->flags & PNV_IODA_PE_VF)
818 parent = pe->parent_dev;
821 parent = pe->pdev->bus->self;
822 bcomp = OpalPciBusAll;
823 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
824 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
825 rid_end = pe->rid + 1;
828 /* Clear the reverse map */
829 for (rid = pe->rid; rid < rid_end; rid++)
830 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
832 /* Release from all parents PELT-V */
834 struct pci_dn *pdn = pci_get_pdn(parent);
835 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
836 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
837 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
838 /* XXX What to do in case of error ? */
840 parent = parent->bus->self;
843 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
844 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
846 /* Disassociate PE in PELT */
847 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
848 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
850 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
851 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
852 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
854 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
858 #ifdef CONFIG_PCI_IOV
859 pe->parent_dev = NULL;
865 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
867 struct pci_dev *parent;
868 uint8_t bcomp, dcomp, fcomp;
869 long rc, rid_end, rid;
871 /* Bus validation ? */
875 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
876 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
877 parent = pe->pbus->self;
878 if (pe->flags & PNV_IODA_PE_BUS_ALL)
879 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
884 case 1: bcomp = OpalPciBusAll; break;
885 case 2: bcomp = OpalPciBus7Bits; break;
886 case 4: bcomp = OpalPciBus6Bits; break;
887 case 8: bcomp = OpalPciBus5Bits; break;
888 case 16: bcomp = OpalPciBus4Bits; break;
889 case 32: bcomp = OpalPciBus3Bits; break;
891 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
893 /* Do an exact match only */
894 bcomp = OpalPciBusAll;
896 rid_end = pe->rid + (count << 8);
898 #ifdef CONFIG_PCI_IOV
899 if (pe->flags & PNV_IODA_PE_VF)
900 parent = pe->parent_dev;
902 #endif /* CONFIG_PCI_IOV */
903 parent = pe->pdev->bus->self;
904 bcomp = OpalPciBusAll;
905 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
906 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
907 rid_end = pe->rid + 1;
911 * Associate PE in PELT. We need add the PE into the
912 * corresponding PELT-V as well. Otherwise, the error
913 * originated from the PE might contribute to other
916 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
917 bcomp, dcomp, fcomp, OPAL_MAP_PE);
919 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
924 * Configure PELTV. NPUs don't have a PELTV table so skip
925 * configuration on them.
927 if (phb->type != PNV_PHB_NPU)
928 pnv_ioda_set_peltv(phb, pe, true);
930 /* Setup reverse map */
931 for (rid = pe->rid; rid < rid_end; rid++)
932 phb->ioda.pe_rmap[rid] = pe->pe_number;
934 /* Setup one MVTs on IODA1 */
935 if (phb->type != PNV_PHB_IODA1) {
940 pe->mve_number = pe->pe_number;
941 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
942 if (rc != OPAL_SUCCESS) {
943 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
947 rc = opal_pci_set_mve_enable(phb->opal_id,
948 pe->mve_number, OPAL_ENABLE_MVE);
950 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
960 #ifdef CONFIG_PCI_IOV
961 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
963 struct pci_dn *pdn = pci_get_pdn(dev);
965 struct resource *res, res2;
966 resource_size_t size;
973 * "offset" is in VFs. The M64 windows are sized so that when they
974 * are segmented, each segment is the same size as the IOV BAR.
975 * Each segment is in a separate PE, and the high order bits of the
976 * address are the PE number. Therefore, each VF's BAR is in a
977 * separate PE, and changing the IOV BAR start address changes the
978 * range of PEs the VFs are in.
980 num_vfs = pdn->num_vfs;
981 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
982 res = &dev->resource[i + PCI_IOV_RESOURCES];
983 if (!res->flags || !res->parent)
987 * The actual IOV BAR range is determined by the start address
988 * and the actual size for num_vfs VFs BAR. This check is to
989 * make sure that after shifting, the range will not overlap
990 * with another device.
992 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
993 res2.flags = res->flags;
994 res2.start = res->start + (size * offset);
995 res2.end = res2.start + (size * num_vfs) - 1;
997 if (res2.end > res->end) {
998 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
999 i, &res2, res, num_vfs, offset);
1005 * After doing so, there would be a "hole" in the /proc/iomem when
1006 * offset is a positive value. It looks like the device return some
1007 * mmio back to the system, which actually no one could use it.
1009 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1010 res = &dev->resource[i + PCI_IOV_RESOURCES];
1011 if (!res->flags || !res->parent)
1014 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1016 res->start += size * offset;
1018 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1019 i, &res2, res, (offset > 0) ? "En" : "Dis",
1021 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1025 #endif /* CONFIG_PCI_IOV */
1027 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1029 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1030 struct pnv_phb *phb = hose->private_data;
1031 struct pci_dn *pdn = pci_get_pdn(dev);
1032 struct pnv_ioda_pe *pe;
1035 pr_err("%s: Device tree node not associated properly\n",
1039 if (pdn->pe_number != IODA_INVALID_PE)
1042 pe = pnv_ioda_alloc_pe(phb);
1044 pr_warning("%s: Not enough PE# available, disabling device\n",
1049 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1050 * pointer in the PE data structure, both should be destroyed at the
1051 * same time. However, this needs to be looked at more closely again
1052 * once we actually start removing things (Hotplug, SR-IOV, ...)
1054 * At some point we want to remove the PDN completely anyways
1058 pdn->pe_number = pe->pe_number;
1059 pe->flags = PNV_IODA_PE_DEV;
1062 pe->mve_number = -1;
1063 pe->rid = dev->bus->number << 8 | pdn->devfn;
1065 pe_info(pe, "Associated device to PE\n");
1067 if (pnv_ioda_configure_pe(phb, pe)) {
1068 /* XXX What do we do here ? */
1069 pnv_ioda_free_pe(pe);
1070 pdn->pe_number = IODA_INVALID_PE;
1076 /* Put PE to the list */
1077 list_add_tail(&pe->list, &phb->ioda.pe_list);
1082 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1084 struct pci_dev *dev;
1086 list_for_each_entry(dev, &bus->devices, bus_list) {
1087 struct pci_dn *pdn = pci_get_pdn(dev);
1090 pr_warn("%s: No device node associated with device !\n",
1096 * In partial hotplug case, the PCI device might be still
1097 * associated with the PE and needn't attach it to the PE
1100 if (pdn->pe_number != IODA_INVALID_PE)
1105 pdn->pe_number = pe->pe_number;
1106 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1107 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1112 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1113 * single PCI bus. Another one that contains the primary PCI bus and its
1114 * subordinate PCI devices and buses. The second type of PE is normally
1115 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1117 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1119 struct pci_controller *hose = pci_bus_to_host(bus);
1120 struct pnv_phb *phb = hose->private_data;
1121 struct pnv_ioda_pe *pe = NULL;
1122 unsigned int pe_num;
1125 * In partial hotplug case, the PE instance might be still alive.
1126 * We should reuse it instead of allocating a new one.
1128 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1129 if (pe_num != IODA_INVALID_PE) {
1130 pe = &phb->ioda.pe_array[pe_num];
1131 pnv_ioda_setup_same_PE(bus, pe);
1135 /* PE number for root bus should have been reserved */
1136 if (pci_is_root_bus(bus) &&
1137 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1138 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1140 /* Check if PE is determined by M64 */
1141 if (!pe && phb->pick_m64_pe)
1142 pe = phb->pick_m64_pe(bus, all);
1144 /* The PE number isn't pinned by M64 */
1146 pe = pnv_ioda_alloc_pe(phb);
1149 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1150 __func__, pci_domain_nr(bus), bus->number);
1154 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1157 pe->mve_number = -1;
1158 pe->rid = bus->busn_res.start << 8;
1161 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1162 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1164 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1165 bus->busn_res.start, pe->pe_number);
1167 if (pnv_ioda_configure_pe(phb, pe)) {
1168 /* XXX What do we do here ? */
1169 pnv_ioda_free_pe(pe);
1174 /* Associate it with all child devices */
1175 pnv_ioda_setup_same_PE(bus, pe);
1177 /* Put PE to the list */
1178 list_add_tail(&pe->list, &phb->ioda.pe_list);
1183 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1185 int pe_num, found_pe = false, rc;
1187 struct pnv_ioda_pe *pe;
1188 struct pci_dev *gpu_pdev;
1189 struct pci_dn *npu_pdn;
1190 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1191 struct pnv_phb *phb = hose->private_data;
1194 * Due to a hardware errata PE#0 on the NPU is reserved for
1195 * error handling. This means we only have three PEs remaining
1196 * which need to be assigned to four links, implying some
1197 * links must share PEs.
1199 * To achieve this we assign PEs such that NPUs linking the
1200 * same GPU get assigned the same PE.
1202 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1203 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1204 pe = &phb->ioda.pe_array[pe_num];
1208 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1210 * This device has the same peer GPU so should
1211 * be assigned the same PE as the existing
1214 dev_info(&npu_pdev->dev,
1215 "Associating to existing PE %x\n", pe_num);
1216 pci_dev_get(npu_pdev);
1217 npu_pdn = pci_get_pdn(npu_pdev);
1218 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1219 npu_pdn->pcidev = npu_pdev;
1220 npu_pdn->pe_number = pe_num;
1221 phb->ioda.pe_rmap[rid] = pe->pe_number;
1223 /* Map the PE to this link */
1224 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1226 OPAL_COMPARE_RID_DEVICE_NUMBER,
1227 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1229 WARN_ON(rc != OPAL_SUCCESS);
1237 * Could not find an existing PE so allocate a new
1240 return pnv_ioda_setup_dev_PE(npu_pdev);
1245 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1247 struct pci_dev *pdev;
1249 list_for_each_entry(pdev, &bus->devices, bus_list)
1250 pnv_ioda_setup_npu_PE(pdev);
1253 static void pnv_pci_ioda_setup_PEs(void)
1255 struct pci_controller *hose, *tmp;
1256 struct pnv_phb *phb;
1258 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1259 phb = hose->private_data;
1260 if (phb->type == PNV_PHB_NPU) {
1261 /* PE#0 is needed for error reporting */
1262 pnv_ioda_reserve_pe(phb, 0);
1263 pnv_ioda_setup_npu_PEs(hose->bus);
1264 if (phb->model == PNV_PHB_MODEL_NPU2)
1270 #ifdef CONFIG_PCI_IOV
1271 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1273 struct pci_bus *bus;
1274 struct pci_controller *hose;
1275 struct pnv_phb *phb;
1281 hose = pci_bus_to_host(bus);
1282 phb = hose->private_data;
1283 pdn = pci_get_pdn(pdev);
1285 if (pdn->m64_single_mode)
1290 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1291 for (j = 0; j < m64_bars; j++) {
1292 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1294 opal_pci_phb_mmio_enable(phb->opal_id,
1295 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1296 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1297 pdn->m64_map[j][i] = IODA_INVALID_M64;
1300 kfree(pdn->m64_map);
1304 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1306 struct pci_bus *bus;
1307 struct pci_controller *hose;
1308 struct pnv_phb *phb;
1311 struct resource *res;
1315 resource_size_t size, start;
1320 hose = pci_bus_to_host(bus);
1321 phb = hose->private_data;
1322 pdn = pci_get_pdn(pdev);
1323 total_vfs = pci_sriov_get_totalvfs(pdev);
1325 if (pdn->m64_single_mode)
1330 pdn->m64_map = kmalloc_array(m64_bars,
1331 sizeof(*pdn->m64_map),
1335 /* Initialize the m64_map to IODA_INVALID_M64 */
1336 for (i = 0; i < m64_bars ; i++)
1337 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1338 pdn->m64_map[i][j] = IODA_INVALID_M64;
1341 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1342 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1343 if (!res->flags || !res->parent)
1346 for (j = 0; j < m64_bars; j++) {
1348 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1349 phb->ioda.m64_bar_idx + 1, 0);
1351 if (win >= phb->ioda.m64_bar_idx + 1)
1353 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1355 pdn->m64_map[j][i] = win;
1357 if (pdn->m64_single_mode) {
1358 size = pci_iov_resource_size(pdev,
1359 PCI_IOV_RESOURCES + i);
1360 start = res->start + size * j;
1362 size = resource_size(res);
1366 /* Map the M64 here */
1367 if (pdn->m64_single_mode) {
1368 pe_num = pdn->pe_num_map[j];
1369 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1370 pe_num, OPAL_M64_WINDOW_TYPE,
1371 pdn->m64_map[j][i], 0);
1374 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1375 OPAL_M64_WINDOW_TYPE,
1382 if (rc != OPAL_SUCCESS) {
1383 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1388 if (pdn->m64_single_mode)
1389 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1390 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1392 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1393 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1395 if (rc != OPAL_SUCCESS) {
1396 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1405 pnv_pci_vf_release_m64(pdev, num_vfs);
1409 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1411 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1413 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1415 struct iommu_table *tbl;
1418 tbl = pe->table_group.tables[0];
1419 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1421 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1423 pnv_pci_ioda2_set_bypass(pe, false);
1424 if (pe->table_group.group) {
1425 iommu_group_put(pe->table_group.group);
1426 BUG_ON(pe->table_group.group);
1428 iommu_tce_table_put(tbl);
1431 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1433 struct pci_bus *bus;
1434 struct pci_controller *hose;
1435 struct pnv_phb *phb;
1436 struct pnv_ioda_pe *pe, *pe_n;
1440 hose = pci_bus_to_host(bus);
1441 phb = hose->private_data;
1442 pdn = pci_get_pdn(pdev);
1444 if (!pdev->is_physfn)
1447 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1448 if (pe->parent_dev != pdev)
1451 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1453 /* Remove from list */
1454 mutex_lock(&phb->ioda.pe_list_mutex);
1455 list_del(&pe->list);
1456 mutex_unlock(&phb->ioda.pe_list_mutex);
1458 pnv_ioda_deconfigure_pe(phb, pe);
1460 pnv_ioda_free_pe(pe);
1464 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1466 struct pci_bus *bus;
1467 struct pci_controller *hose;
1468 struct pnv_phb *phb;
1469 struct pnv_ioda_pe *pe;
1474 hose = pci_bus_to_host(bus);
1475 phb = hose->private_data;
1476 pdn = pci_get_pdn(pdev);
1477 num_vfs = pdn->num_vfs;
1479 /* Release VF PEs */
1480 pnv_ioda_release_vf_PE(pdev);
1482 if (phb->type == PNV_PHB_IODA2) {
1483 if (!pdn->m64_single_mode)
1484 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1486 /* Release M64 windows */
1487 pnv_pci_vf_release_m64(pdev, num_vfs);
1489 /* Release PE numbers */
1490 if (pdn->m64_single_mode) {
1491 for (i = 0; i < num_vfs; i++) {
1492 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1495 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1496 pnv_ioda_free_pe(pe);
1499 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1500 /* Releasing pe_num_map */
1501 kfree(pdn->pe_num_map);
1505 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1506 struct pnv_ioda_pe *pe);
1507 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1509 struct pci_bus *bus;
1510 struct pci_controller *hose;
1511 struct pnv_phb *phb;
1512 struct pnv_ioda_pe *pe;
1518 hose = pci_bus_to_host(bus);
1519 phb = hose->private_data;
1520 pdn = pci_get_pdn(pdev);
1522 if (!pdev->is_physfn)
1525 /* Reserve PE for each VF */
1526 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1527 if (pdn->m64_single_mode)
1528 pe_num = pdn->pe_num_map[vf_index];
1530 pe_num = *pdn->pe_num_map + vf_index;
1532 pe = &phb->ioda.pe_array[pe_num];
1533 pe->pe_number = pe_num;
1535 pe->flags = PNV_IODA_PE_VF;
1537 pe->parent_dev = pdev;
1538 pe->mve_number = -1;
1539 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1540 pci_iov_virtfn_devfn(pdev, vf_index);
1542 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1543 hose->global_number, pdev->bus->number,
1544 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1545 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1547 if (pnv_ioda_configure_pe(phb, pe)) {
1548 /* XXX What do we do here ? */
1549 pnv_ioda_free_pe(pe);
1554 /* Put PE to the list */
1555 mutex_lock(&phb->ioda.pe_list_mutex);
1556 list_add_tail(&pe->list, &phb->ioda.pe_list);
1557 mutex_unlock(&phb->ioda.pe_list_mutex);
1559 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1563 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1565 struct pci_bus *bus;
1566 struct pci_controller *hose;
1567 struct pnv_phb *phb;
1568 struct pnv_ioda_pe *pe;
1574 hose = pci_bus_to_host(bus);
1575 phb = hose->private_data;
1576 pdn = pci_get_pdn(pdev);
1578 if (phb->type == PNV_PHB_IODA2) {
1579 if (!pdn->vfs_expanded) {
1580 dev_info(&pdev->dev, "don't support this SRIOV device"
1581 " with non 64bit-prefetchable IOV BAR\n");
1586 * When M64 BARs functions in Single PE mode, the number of VFs
1587 * could be enabled must be less than the number of M64 BARs.
1589 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1590 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1594 /* Allocating pe_num_map */
1595 if (pdn->m64_single_mode)
1596 pdn->pe_num_map = kmalloc_array(num_vfs,
1597 sizeof(*pdn->pe_num_map),
1600 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1602 if (!pdn->pe_num_map)
1605 if (pdn->m64_single_mode)
1606 for (i = 0; i < num_vfs; i++)
1607 pdn->pe_num_map[i] = IODA_INVALID_PE;
1609 /* Calculate available PE for required VFs */
1610 if (pdn->m64_single_mode) {
1611 for (i = 0; i < num_vfs; i++) {
1612 pe = pnv_ioda_alloc_pe(phb);
1618 pdn->pe_num_map[i] = pe->pe_number;
1621 mutex_lock(&phb->ioda.pe_alloc_mutex);
1622 *pdn->pe_num_map = bitmap_find_next_zero_area(
1623 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1625 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1626 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1627 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1628 kfree(pdn->pe_num_map);
1631 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1632 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1634 pdn->num_vfs = num_vfs;
1636 /* Assign M64 window accordingly */
1637 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1639 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1644 * When using one M64 BAR to map one IOV BAR, we need to shift
1645 * the IOV BAR according to the PE# allocated to the VFs.
1646 * Otherwise, the PE# for the VF will conflict with others.
1648 if (!pdn->m64_single_mode) {
1649 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1656 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1661 if (pdn->m64_single_mode) {
1662 for (i = 0; i < num_vfs; i++) {
1663 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1666 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1667 pnv_ioda_free_pe(pe);
1670 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1672 /* Releasing pe_num_map */
1673 kfree(pdn->pe_num_map);
1678 int pcibios_sriov_disable(struct pci_dev *pdev)
1680 pnv_pci_sriov_disable(pdev);
1682 /* Release PCI data */
1683 remove_dev_pci_data(pdev);
1687 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1689 /* Allocate PCI data */
1690 add_dev_pci_data(pdev);
1692 return pnv_pci_sriov_enable(pdev, num_vfs);
1694 #endif /* CONFIG_PCI_IOV */
1696 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1698 struct pci_dn *pdn = pci_get_pdn(pdev);
1699 struct pnv_ioda_pe *pe;
1702 * The function can be called while the PE#
1703 * hasn't been assigned. Do nothing for the
1706 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1709 pe = &phb->ioda.pe_array[pdn->pe_number];
1710 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1711 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1712 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1714 * Note: iommu_add_device() will fail here as
1715 * for physical PE: the device is already added by now;
1716 * for virtual PE: sysfs entries are not ready yet and
1717 * tce_iommu_bus_notifier will add the device to a group later.
1721 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1723 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1724 struct pnv_phb *phb = hose->private_data;
1725 struct pci_dn *pdn = pci_get_pdn(pdev);
1726 struct pnv_ioda_pe *pe;
1728 bool bypass = false;
1730 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1733 pe = &phb->ioda.pe_array[pdn->pe_number];
1734 if (pe->tce_bypass_enabled) {
1735 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1736 bypass = (dma_mask >= top);
1740 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1741 set_dma_ops(&pdev->dev, &dma_direct_ops);
1743 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1744 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1746 *pdev->dev.dma_mask = dma_mask;
1748 /* Update peer npu devices */
1749 pnv_npu_try_dma_set_bypass(pdev, bypass);
1754 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1756 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1757 struct pnv_phb *phb = hose->private_data;
1758 struct pci_dn *pdn = pci_get_pdn(pdev);
1759 struct pnv_ioda_pe *pe;
1762 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1765 pe = &phb->ioda.pe_array[pdn->pe_number];
1766 if (!pe->tce_bypass_enabled)
1767 return __dma_get_required_mask(&pdev->dev);
1770 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1771 mask = 1ULL << (fls64(end) - 1);
1777 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1778 struct pci_bus *bus,
1781 struct pci_dev *dev;
1783 list_for_each_entry(dev, &bus->devices, bus_list) {
1784 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1785 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1787 iommu_add_device(&dev->dev);
1789 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1790 pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1795 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1798 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1799 (phb->regs + 0x210);
1802 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1803 unsigned long index, unsigned long npages, bool rm)
1805 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1806 &tbl->it_group_list, struct iommu_table_group_link,
1808 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1809 struct pnv_ioda_pe, table_group);
1810 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1811 unsigned long start, end, inc;
1813 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1814 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1817 /* p7ioc-style invalidation, 2 TCEs per write */
1818 start |= (1ull << 63);
1819 end |= (1ull << 63);
1821 end |= inc - 1; /* round up end to be different than start */
1823 mb(); /* Ensure above stores are visible */
1824 while (start <= end) {
1826 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1828 __raw_writeq(cpu_to_be64(start), invalidate);
1833 * The iommu layer will do another mb() for us on build()
1834 * and we don't care on free()
1838 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1839 long npages, unsigned long uaddr,
1840 enum dma_data_direction direction,
1841 unsigned long attrs)
1843 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1847 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1852 #ifdef CONFIG_IOMMU_API
1853 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1854 unsigned long *hpa, enum dma_data_direction *direction)
1856 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1859 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1864 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
1865 unsigned long *hpa, enum dma_data_direction *direction)
1867 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1870 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
1876 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1879 pnv_tce_free(tbl, index, npages);
1881 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1884 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1885 .set = pnv_ioda1_tce_build,
1886 #ifdef CONFIG_IOMMU_API
1887 .exchange = pnv_ioda1_tce_xchg,
1888 .exchange_rm = pnv_ioda1_tce_xchg_rm,
1890 .clear = pnv_ioda1_tce_free,
1894 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1895 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1896 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1898 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1900 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1901 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1903 mb(); /* Ensure previous TCE table stores are visible */
1905 __raw_rm_writeq(cpu_to_be64(val), invalidate);
1907 __raw_writeq(cpu_to_be64(val), invalidate);
1910 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1912 /* 01xb - invalidate TCEs that match the specified PE# */
1913 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1914 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1916 mb(); /* Ensure above stores are visible */
1917 __raw_writeq(cpu_to_be64(val), invalidate);
1920 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1921 unsigned shift, unsigned long index,
1922 unsigned long npages)
1924 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1925 unsigned long start, end, inc;
1927 /* We'll invalidate DMA address in PE scope */
1928 start = PHB3_TCE_KILL_INVAL_ONE;
1929 start |= (pe->pe_number & 0xFF);
1932 /* Figure out the start, end and step */
1933 start |= (index << shift);
1934 end |= ((index + npages - 1) << shift);
1935 inc = (0x1ull << shift);
1938 while (start <= end) {
1940 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1942 __raw_writeq(cpu_to_be64(start), invalidate);
1947 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1949 struct pnv_phb *phb = pe->phb;
1951 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1952 pnv_pci_phb3_tce_invalidate_pe(pe);
1954 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1955 pe->pe_number, 0, 0, 0);
1958 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1959 unsigned long index, unsigned long npages, bool rm)
1961 struct iommu_table_group_link *tgl;
1963 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
1964 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1965 struct pnv_ioda_pe, table_group);
1966 struct pnv_phb *phb = pe->phb;
1967 unsigned int shift = tbl->it_page_shift;
1970 * NVLink1 can use the TCE kill register directly as
1971 * it's the same as PHB3. NVLink2 is different and
1972 * should go via the OPAL call.
1974 if (phb->model == PNV_PHB_MODEL_NPU) {
1976 * The NVLink hardware does not support TCE kill
1977 * per TCE entry so we have to invalidate
1978 * the entire cache for it.
1980 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1983 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1984 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1987 opal_pci_tce_kill(phb->opal_id,
1988 OPAL_PCI_TCE_KILL_PAGES,
1989 pe->pe_number, 1u << shift,
1990 index << shift, npages);
1994 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1996 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
1997 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1999 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2002 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2003 long npages, unsigned long uaddr,
2004 enum dma_data_direction direction,
2005 unsigned long attrs)
2007 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2011 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2016 #ifdef CONFIG_IOMMU_API
2017 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2018 unsigned long *hpa, enum dma_data_direction *direction)
2020 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2023 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2028 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2029 unsigned long *hpa, enum dma_data_direction *direction)
2031 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2034 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2040 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2043 pnv_tce_free(tbl, index, npages);
2045 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2048 static void pnv_ioda2_table_free(struct iommu_table *tbl)
2050 pnv_pci_ioda2_table_free_pages(tbl);
2053 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2054 .set = pnv_ioda2_tce_build,
2055 #ifdef CONFIG_IOMMU_API
2056 .exchange = pnv_ioda2_tce_xchg,
2057 .exchange_rm = pnv_ioda2_tce_xchg_rm,
2059 .clear = pnv_ioda2_tce_free,
2061 .free = pnv_ioda2_table_free,
2064 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2066 unsigned int *weight = (unsigned int *)data;
2068 /* This is quite simplistic. The "base" weight of a device
2069 * is 10. 0 means no DMA is to be accounted for it.
2071 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2074 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2075 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2076 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2078 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2086 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2088 unsigned int weight = 0;
2090 /* SRIOV VF has same DMA32 weight as its PF */
2091 #ifdef CONFIG_PCI_IOV
2092 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2093 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2098 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2099 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2100 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2101 struct pci_dev *pdev;
2103 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2104 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2105 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2106 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2112 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2113 struct pnv_ioda_pe *pe)
2116 struct page *tce_mem = NULL;
2117 struct iommu_table *tbl;
2118 unsigned int weight, total_weight = 0;
2119 unsigned int tce32_segsz, base, segs, avail, i;
2123 /* XXX FIXME: Handle 64-bit only DMA devices */
2124 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2125 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2126 weight = pnv_pci_ioda_pe_dma_weight(pe);
2130 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2132 segs = (weight * phb->ioda.dma32_count) / total_weight;
2137 * Allocate contiguous DMA32 segments. We begin with the expected
2138 * number of segments. With one more attempt, the number of DMA32
2139 * segments to be allocated is decreased by one until one segment
2140 * is allocated successfully.
2143 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2144 for (avail = 0, i = base; i < base + segs; i++) {
2145 if (phb->ioda.dma32_segmap[i] ==
2156 pe_warn(pe, "No available DMA32 segments\n");
2161 tbl = pnv_pci_table_alloc(phb->hose->node);
2165 iommu_register_group(&pe->table_group, phb->hose->global_number,
2167 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2169 /* Grab a 32-bit TCE table */
2170 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2171 weight, total_weight, base, segs);
2172 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2173 base * PNV_IODA1_DMA32_SEGSIZE,
2174 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2176 /* XXX Currently, we allocate one big contiguous table for the
2177 * TCEs. We only really need one chunk per 256M of TCE space
2178 * (ie per segment) but that's an optimization for later, it
2179 * requires some added smarts with our get/put_tce implementation
2181 * Each TCE page is 4KB in size and each TCE entry occupies 8
2184 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2185 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2186 get_order(tce32_segsz * segs));
2188 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2191 addr = page_address(tce_mem);
2192 memset(addr, 0, tce32_segsz * segs);
2195 for (i = 0; i < segs; i++) {
2196 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2199 __pa(addr) + tce32_segsz * i,
2200 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2202 pe_err(pe, " Failed to configure 32-bit TCE table,"
2208 /* Setup DMA32 segment mapping */
2209 for (i = base; i < base + segs; i++)
2210 phb->ioda.dma32_segmap[i] = pe->pe_number;
2212 /* Setup linux iommu table */
2213 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2214 base * PNV_IODA1_DMA32_SEGSIZE,
2215 IOMMU_PAGE_SHIFT_4K);
2217 tbl->it_ops = &pnv_ioda1_iommu_ops;
2218 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2219 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2220 iommu_init_table(tbl, phb->hose->node);
2222 if (pe->flags & PNV_IODA_PE_DEV) {
2224 * Setting table base here only for carrying iommu_group
2225 * further down to let iommu_add_device() do the job.
2226 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2228 set_iommu_table_base(&pe->pdev->dev, tbl);
2229 iommu_add_device(&pe->pdev->dev);
2230 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2231 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2235 /* XXX Failure: Try to fallback to 64-bit only ? */
2237 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2239 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2240 iommu_tce_table_put(tbl);
2244 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2245 int num, struct iommu_table *tbl)
2247 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2249 struct pnv_phb *phb = pe->phb;
2251 const unsigned long size = tbl->it_indirect_levels ?
2252 tbl->it_level_size : tbl->it_size;
2253 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2254 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2256 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2257 start_addr, start_addr + win_size - 1,
2258 IOMMU_PAGE_SIZE(tbl));
2261 * Map TCE table through TVT. The TVE index is the PE number
2262 * shifted by 1 bit for 32-bits DMA space.
2264 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2266 (pe->pe_number << 1) + num,
2267 tbl->it_indirect_levels + 1,
2270 IOMMU_PAGE_SIZE(tbl));
2272 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2276 pnv_pci_link_table_and_group(phb->hose->node, num,
2277 tbl, &pe->table_group);
2278 pnv_pci_ioda2_tce_invalidate_pe(pe);
2283 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2285 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2288 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2290 phys_addr_t top = memblock_end_of_DRAM();
2292 top = roundup_pow_of_two(top);
2293 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2296 pe->tce_bypass_base,
2299 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2302 pe->tce_bypass_base,
2306 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2308 pe->tce_bypass_enabled = enable;
2311 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2312 __u32 page_shift, __u64 window_size, __u32 levels,
2313 struct iommu_table *tbl);
2315 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2316 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2317 struct iommu_table **ptbl)
2319 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2321 int nid = pe->phb->hose->node;
2322 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2324 struct iommu_table *tbl;
2326 tbl = pnv_pci_table_alloc(nid);
2330 tbl->it_ops = &pnv_ioda2_iommu_ops;
2332 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2333 bus_offset, page_shift, window_size,
2336 iommu_tce_table_put(tbl);
2345 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2347 struct iommu_table *tbl = NULL;
2351 * crashkernel= specifies the kdump kernel's maximum memory at
2352 * some offset and there is no guaranteed the result is a power
2353 * of 2, which will cause errors later.
2355 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2358 * In memory constrained environments, e.g. kdump kernel, the
2359 * DMA window can be larger than available memory, which will
2360 * cause errors later.
2362 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2364 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2365 IOMMU_PAGE_SHIFT_4K,
2367 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2369 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2374 iommu_init_table(tbl, pe->phb->hose->node);
2376 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2378 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2380 iommu_tce_table_put(tbl);
2384 if (!pnv_iommu_bypass_disabled)
2385 pnv_pci_ioda2_set_bypass(pe, true);
2388 * Setting table base here only for carrying iommu_group
2389 * further down to let iommu_add_device() do the job.
2390 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2392 if (pe->flags & PNV_IODA_PE_DEV)
2393 set_iommu_table_base(&pe->pdev->dev, tbl);
2398 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2399 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2402 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2404 struct pnv_phb *phb = pe->phb;
2407 pe_info(pe, "Removing DMA window #%d\n", num);
2409 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2410 (pe->pe_number << 1) + num,
2411 0/* levels */, 0/* table address */,
2412 0/* table size */, 0/* page size */);
2414 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2416 pnv_pci_ioda2_tce_invalidate_pe(pe);
2418 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2424 #ifdef CONFIG_IOMMU_API
2425 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2426 __u64 window_size, __u32 levels)
2428 unsigned long bytes = 0;
2429 const unsigned window_shift = ilog2(window_size);
2430 unsigned entries_shift = window_shift - page_shift;
2431 unsigned table_shift = entries_shift + 3;
2432 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2433 unsigned long direct_table_size;
2435 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2436 (window_size > memory_hotplug_max()) ||
2437 !is_power_of_2(window_size))
2440 /* Calculate a direct table size from window_size and levels */
2441 entries_shift = (entries_shift + levels - 1) / levels;
2442 table_shift = entries_shift + 3;
2443 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2444 direct_table_size = 1UL << table_shift;
2446 for ( ; levels; --levels) {
2447 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2449 tce_table_size /= direct_table_size;
2450 tce_table_size <<= 3;
2451 tce_table_size = max_t(unsigned long,
2452 tce_table_size, direct_table_size);
2458 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2460 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2462 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2463 struct iommu_table *tbl = pe->table_group.tables[0];
2465 pnv_pci_ioda2_set_bypass(pe, false);
2466 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2468 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2469 iommu_tce_table_put(tbl);
2472 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2474 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2477 pnv_pci_ioda2_setup_default_config(pe);
2479 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2482 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2483 .get_table_size = pnv_pci_ioda2_get_table_size,
2484 .create_table = pnv_pci_ioda2_create_table,
2485 .set_window = pnv_pci_ioda2_set_window,
2486 .unset_window = pnv_pci_ioda2_unset_window,
2487 .take_ownership = pnv_ioda2_take_ownership,
2488 .release_ownership = pnv_ioda2_release_ownership,
2491 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2493 struct pci_controller *hose;
2494 struct pnv_phb *phb;
2495 struct pnv_ioda_pe **ptmppe = opaque;
2496 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2497 struct pci_dn *pdn = pci_get_pdn(pdev);
2499 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2502 hose = pci_bus_to_host(pdev->bus);
2503 phb = hose->private_data;
2504 if (phb->type != PNV_PHB_NPU)
2507 *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2513 * This returns PE of associated NPU.
2514 * This assumes that NPU is in the same IOMMU group with GPU and there is
2517 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2518 struct iommu_table_group *table_group)
2520 struct pnv_ioda_pe *npe = NULL;
2521 int ret = iommu_group_for_each_dev(table_group->group, &npe,
2522 gpe_table_group_to_npe_cb);
2524 BUG_ON(!ret || !npe);
2529 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2530 int num, struct iommu_table *tbl)
2532 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2537 ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2539 pnv_pci_ioda2_unset_window(table_group, num);
2544 static long pnv_pci_ioda2_npu_unset_window(
2545 struct iommu_table_group *table_group,
2548 long ret = pnv_pci_ioda2_unset_window(table_group, num);
2553 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2556 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2559 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2560 * the iommu_table if 32bit DMA is enabled.
2562 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2563 pnv_ioda2_take_ownership(table_group);
2566 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2567 .get_table_size = pnv_pci_ioda2_get_table_size,
2568 .create_table = pnv_pci_ioda2_create_table,
2569 .set_window = pnv_pci_ioda2_npu_set_window,
2570 .unset_window = pnv_pci_ioda2_npu_unset_window,
2571 .take_ownership = pnv_ioda2_npu_take_ownership,
2572 .release_ownership = pnv_ioda2_release_ownership,
2575 static void pnv_pci_ioda_setup_iommu_api(void)
2577 struct pci_controller *hose, *tmp;
2578 struct pnv_phb *phb;
2579 struct pnv_ioda_pe *pe, *gpe;
2582 * Now we have all PHBs discovered, time to add NPU devices to
2583 * the corresponding IOMMU groups.
2585 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2586 phb = hose->private_data;
2588 if (phb->type != PNV_PHB_NPU)
2591 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2592 gpe = pnv_pci_npu_setup_iommu(pe);
2594 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2598 #else /* !CONFIG_IOMMU_API */
2599 static void pnv_pci_ioda_setup_iommu_api(void) { };
2602 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2603 unsigned levels, unsigned long limit,
2604 unsigned long *current_offset, unsigned long *total_allocated)
2606 struct page *tce_mem = NULL;
2608 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2609 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2610 unsigned entries = 1UL << (shift - 3);
2613 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2615 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2618 addr = page_address(tce_mem);
2619 memset(addr, 0, allocated);
2620 *total_allocated += allocated;
2624 *current_offset += allocated;
2628 for (i = 0; i < entries; ++i) {
2629 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2630 levels, limit, current_offset, total_allocated);
2634 addr[i] = cpu_to_be64(__pa(tmp) |
2635 TCE_PCI_READ | TCE_PCI_WRITE);
2637 if (*current_offset >= limit)
2644 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2645 unsigned long size, unsigned level);
2647 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2648 __u32 page_shift, __u64 window_size, __u32 levels,
2649 struct iommu_table *tbl)
2652 unsigned long offset = 0, level_shift, total_allocated = 0;
2653 const unsigned window_shift = ilog2(window_size);
2654 unsigned entries_shift = window_shift - page_shift;
2655 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2656 const unsigned long tce_table_size = 1UL << table_shift;
2658 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2661 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2664 /* Adjust direct table size from window_size and levels */
2665 entries_shift = (entries_shift + levels - 1) / levels;
2666 level_shift = entries_shift + 3;
2667 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2669 if ((level_shift - 3) * levels + page_shift >= 60)
2672 /* Allocate TCE table */
2673 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2674 levels, tce_table_size, &offset, &total_allocated);
2676 /* addr==NULL means that the first level allocation failed */
2681 * First level was allocated but some lower level failed as
2682 * we did not allocate as much as we wanted,
2683 * release partially allocated table.
2685 if (offset < tce_table_size) {
2686 pnv_pci_ioda2_table_do_free_pages(addr,
2687 1ULL << (level_shift - 3), levels - 1);
2691 /* Setup linux iommu table */
2692 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2694 tbl->it_level_size = 1ULL << (level_shift - 3);
2695 tbl->it_indirect_levels = levels - 1;
2696 tbl->it_allocated_size = total_allocated;
2698 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2699 window_size, tce_table_size, bus_offset);
2704 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2705 unsigned long size, unsigned level)
2707 const unsigned long addr_ul = (unsigned long) addr &
2708 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2712 u64 *tmp = (u64 *) addr_ul;
2714 for (i = 0; i < size; ++i) {
2715 unsigned long hpa = be64_to_cpu(tmp[i]);
2717 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2720 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2725 free_pages(addr_ul, get_order(size << 3));
2728 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2730 const unsigned long size = tbl->it_indirect_levels ?
2731 tbl->it_level_size : tbl->it_size;
2736 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2737 tbl->it_indirect_levels);
2740 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2741 struct pnv_ioda_pe *pe)
2745 if (!pnv_pci_ioda_pe_dma_weight(pe))
2748 /* TVE #1 is selected by PCI address bit 59 */
2749 pe->tce_bypass_base = 1ull << 59;
2751 iommu_register_group(&pe->table_group, phb->hose->global_number,
2754 /* The PE will reserve all possible 32-bits space */
2755 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2756 phb->ioda.m32_pci_base);
2758 /* Setup linux iommu table */
2759 pe->table_group.tce32_start = 0;
2760 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2761 pe->table_group.max_dynamic_windows_supported =
2762 IOMMU_TABLE_GROUP_MAX_TABLES;
2763 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2764 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2765 #ifdef CONFIG_IOMMU_API
2766 pe->table_group.ops = &pnv_pci_ioda2_ops;
2769 rc = pnv_pci_ioda2_setup_default_config(pe);
2773 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2774 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2777 #ifdef CONFIG_PCI_MSI
2778 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2780 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2783 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2786 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2789 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2790 struct irq_chip *chip = irq_data_get_irq_chip(d);
2792 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2799 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2801 struct irq_data *idata;
2802 struct irq_chip *ichip;
2804 /* The MSI EOI OPAL call is only needed on PHB3 */
2805 if (phb->model != PNV_PHB_MODEL_PHB3)
2808 if (!phb->ioda.irq_chip_init) {
2810 * First time we setup an MSI IRQ, we need to setup the
2811 * corresponding IRQ chip to route correctly.
2813 idata = irq_get_irq_data(virq);
2814 ichip = irq_data_get_irq_chip(idata);
2815 phb->ioda.irq_chip_init = 1;
2816 phb->ioda.irq_chip = *ichip;
2817 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2819 irq_set_chip(virq, &phb->ioda.irq_chip);
2823 * Returns true iff chip is something that we could call
2824 * pnv_opal_pci_msi_eoi for.
2826 bool is_pnv_opal_msi(struct irq_chip *chip)
2828 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2830 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2832 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2833 unsigned int hwirq, unsigned int virq,
2834 unsigned int is_64, struct msi_msg *msg)
2836 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2837 unsigned int xive_num = hwirq - phb->msi_base;
2841 /* No PE assigned ? bail out ... no MSI for you ! */
2845 /* Check if we have an MVE */
2846 if (pe->mve_number < 0)
2849 /* Force 32-bit MSI on some broken devices */
2850 if (dev->no_64bit_msi)
2853 /* Assign XIVE to PE */
2854 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2856 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2857 pci_name(dev), rc, xive_num);
2864 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2867 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2871 msg->address_hi = be64_to_cpu(addr64) >> 32;
2872 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2876 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2879 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2883 msg->address_hi = 0;
2884 msg->address_lo = be32_to_cpu(addr32);
2886 msg->data = be32_to_cpu(data);
2888 pnv_set_msi_irq_chip(phb, virq);
2890 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2891 " address=%x_%08x data=%x PE# %x\n",
2892 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2893 msg->address_hi, msg->address_lo, data, pe->pe_number);
2898 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2901 const __be32 *prop = of_get_property(phb->hose->dn,
2902 "ibm,opal-msi-ranges", NULL);
2905 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2910 phb->msi_base = be32_to_cpup(prop);
2911 count = be32_to_cpup(prop + 1);
2912 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2913 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2914 phb->hose->global_number);
2918 phb->msi_setup = pnv_pci_ioda_msi_setup;
2919 phb->msi32_support = 1;
2920 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2921 count, phb->msi_base);
2924 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2925 #endif /* CONFIG_PCI_MSI */
2927 #ifdef CONFIG_PCI_IOV
2928 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2930 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2931 struct pnv_phb *phb = hose->private_data;
2932 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2933 struct resource *res;
2935 resource_size_t size, total_vf_bar_sz;
2939 if (!pdev->is_physfn || pdev->is_added)
2942 pdn = pci_get_pdn(pdev);
2943 pdn->vfs_expanded = 0;
2944 pdn->m64_single_mode = false;
2946 total_vfs = pci_sriov_get_totalvfs(pdev);
2947 mul = phb->ioda.total_pe_num;
2948 total_vf_bar_sz = 0;
2950 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2951 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2952 if (!res->flags || res->parent)
2954 if (!pnv_pci_is_m64_flags(res->flags)) {
2955 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2956 " non M64 VF BAR%d: %pR. \n",
2961 total_vf_bar_sz += pci_iov_resource_size(pdev,
2962 i + PCI_IOV_RESOURCES);
2965 * If bigger than quarter of M64 segment size, just round up
2968 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2969 * with other devices, IOV BAR size is expanded to be
2970 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2971 * segment size , the expanded size would equal to half of the
2972 * whole M64 space size, which will exhaust the M64 Space and
2973 * limit the system flexibility. This is a design decision to
2974 * set the boundary to quarter of the M64 segment size.
2976 if (total_vf_bar_sz > gate) {
2977 mul = roundup_pow_of_two(total_vfs);
2978 dev_info(&pdev->dev,
2979 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2980 total_vf_bar_sz, gate, mul);
2981 pdn->m64_single_mode = true;
2986 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2987 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2988 if (!res->flags || res->parent)
2991 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2993 * On PHB3, the minimum size alignment of M64 BAR in single
2996 if (pdn->m64_single_mode && (size < SZ_32M))
2998 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2999 res->end = res->start + size * mul - 1;
3000 dev_dbg(&pdev->dev, " %pR\n", res);
3001 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3004 pdn->vfs_expanded = mul;
3009 /* To save MMIO space, IOV BAR is truncated. */
3010 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3011 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3013 res->end = res->start - 1;
3016 #endif /* CONFIG_PCI_IOV */
3018 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3019 struct resource *res)
3021 struct pnv_phb *phb = pe->phb;
3022 struct pci_bus_region region;
3026 if (!res || !res->flags || res->start > res->end)
3029 if (res->flags & IORESOURCE_IO) {
3030 region.start = res->start - phb->ioda.io_pci_base;
3031 region.end = res->end - phb->ioda.io_pci_base;
3032 index = region.start / phb->ioda.io_segsize;
3034 while (index < phb->ioda.total_pe_num &&
3035 region.start <= region.end) {
3036 phb->ioda.io_segmap[index] = pe->pe_number;
3037 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3038 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3039 if (rc != OPAL_SUCCESS) {
3040 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3041 __func__, rc, index, pe->pe_number);
3045 region.start += phb->ioda.io_segsize;
3048 } else if ((res->flags & IORESOURCE_MEM) &&
3049 !pnv_pci_is_m64(phb, res)) {
3050 region.start = res->start -
3051 phb->hose->mem_offset[0] -
3052 phb->ioda.m32_pci_base;
3053 region.end = res->end -
3054 phb->hose->mem_offset[0] -
3055 phb->ioda.m32_pci_base;
3056 index = region.start / phb->ioda.m32_segsize;
3058 while (index < phb->ioda.total_pe_num &&
3059 region.start <= region.end) {
3060 phb->ioda.m32_segmap[index] = pe->pe_number;
3061 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3062 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3063 if (rc != OPAL_SUCCESS) {
3064 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3065 __func__, rc, index, pe->pe_number);
3069 region.start += phb->ioda.m32_segsize;
3076 * This function is supposed to be called on basis of PE from top
3077 * to bottom style. So the the I/O or MMIO segment assigned to
3078 * parent PE could be overridden by its child PEs if necessary.
3080 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3082 struct pci_dev *pdev;
3086 * NOTE: We only care PCI bus based PE for now. For PCI
3087 * device based PE, for example SRIOV sensitive VF should
3088 * be figured out later.
3090 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3092 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3093 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3094 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3097 * If the PE contains all subordinate PCI buses, the
3098 * windows of the child bridges should be mapped to
3101 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3103 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3104 pnv_ioda_setup_pe_res(pe,
3105 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3109 #ifdef CONFIG_DEBUG_FS
3110 static int pnv_pci_diag_data_set(void *data, u64 val)
3112 struct pci_controller *hose;
3113 struct pnv_phb *phb;
3119 hose = (struct pci_controller *)data;
3120 if (!hose || !hose->private_data)
3123 phb = hose->private_data;
3125 /* Retrieve the diag data from firmware */
3126 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
3127 PNV_PCI_DIAG_BUF_SIZE);
3128 if (ret != OPAL_SUCCESS)
3131 /* Print the diag data to the kernel log */
3132 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
3136 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3137 pnv_pci_diag_data_set, "%llu\n");
3139 #endif /* CONFIG_DEBUG_FS */
3141 static void pnv_pci_ioda_create_dbgfs(void)
3143 #ifdef CONFIG_DEBUG_FS
3144 struct pci_controller *hose, *tmp;
3145 struct pnv_phb *phb;
3148 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3149 phb = hose->private_data;
3151 /* Notify initialization of PHB done */
3152 phb->initialized = 1;
3154 sprintf(name, "PCI%04x", hose->global_number);
3155 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3157 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3158 __func__, hose->global_number);
3162 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3163 &pnv_pci_diag_data_fops);
3165 #endif /* CONFIG_DEBUG_FS */
3168 static void pnv_pci_ioda_fixup(void)
3170 pnv_pci_ioda_setup_PEs();
3171 pnv_pci_ioda_setup_iommu_api();
3172 pnv_pci_ioda_create_dbgfs();
3176 eeh_addr_cache_build();
3181 * Returns the alignment for I/O or memory windows for P2P
3182 * bridges. That actually depends on how PEs are segmented.
3183 * For now, we return I/O or M32 segment size for PE sensitive
3184 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3185 * 1MiB for memory) will be returned.
3187 * The current PCI bus might be put into one PE, which was
3188 * create against the parent PCI bridge. For that case, we
3189 * needn't enlarge the alignment so that we can save some
3192 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3195 struct pci_dev *bridge;
3196 struct pci_controller *hose = pci_bus_to_host(bus);
3197 struct pnv_phb *phb = hose->private_data;
3198 int num_pci_bridges = 0;
3202 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3204 if (num_pci_bridges >= 2)
3208 bridge = bridge->bus->self;
3212 * We fall back to M32 if M64 isn't supported. We enforce the M64
3213 * alignment for any 64-bit resource, PCIe doesn't care and
3214 * bridges only do 64-bit prefetchable anyway.
3216 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3217 return phb->ioda.m64_segsize;
3218 if (type & IORESOURCE_MEM)
3219 return phb->ioda.m32_segsize;
3221 return phb->ioda.io_segsize;
3225 * We are updating root port or the upstream port of the
3226 * bridge behind the root port with PHB's windows in order
3227 * to accommodate the changes on required resources during
3228 * PCI (slot) hotplug, which is connected to either root
3229 * port or the downstream ports of PCIe switch behind the
3232 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3235 struct pci_controller *hose = pci_bus_to_host(bus);
3236 struct pnv_phb *phb = hose->private_data;
3237 struct pci_dev *bridge = bus->self;
3238 struct resource *r, *w;
3239 bool msi_region = false;
3242 /* Check if we need apply fixup to the bridge's windows */
3243 if (!pci_is_root_bus(bridge->bus) &&
3244 !pci_is_root_bus(bridge->bus->self->bus))
3247 /* Fixup the resources */
3248 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3249 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3250 if (!r->flags || !r->parent)
3254 if (r->flags & type & IORESOURCE_IO)
3255 w = &hose->io_resource;
3256 else if (pnv_pci_is_m64(phb, r) &&
3257 (type & IORESOURCE_PREFETCH) &&
3258 phb->ioda.m64_segsize)
3259 w = &hose->mem_resources[1];
3260 else if (r->flags & type & IORESOURCE_MEM) {
3261 w = &hose->mem_resources[0];
3265 r->start = w->start;
3268 /* The 64KB 32-bits MSI region shouldn't be included in
3269 * the 32-bits bridge window. Otherwise, we can see strange
3270 * issues. One of them is EEH error observed on Garrison.
3272 * Exclude top 1MB region which is the minimal alignment of
3273 * 32-bits bridge window.
3282 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3284 struct pci_controller *hose = pci_bus_to_host(bus);
3285 struct pnv_phb *phb = hose->private_data;
3286 struct pci_dev *bridge = bus->self;
3287 struct pnv_ioda_pe *pe;
3288 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3290 /* Extend bridge's windows if necessary */
3291 pnv_pci_fixup_bridge_resources(bus, type);
3293 /* The PE for root bus should be realized before any one else */
3294 if (!phb->ioda.root_pe_populated) {
3295 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3297 phb->ioda.root_pe_idx = pe->pe_number;
3298 phb->ioda.root_pe_populated = true;
3302 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3303 if (list_empty(&bus->devices))
3306 /* Reserve PEs according to used M64 resources */
3307 if (phb->reserve_m64_pe)
3308 phb->reserve_m64_pe(bus, NULL, all);
3311 * Assign PE. We might run here because of partial hotplug.
3312 * For the case, we just pick up the existing PE and should
3313 * not allocate resources again.
3315 pe = pnv_ioda_setup_bus_PE(bus, all);
3319 pnv_ioda_setup_pe_seg(pe);
3320 switch (phb->type) {
3322 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3325 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3328 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3329 __func__, phb->hose->global_number, phb->type);
3333 static resource_size_t pnv_pci_default_alignment(void)
3338 #ifdef CONFIG_PCI_IOV
3339 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3342 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3343 struct pnv_phb *phb = hose->private_data;
3344 struct pci_dn *pdn = pci_get_pdn(pdev);
3345 resource_size_t align;
3348 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3349 * SR-IOV. While from hardware perspective, the range mapped by M64
3350 * BAR should be size aligned.
3352 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3353 * powernv-specific hardware restriction is gone. But if just use the
3354 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3355 * in one segment of M64 #15, which introduces the PE conflict between
3356 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3359 * This function returns the total IOV BAR size if M64 BAR is in
3360 * Shared PE mode or just VF BAR size if not.
3361 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3362 * M64 segment size if IOV BAR size is less.
3364 align = pci_iov_resource_size(pdev, resno);
3365 if (!pdn->vfs_expanded)
3367 if (pdn->m64_single_mode)
3368 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3370 return pdn->vfs_expanded * align;
3372 #endif /* CONFIG_PCI_IOV */
3374 /* Prevent enabling devices for which we couldn't properly
3377 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3379 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3380 struct pnv_phb *phb = hose->private_data;
3383 /* The function is probably called while the PEs have
3384 * not be created yet. For example, resource reassignment
3385 * during PCI probe period. We just skip the check if
3388 if (!phb->initialized)
3391 pdn = pci_get_pdn(dev);
3392 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3398 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3401 struct pnv_ioda_pe *pe = container_of(table_group,
3402 struct pnv_ioda_pe, table_group);
3403 struct pnv_phb *phb = pe->phb;
3407 pe_info(pe, "Removing DMA window #%d\n", num);
3408 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3409 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3412 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3413 idx, 0, 0ul, 0ul, 0ul);
3414 if (rc != OPAL_SUCCESS) {
3415 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3420 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3423 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3424 return OPAL_SUCCESS;
3427 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3429 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3430 struct iommu_table *tbl = pe->table_group.tables[0];
3436 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3437 if (rc != OPAL_SUCCESS)
3440 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3441 if (pe->table_group.group) {
3442 iommu_group_put(pe->table_group.group);
3443 WARN_ON(pe->table_group.group);
3446 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3447 iommu_tce_table_put(tbl);
3450 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3452 struct iommu_table *tbl = pe->table_group.tables[0];
3453 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3454 #ifdef CONFIG_IOMMU_API
3461 #ifdef CONFIG_IOMMU_API
3462 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3464 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3467 pnv_pci_ioda2_set_bypass(pe, false);
3468 if (pe->table_group.group) {
3469 iommu_group_put(pe->table_group.group);
3470 WARN_ON(pe->table_group.group);
3473 pnv_pci_ioda2_table_free_pages(tbl);
3474 iommu_tce_table_put(tbl);
3477 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3481 struct pnv_phb *phb = pe->phb;
3485 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3486 if (map[idx] != pe->pe_number)
3489 if (win == OPAL_M64_WINDOW_TYPE)
3490 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3491 phb->ioda.reserved_pe_idx, win,
3492 idx / PNV_IODA1_M64_SEGS,
3493 idx % PNV_IODA1_M64_SEGS);
3495 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3496 phb->ioda.reserved_pe_idx, win, 0, idx);
3498 if (rc != OPAL_SUCCESS)
3499 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3502 map[idx] = IODA_INVALID_PE;
3506 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3508 struct pnv_phb *phb = pe->phb;
3510 if (phb->type == PNV_PHB_IODA1) {
3511 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3512 phb->ioda.io_segmap);
3513 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3514 phb->ioda.m32_segmap);
3515 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3516 phb->ioda.m64_segmap);
3517 } else if (phb->type == PNV_PHB_IODA2) {
3518 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3519 phb->ioda.m32_segmap);
3523 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3525 struct pnv_phb *phb = pe->phb;
3526 struct pnv_ioda_pe *slave, *tmp;
3528 list_del(&pe->list);
3529 switch (phb->type) {
3531 pnv_pci_ioda1_release_pe_dma(pe);
3534 pnv_pci_ioda2_release_pe_dma(pe);
3540 pnv_ioda_release_pe_seg(pe);
3541 pnv_ioda_deconfigure_pe(pe->phb, pe);
3543 /* Release slave PEs in the compound PE */
3544 if (pe->flags & PNV_IODA_PE_MASTER) {
3545 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3546 list_del(&slave->list);
3547 pnv_ioda_free_pe(slave);
3552 * The PE for root bus can be removed because of hotplug in EEH
3553 * recovery for fenced PHB error. We need to mark the PE dead so
3554 * that it can be populated again in PCI hot add path. The PE
3555 * shouldn't be destroyed as it's the global reserved resource.
3557 if (phb->ioda.root_pe_populated &&
3558 phb->ioda.root_pe_idx == pe->pe_number)
3559 phb->ioda.root_pe_populated = false;
3561 pnv_ioda_free_pe(pe);
3564 static void pnv_pci_release_device(struct pci_dev *pdev)
3566 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3567 struct pnv_phb *phb = hose->private_data;
3568 struct pci_dn *pdn = pci_get_pdn(pdev);
3569 struct pnv_ioda_pe *pe;
3571 if (pdev->is_virtfn)
3574 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3578 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3579 * isn't removed and added afterwards in this scenario. We should
3580 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3581 * device count is decreased on removing devices while failing to
3582 * be increased on adding devices. It leads to unbalanced PE's device
3583 * count and eventually make normal PCI hotplug path broken.
3585 pe = &phb->ioda.pe_array[pdn->pe_number];
3586 pdn->pe_number = IODA_INVALID_PE;
3588 WARN_ON(--pe->device_count < 0);
3589 if (pe->device_count == 0)
3590 pnv_ioda_release_pe(pe);
3593 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3595 struct pnv_phb *phb = hose->private_data;
3597 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3601 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3602 .dma_dev_setup = pnv_pci_dma_dev_setup,
3603 .dma_bus_setup = pnv_pci_dma_bus_setup,
3604 #ifdef CONFIG_PCI_MSI
3605 .setup_msi_irqs = pnv_setup_msi_irqs,
3606 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3608 .enable_device_hook = pnv_pci_enable_device_hook,
3609 .release_device = pnv_pci_release_device,
3610 .window_alignment = pnv_pci_window_alignment,
3611 .setup_bridge = pnv_pci_setup_bridge,
3612 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3613 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3614 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3615 .shutdown = pnv_pci_ioda_shutdown,
3618 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3620 dev_err_once(&npdev->dev,
3621 "%s operation unsupported for NVLink devices\n",
3626 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3627 .dma_dev_setup = pnv_pci_dma_dev_setup,
3628 #ifdef CONFIG_PCI_MSI
3629 .setup_msi_irqs = pnv_setup_msi_irqs,
3630 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3632 .enable_device_hook = pnv_pci_enable_device_hook,
3633 .window_alignment = pnv_pci_window_alignment,
3634 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3635 .dma_set_mask = pnv_npu_dma_set_mask,
3636 .shutdown = pnv_pci_ioda_shutdown,
3639 #ifdef CONFIG_CXL_BASE
3640 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3641 .dma_dev_setup = pnv_pci_dma_dev_setup,
3642 .dma_bus_setup = pnv_pci_dma_bus_setup,
3643 #ifdef CONFIG_PCI_MSI
3644 .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs,
3645 .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs,
3647 .enable_device_hook = pnv_cxl_enable_device_hook,
3648 .disable_device = pnv_cxl_disable_device,
3649 .release_device = pnv_pci_release_device,
3650 .window_alignment = pnv_pci_window_alignment,
3651 .setup_bridge = pnv_pci_setup_bridge,
3652 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3653 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3654 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3655 .shutdown = pnv_pci_ioda_shutdown,
3659 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3660 u64 hub_id, int ioda_type)
3662 struct pci_controller *hose;
3663 struct pnv_phb *phb;
3664 unsigned long size, m64map_off, m32map_off, pemap_off;
3665 unsigned long iomap_off = 0, dma32map_off = 0;
3667 const __be64 *prop64;
3668 const __be32 *prop32;
3675 if (!of_device_is_available(np))
3678 pr_info("Initializing %s PHB (%s)\n",
3679 pnv_phb_names[ioda_type], of_node_full_name(np));
3681 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3683 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3686 phb_id = be64_to_cpup(prop64);
3687 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3689 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3691 /* Allocate PCI controller */
3692 phb->hose = hose = pcibios_alloc_controller(np);
3694 pr_err(" Can't allocate PCI controller for %s\n",
3696 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3700 spin_lock_init(&phb->lock);
3701 prop32 = of_get_property(np, "bus-range", &len);
3702 if (prop32 && len == 8) {
3703 hose->first_busno = be32_to_cpu(prop32[0]);
3704 hose->last_busno = be32_to_cpu(prop32[1]);
3706 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3707 hose->first_busno = 0;
3708 hose->last_busno = 0xff;
3710 hose->private_data = phb;
3711 phb->hub_id = hub_id;
3712 phb->opal_id = phb_id;
3713 phb->type = ioda_type;
3714 mutex_init(&phb->ioda.pe_alloc_mutex);
3716 /* Detect specific models for error handling */
3717 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3718 phb->model = PNV_PHB_MODEL_P7IOC;
3719 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3720 phb->model = PNV_PHB_MODEL_PHB3;
3721 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3722 phb->model = PNV_PHB_MODEL_NPU;
3723 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3724 phb->model = PNV_PHB_MODEL_NPU2;
3726 phb->model = PNV_PHB_MODEL_UNKNOWN;
3728 /* Parse 32-bit and IO ranges (if any) */
3729 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3732 if (!of_address_to_resource(np, 0, &r)) {
3733 phb->regs_phys = r.start;
3734 phb->regs = ioremap(r.start, resource_size(&r));
3735 if (phb->regs == NULL)
3736 pr_err(" Failed to map registers !\n");
3739 /* Initialize more IODA stuff */
3740 phb->ioda.total_pe_num = 1;
3741 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3743 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3744 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3746 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3748 /* Invalidate RID to PE# mapping */
3749 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3750 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3752 /* Parse 64-bit MMIO range */
3753 pnv_ioda_parse_m64_window(phb);
3755 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3756 /* FW Has already off top 64k of M32 space (MSI space) */
3757 phb->ioda.m32_size += 0x10000;
3759 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3760 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3761 phb->ioda.io_size = hose->pci_io_size;
3762 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3763 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3765 /* Calculate how many 32-bit TCE segments we have */
3766 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3767 PNV_IODA1_DMA32_SEGSIZE;
3769 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3770 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3771 sizeof(unsigned long));
3773 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3775 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3776 if (phb->type == PNV_PHB_IODA1) {
3778 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3779 dma32map_off = size;
3780 size += phb->ioda.dma32_count *
3781 sizeof(phb->ioda.dma32_segmap[0]);
3784 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3785 aux = memblock_virt_alloc(size, 0);
3786 phb->ioda.pe_alloc = aux;
3787 phb->ioda.m64_segmap = aux + m64map_off;
3788 phb->ioda.m32_segmap = aux + m32map_off;
3789 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3790 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3791 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3793 if (phb->type == PNV_PHB_IODA1) {
3794 phb->ioda.io_segmap = aux + iomap_off;
3795 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3796 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3798 phb->ioda.dma32_segmap = aux + dma32map_off;
3799 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3800 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3802 phb->ioda.pe_array = aux + pemap_off;
3805 * Choose PE number for root bus, which shouldn't have
3806 * M64 resources consumed by its child devices. To pick
3807 * the PE number adjacent to the reserved one if possible.
3809 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3810 if (phb->ioda.reserved_pe_idx == 0) {
3811 phb->ioda.root_pe_idx = 1;
3812 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3813 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3814 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3815 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3817 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3820 INIT_LIST_HEAD(&phb->ioda.pe_list);
3821 mutex_init(&phb->ioda.pe_list_mutex);
3823 /* Calculate how many 32-bit TCE segments we have */
3824 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3825 PNV_IODA1_DMA32_SEGSIZE;
3827 #if 0 /* We should really do that ... */
3828 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3831 starting_real_address,
3832 starting_pci_address,
3836 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3837 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3838 phb->ioda.m32_size, phb->ioda.m32_segsize);
3839 if (phb->ioda.m64_size)
3840 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3841 phb->ioda.m64_size, phb->ioda.m64_segsize);
3842 if (phb->ioda.io_size)
3843 pr_info(" IO: 0x%x [segment=0x%x]\n",
3844 phb->ioda.io_size, phb->ioda.io_segsize);
3847 phb->hose->ops = &pnv_pci_ops;
3848 phb->get_pe_state = pnv_ioda_get_pe_state;
3849 phb->freeze_pe = pnv_ioda_freeze_pe;
3850 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3852 /* Setup MSI support */
3853 pnv_pci_init_ioda_msis(phb);
3856 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3857 * to let the PCI core do resource assignment. It's supposed
3858 * that the PCI core will do correct I/O and MMIO alignment
3859 * for the P2P bridge bars so that each PCI bus (excluding
3860 * the child P2P bridges) can form individual PE.
3862 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3864 if (phb->type == PNV_PHB_NPU) {
3865 hose->controller_ops = pnv_npu_ioda_controller_ops;
3867 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3868 hose->controller_ops = pnv_pci_ioda_controller_ops;
3871 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3873 #ifdef CONFIG_PCI_IOV
3874 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3875 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3878 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3880 /* Reset IODA tables to a clean state */
3881 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3883 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
3886 * If we're running in kdump kernel, the previous kernel never
3887 * shutdown PCI devices correctly. We already got IODA table
3888 * cleaned out. So we have to issue PHB reset to stop all PCI
3889 * transactions from previous kernel.
3891 if (is_kdump_kernel()) {
3892 pr_info(" Issue PHB reset ...\n");
3893 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3894 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3897 /* Remove M64 resource if we can't configure it successfully */
3898 if (!phb->init_m64 || phb->init_m64(phb))
3899 hose->mem_resources[1].flags = 0;
3902 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3904 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3907 void __init pnv_pci_init_npu_phb(struct device_node *np)
3909 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3912 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3914 struct device_node *phbn;
3915 const __be64 *prop64;
3918 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3920 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3922 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3925 hub_id = be64_to_cpup(prop64);
3926 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3928 /* Count child PHBs */
3929 for_each_child_of_node(np, phbn) {
3930 /* Look for IODA1 PHBs */
3931 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3932 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);