2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/memblock.h>
27 #include <linux/log2.h>
28 #include <linux/slab.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/machdep.h>
34 #include <sysdev/fsl_soc.h>
35 #include <sysdev/fsl_pci.h>
37 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
39 static void quirk_fsl_pcie_header(struct pci_dev *dev)
43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
49 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
57 static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
60 static int fsl_pcie_check_link(struct pci_controller *hose)
64 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
65 if (hose->ops->read == fsl_indirect_read_config) {
70 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
72 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
73 if (val < PCIE_LTSSM_L0)
76 struct ccsr_pci __iomem *pci = hose->private_data;
77 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
78 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
79 >> PEX_CSR0_LTSSM_SHIFT;
80 if (val != PEX_CSR0_LTSSM_L0)
87 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
88 int offset, int len, u32 *val)
90 struct pci_controller *hose = pci_bus_to_host(bus);
92 if (fsl_pcie_check_link(hose))
93 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
95 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
97 return indirect_read_config(bus, devfn, offset, len, val);
100 static struct pci_ops fsl_indirect_pci_ops =
102 .read = fsl_indirect_read_config,
103 .write = indirect_write_config,
106 static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
107 resource_size_t cfg_addr,
108 resource_size_t cfg_data, u32 flags)
110 setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
111 hose->ops = &fsl_indirect_pci_ops;
114 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
116 #define MAX_PHYS_ADDR_BITS 40
117 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
119 static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
121 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
125 * Fixup PCI devices that are able to DMA to above the physical
126 * address width of the SoC such that we can address any internal
127 * SoC address from across PCI if needed
129 if ((dev->bus == &pci_bus_type) &&
130 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
131 set_dma_ops(dev, &dma_direct_ops);
132 set_dma_offset(dev, pci64_dma_offset);
135 *dev->dma_mask = dma_mask;
139 static int setup_one_atmu(struct ccsr_pci __iomem *pci,
140 unsigned int index, const struct resource *res,
141 resource_size_t offset)
143 resource_size_t pci_addr = res->start - offset;
144 resource_size_t phys_addr = res->start;
145 resource_size_t size = resource_size(res);
146 u32 flags = 0x80044000; /* enable & mem R/W */
149 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
150 (u64)res->start, (u64)size);
152 if (res->flags & IORESOURCE_PREFETCH)
153 flags |= 0x10000000; /* enable relaxed ordering */
155 for (i = 0; size > 0; i++) {
156 unsigned int bits = min(ilog2(size),
157 __ffs(pci_addr | phys_addr));
162 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
163 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
164 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
165 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
167 pci_addr += (resource_size_t)1U << bits;
168 phys_addr += (resource_size_t)1U << bits;
169 size -= (resource_size_t)1U << bits;
175 /* atmu setup for fsl pci/pcie controller */
176 static void setup_pci_atmu(struct pci_controller *hose)
178 struct ccsr_pci __iomem *pci = hose->private_data;
179 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
180 u64 mem, sz, paddr_hi = 0;
181 u64 paddr_lo = ULLONG_MAX;
182 u32 pcicsrbar = 0, pcicsrbar_sz;
183 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
184 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
185 const char *name = hose->dn->full_name;
189 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
190 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
197 /* Disable all windows (except powar0 since it's ignored) */
198 for(i = 1; i < 5; i++)
199 out_be32(&pci->pow[i].powar, 0);
200 for (i = start_idx; i < end_idx; i++)
201 out_be32(&pci->piw[i].piwar, 0);
203 /* Setup outbound MEM window */
204 for(i = 0, j = 1; i < 3; i++) {
205 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
208 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
209 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
211 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
212 hose->pci_mem_offset);
214 if (n < 0 || j >= 5) {
215 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
216 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
221 /* Setup outbound IO window */
222 if (hose->io_resource.flags & IORESOURCE_IO) {
224 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
226 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
227 "phy base 0x%016llx.\n",
228 (u64)hose->io_resource.start,
229 (u64)resource_size(&hose->io_resource),
230 (u64)hose->io_base_phys);
231 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
232 out_be32(&pci->pow[j].potear, 0);
233 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
235 out_be32(&pci->pow[j].powar, 0x80088000
236 | (ilog2(hose->io_resource.end
237 - hose->io_resource.start + 1) - 1));
241 /* convert to pci address space */
242 paddr_hi -= hose->pci_mem_offset;
243 paddr_lo -= hose->pci_mem_offset;
245 if (paddr_hi == paddr_lo) {
246 pr_err("%s: No outbound window space\n", name);
251 pr_err("%s: No space for inbound window\n", name);
255 /* setup PCSRBAR/PEXCSRBAR */
256 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
257 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
258 pcicsrbar_sz = ~pcicsrbar_sz + 1;
260 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
261 (paddr_lo > 0x100000000ull))
262 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
264 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
265 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
267 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
269 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
271 /* Setup inbound mem window */
272 mem = memblock_end_of_DRAM();
275 * The msi-address-64 property, if it exists, indicates the physical
276 * address of the MSIIR register. Normally, this register is located
277 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
278 * this property exists, then we normally need to create a new ATMU
279 * for it. For now, however, we cheat. The only entity that creates
280 * this property is the Freescale hypervisor, and the address is
281 * specified in the partition configuration. Typically, the address
282 * is located in the page immediately after the end of DDR. If so, we
283 * can avoid allocating a new ATMU by extending the DDR ATMU by one
286 reg = of_get_property(hose->dn, "msi-address-64", &len);
287 if (reg && (len == sizeof(u64))) {
288 u64 address = be64_to_cpup(reg);
290 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
291 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
294 /* TODO: Create a new ATMU for MSIIR */
295 pr_warn("%s: msi-address-64 address of %llx is "
296 "unsupported\n", name, address);
300 sz = min(mem, paddr_lo);
303 /* PCIe can overmap inbound & outbound since RX & TX are separated */
304 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
305 /* Size window to exact size if power-of-two or one size up */
306 if ((1ull << mem_log) != mem) {
307 if ((1ull << mem_log) > mem)
308 pr_info("%s: Setting PCI inbound window "
309 "greater than memory size\n", name);
313 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
315 /* Setup inbound memory window */
316 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
317 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
318 out_be32(&pci->piw[win_idx].piwar, piwar);
321 hose->dma_window_base_cur = 0x00000000;
322 hose->dma_window_size = (resource_size_t)sz;
325 * if we have >4G of memory setup second PCI inbound window to
326 * let devices that are 64-bit address capable to work w/o
327 * SWIOTLB and access the full range of memory
330 mem_log = ilog2(mem);
332 /* Size window up if we dont fit in exact power-of-2 */
333 if ((1ull << mem_log) != mem)
336 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
338 /* Setup inbound memory window */
339 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
340 out_be32(&pci->piw[win_idx].piwbear,
341 pci64_dma_offset >> 44);
342 out_be32(&pci->piw[win_idx].piwbar,
343 pci64_dma_offset >> 12);
344 out_be32(&pci->piw[win_idx].piwar, piwar);
347 * install our own dma_set_mask handler to fixup dma_ops
350 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
352 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
357 /* Setup inbound memory window */
358 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
359 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
360 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
363 paddr += 1ull << mem_log;
364 sz -= 1ull << mem_log;
368 piwar |= (mem_log - 1);
370 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
371 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
372 out_be32(&pci->piw[win_idx].piwar, piwar);
375 paddr += 1ull << mem_log;
378 hose->dma_window_base_cur = 0x00000000;
379 hose->dma_window_size = (resource_size_t)paddr;
382 if (hose->dma_window_size < mem) {
383 #ifndef CONFIG_SWIOTLB
384 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
385 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
388 /* adjusting outbound windows could reclaim space in mem map */
389 if (paddr_hi < 0xffffffffull)
390 pr_warning("%s: WARNING: Outbound window cfg leaves "
391 "gaps in memory map. Adjusting the memory map "
392 "could reduce unnecessary bounce buffering.\n",
395 pr_info("%s: DMA window size is 0x%llx\n", name,
396 (u64)hose->dma_window_size);
400 static void __init setup_pci_cmd(struct pci_controller *hose)
405 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
406 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
408 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
410 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
412 int pci_x_cmd = cap_x + PCI_X_CMD;
413 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
414 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
415 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
417 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
421 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
423 struct pci_controller *hose = pci_bus_to_host(bus);
424 int i, is_pcie = 0, no_link;
426 /* The root complex bridge comes up with bogus resources,
427 * we copy the PHB ones in.
429 * With the current generic PCI code, the PHB bus no longer
430 * has bus->resource[0..4] set, so things are a bit more
434 if (fsl_pcie_bus_fixup)
435 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
436 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
438 if (bus->parent == hose->bus && (is_pcie || no_link)) {
439 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
440 struct resource *res = bus->resource[i];
441 struct resource *par;
446 par = &hose->io_resource;
448 par = &hose->mem_resources[i-1];
451 res->start = par ? par->start : 0;
452 res->end = par ? par->end : 0;
453 res->flags = par ? par->flags : 0;
458 int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
461 struct pci_controller *hose;
462 struct resource rsrc;
463 const int *bus_range;
465 struct device_node *dev;
466 struct ccsr_pci __iomem *pci;
468 dev = pdev->dev.of_node;
470 if (!of_device_is_available(dev)) {
471 pr_warning("%s: disabled\n", dev->full_name);
475 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
477 /* Fetch host bridge registers address */
478 if (of_address_to_resource(dev, 0, &rsrc)) {
479 printk(KERN_WARNING "Can't get pci register base!");
483 /* Get bus range if any */
484 bus_range = of_get_property(dev, "bus-range", &len);
485 if (bus_range == NULL || len < 2 * sizeof(int))
486 printk(KERN_WARNING "Can't get bus-range for %s, assume"
487 " bus 0\n", dev->full_name);
489 pci_add_flags(PCI_REASSIGN_ALL_BUS);
490 hose = pcibios_alloc_controller(dev);
494 /* set platform device as the parent */
495 hose->parent = &pdev->dev;
496 hose->first_busno = bus_range ? bus_range[0] : 0x0;
497 hose->last_busno = bus_range ? bus_range[1] : 0xff;
499 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
500 (u64)rsrc.start, (u64)resource_size(&rsrc));
502 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
503 if (!hose->private_data)
506 fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
507 PPC_INDIRECT_TYPE_BIG_ENDIAN);
509 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
510 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
512 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
513 /* For PCIE read HEADER_TYPE to identify controler mode */
514 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
515 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
519 /* For PCI read PROG to identify controller mode */
520 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
521 if ((progif & 1) == 1)
527 /* check PCI express link status */
528 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
529 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
530 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
531 if (fsl_pcie_check_link(hose))
532 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
535 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
536 "Firmware bus number: %d->%d\n",
537 (unsigned long long)rsrc.start, hose->first_busno,
540 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
541 hose, hose->cfg_addr, hose->cfg_data);
543 /* Interpret the "ranges" property */
544 /* This also maps the I/O region and sets isa_io/mem_base */
545 pci_process_bridge_OF_ranges(hose, dev, is_primary);
547 /* Setup PEX window registers */
548 setup_pci_atmu(hose);
553 iounmap(hose->private_data);
554 /* unmap cfg_data & cfg_addr separately if not on same page */
555 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
556 ((unsigned long)hose->cfg_addr & PAGE_MASK))
557 iounmap(hose->cfg_data);
558 iounmap(hose->cfg_addr);
559 pcibios_free_controller(hose);
562 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
564 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
566 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
567 struct mpc83xx_pcie_priv {
568 void __iomem *cfg_type0;
569 void __iomem *cfg_type1;
573 struct pex_inbound_window {
581 * With the convention of u-boot, the PCIE outbound window 0 serves
582 * as configuration transactions outbound.
584 #define PEX_OUTWIN0_BAR 0xCA4
585 #define PEX_OUTWIN0_TAL 0xCA8
586 #define PEX_OUTWIN0_TAH 0xCAC
587 #define PEX_RC_INWIN_BASE 0xE60
588 #define PEX_RCIWARn_EN 0x1
590 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
592 struct pci_controller *hose = pci_bus_to_host(bus);
594 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
595 return PCIBIOS_DEVICE_NOT_FOUND;
597 * Workaround for the HW bug: for Type 0 configure transactions the
598 * PCI-E controller does not check the device number bits and just
599 * assumes that the device number bits are 0.
601 if (bus->number == hose->first_busno ||
602 bus->primary == hose->first_busno) {
604 return PCIBIOS_DEVICE_NOT_FOUND;
607 if (ppc_md.pci_exclude_device) {
608 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
609 return PCIBIOS_DEVICE_NOT_FOUND;
612 return PCIBIOS_SUCCESSFUL;
615 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
616 unsigned int devfn, int offset)
618 struct pci_controller *hose = pci_bus_to_host(bus);
619 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
620 u32 dev_base = bus->number << 24 | devfn << 16;
623 ret = mpc83xx_pcie_exclude_device(bus, devfn);
630 if (bus->number == hose->first_busno)
631 return pcie->cfg_type0 + offset;
633 if (pcie->dev_base == dev_base)
636 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
638 pcie->dev_base = dev_base;
640 return pcie->cfg_type1 + offset;
643 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
644 int offset, int len, u32 *val)
646 void __iomem *cfg_addr;
648 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
650 return PCIBIOS_DEVICE_NOT_FOUND;
654 *val = in_8(cfg_addr);
657 *val = in_le16(cfg_addr);
660 *val = in_le32(cfg_addr);
664 return PCIBIOS_SUCCESSFUL;
667 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
668 int offset, int len, u32 val)
670 struct pci_controller *hose = pci_bus_to_host(bus);
671 void __iomem *cfg_addr;
673 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
675 return PCIBIOS_DEVICE_NOT_FOUND;
677 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
678 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
683 out_8(cfg_addr, val);
686 out_le16(cfg_addr, val);
689 out_le32(cfg_addr, val);
693 return PCIBIOS_SUCCESSFUL;
696 static struct pci_ops mpc83xx_pcie_ops = {
697 .read = mpc83xx_pcie_read_config,
698 .write = mpc83xx_pcie_write_config,
701 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
702 struct resource *reg)
704 struct mpc83xx_pcie_priv *pcie;
708 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
712 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
713 if (!pcie->cfg_type0)
716 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
718 /* PCI-E isn't configured. */
723 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
724 if (!pcie->cfg_type1)
727 WARN_ON(hose->dn->data);
728 hose->dn->data = pcie;
729 hose->ops = &mpc83xx_pcie_ops;
730 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
732 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
733 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
735 if (fsl_pcie_check_link(hose))
736 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
740 iounmap(pcie->cfg_type0);
747 int __init mpc83xx_add_bridge(struct device_node *dev)
751 struct pci_controller *hose;
752 struct resource rsrc_reg;
753 struct resource rsrc_cfg;
754 const int *bus_range;
759 if (!of_device_is_available(dev)) {
760 pr_warning("%s: disabled by the firmware.\n",
764 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
766 /* Fetch host bridge registers address */
767 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
768 printk(KERN_WARNING "Can't get pci register base!\n");
772 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
774 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
776 "No pci config register base in dev tree, "
779 * MPC83xx supports up to two host controllers
780 * one at 0x8500 has config space registers at 0x8300
781 * one at 0x8600 has config space registers at 0x8380
783 if ((rsrc_reg.start & 0xfffff) == 0x8500)
784 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
785 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
786 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
789 * Controller at offset 0x8500 is primary
791 if ((rsrc_reg.start & 0xfffff) == 0x8500)
796 /* Get bus range if any */
797 bus_range = of_get_property(dev, "bus-range", &len);
798 if (bus_range == NULL || len < 2 * sizeof(int)) {
799 printk(KERN_WARNING "Can't get bus-range for %s, assume"
800 " bus 0\n", dev->full_name);
803 pci_add_flags(PCI_REASSIGN_ALL_BUS);
804 hose = pcibios_alloc_controller(dev);
808 hose->first_busno = bus_range ? bus_range[0] : 0;
809 hose->last_busno = bus_range ? bus_range[1] : 0xff;
811 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
812 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
816 fsl_setup_indirect_pci(hose, rsrc_cfg.start,
817 rsrc_cfg.start + 4, 0);
820 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
821 "Firmware bus number: %d->%d\n",
822 (unsigned long long)rsrc_reg.start, hose->first_busno,
825 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
826 hose, hose->cfg_addr, hose->cfg_data);
828 /* Interpret the "ranges" property */
829 /* This also maps the I/O region and sets isa_io/mem_base */
830 pci_process_bridge_OF_ranges(hose, dev, primary);
834 pcibios_free_controller(hose);
837 #endif /* CONFIG_PPC_83xx */
839 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
841 #ifdef CONFIG_PPC_83xx
842 if (is_mpc83xx_pci) {
843 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
844 struct pex_inbound_window *in;
847 /* Walk the Root Complex Inbound windows to match IMMR base */
848 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
849 for (i = 0; i < 4; i++) {
850 /* not enabled, skip */
851 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
854 if (get_immrbase() == in_le32(&in[i].tar))
855 return (u64)in_le32(&in[i].barh) << 32 |
856 in_le32(&in[i].barl);
859 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
863 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
864 if (!is_mpc83xx_pci) {
867 pci_bus_read_config_dword(hose->bus,
868 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
876 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
877 static const struct of_device_id pci_ids[] = {
878 { .compatible = "fsl,mpc8540-pci", },
879 { .compatible = "fsl,mpc8548-pcie", },
880 { .compatible = "fsl,mpc8610-pci", },
881 { .compatible = "fsl,mpc8641-pcie", },
882 { .compatible = "fsl,qoriq-pcie-v2.1", },
883 { .compatible = "fsl,qoriq-pcie-v2.2", },
884 { .compatible = "fsl,qoriq-pcie-v2.3", },
885 { .compatible = "fsl,qoriq-pcie-v2.4", },
886 { .compatible = "fsl,qoriq-pcie-v3.0", },
889 * The following entries are for compatibility with older device
892 { .compatible = "fsl,p1022-pcie", },
893 { .compatible = "fsl,p4080-pcie", },
898 struct device_node *fsl_pci_primary;
900 void fsl_pci_assign_primary(void)
902 struct device_node *np;
904 /* Callers can specify the primary bus using other means. */
908 /* If a PCI host bridge contains an ISA node, it's primary. */
909 np = of_find_node_by_type(NULL, "isa");
910 while ((fsl_pci_primary = of_get_parent(np))) {
912 np = fsl_pci_primary;
914 if (of_match_node(pci_ids, np) && of_device_is_available(np))
919 * If there's no PCI host bridge with ISA, arbitrarily
920 * designate one as primary. This can go away once
921 * various bugs with primary-less systems are fixed.
923 for_each_matching_node(np, pci_ids) {
924 if (of_device_is_available(np)) {
925 fsl_pci_primary = np;
932 static int fsl_pci_probe(struct platform_device *pdev)
935 struct device_node *node;
936 #ifdef CONFIG_SWIOTLB
937 struct pci_controller *hose;
940 node = pdev->dev.of_node;
941 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
943 #ifdef CONFIG_SWIOTLB
945 hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
948 * if we couldn't map all of DRAM via the dma windows
949 * we need SWIOTLB to handle buffers located outside of
950 * dma capable memory region
952 if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
953 hose->dma_window_size)
954 ppc_swiotlb_enable = 1;
958 mpc85xx_pci_err_probe(pdev);
964 static int fsl_pci_resume(struct device *dev)
966 struct pci_controller *hose;
967 struct resource pci_rsrc;
969 hose = pci_find_hose_for_OF_device(dev->of_node);
973 if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
974 dev_err(dev, "Get pci register base failed.");
978 setup_pci_atmu(hose);
983 static const struct dev_pm_ops pci_pm_ops = {
984 .resume = fsl_pci_resume,
987 #define PCI_PM_OPS (&pci_pm_ops)
991 #define PCI_PM_OPS NULL
995 static struct platform_driver fsl_pci_driver = {
999 .of_match_table = pci_ids,
1001 .probe = fsl_pci_probe,
1004 static int __init fsl_pci_init(void)
1006 return platform_driver_register(&fsl_pci_driver);
1008 arch_initcall(fsl_pci_init);