2 * Freescale MPC85xx/MPC86xx RapidIO support
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
13 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/interrupt.h>
30 #include <linux/device.h>
31 #include <linux/rio.h>
32 #include <linux/rio_drv.h>
33 #include <linux/of_platform.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36 #include <linux/kfifo.h>
39 #include <asm/machdep.h>
40 #include <asm/uaccess.h>
42 #undef DEBUG_PW /* Port-Write debugging */
44 /* RapidIO definition irq, which read from OF-tree */
45 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
46 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
47 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
48 #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
50 #define RIO_ATMU_REGS_OFFSET 0x10c00
51 #define RIO_P_MSG_REGS_OFFSET 0x11000
52 #define RIO_S_MSG_REGS_OFFSET 0x13000
53 #define RIO_GCCSR 0x13c
54 #define RIO_ESCSR 0x158
55 #define RIO_CCSR 0x15c
56 #define RIO_LTLEDCSR 0x0608
57 #define RIO_LTLEDCSR_IER 0x80000000
58 #define RIO_LTLEDCSR_PRT 0x01000000
59 #define RIO_LTLEECSR 0x060c
60 #define RIO_EPWISR 0x10010
61 #define RIO_ISR_AACR 0x10120
62 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
63 #define RIO_MAINT_WIN_SIZE 0x400000
64 #define RIO_DBELL_WIN_SIZE 0x1000
66 #define RIO_MSG_OMR_MUI 0x00000002
67 #define RIO_MSG_OSR_TE 0x00000080
68 #define RIO_MSG_OSR_QOI 0x00000020
69 #define RIO_MSG_OSR_QFI 0x00000010
70 #define RIO_MSG_OSR_MUB 0x00000004
71 #define RIO_MSG_OSR_EOMI 0x00000002
72 #define RIO_MSG_OSR_QEI 0x00000001
74 #define RIO_MSG_IMR_MI 0x00000002
75 #define RIO_MSG_ISR_TE 0x00000080
76 #define RIO_MSG_ISR_QFI 0x00000010
77 #define RIO_MSG_ISR_DIQI 0x00000001
79 #define RIO_IPWMR_SEN 0x00100000
80 #define RIO_IPWMR_QFIE 0x00000100
81 #define RIO_IPWMR_EIE 0x00000020
82 #define RIO_IPWMR_CQ 0x00000002
83 #define RIO_IPWMR_PWE 0x00000001
85 #define RIO_IPWSR_QF 0x00100000
86 #define RIO_IPWSR_TE 0x00000080
87 #define RIO_IPWSR_QFI 0x00000010
88 #define RIO_IPWSR_PWD 0x00000008
89 #define RIO_IPWSR_PWB 0x00000004
91 #define RIO_EPWISR_PINT 0x80000000
92 #define RIO_EPWISR_PW 0x00000001
94 #define RIO_MSG_DESC_SIZE 32
95 #define RIO_MSG_BUFFER_SIZE 4096
96 #define RIO_MIN_TX_RING_SIZE 2
97 #define RIO_MAX_TX_RING_SIZE 2048
98 #define RIO_MIN_RX_RING_SIZE 2
99 #define RIO_MAX_RX_RING_SIZE 2048
101 #define DOORBELL_DMR_DI 0x00000002
102 #define DOORBELL_DSR_TE 0x00000080
103 #define DOORBELL_DSR_QFI 0x00000010
104 #define DOORBELL_DSR_DIQI 0x00000001
105 #define DOORBELL_TID_OFFSET 0x02
106 #define DOORBELL_SID_OFFSET 0x04
107 #define DOORBELL_INFO_OFFSET 0x06
109 #define DOORBELL_MESSAGE_SIZE 0x08
110 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
111 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
112 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
114 struct rio_atmu_regs {
123 struct rio_msg_regs {
124 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
125 u32 osr; /* 0xD_3004 - Outbound message 0 status register */
127 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
128 dequeue pointer address register */
130 u32 osar; /* 0xD_3014 - Outbound message 0 source address
132 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
134 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
136 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
139 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
140 enqueue pointer address register */
142 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
143 u32 isr; /* 0xD_3064 - Inbound message 0 status register */
145 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
146 pointer address register*/
148 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
149 pointer address register */
151 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
152 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
154 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
156 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
159 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
160 configuration register */
162 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
163 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
165 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
168 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
171 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
172 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
173 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
175 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
190 struct rio_dbell_ring {
195 struct rio_msg_tx_ring {
198 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
199 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
205 struct rio_msg_rx_ring {
208 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
214 struct rio_port_write_msg {
224 void __iomem *regs_win;
225 struct rio_atmu_regs __iomem *atmu_regs;
226 struct rio_atmu_regs __iomem *maint_atmu_regs;
227 struct rio_atmu_regs __iomem *dbell_atmu_regs;
228 void __iomem *dbell_win;
229 void __iomem *maint_win;
230 struct rio_msg_regs __iomem *msg_regs;
231 struct rio_dbell_ring dbell_ring;
232 struct rio_msg_tx_ring msg_tx_ring;
233 struct rio_msg_rx_ring msg_rx_ring;
234 struct rio_port_write_msg port_write_msg;
239 struct work_struct pw_work;
240 struct kfifo pw_fifo;
241 spinlock_t pw_fifo_lock;
244 #define __fsl_read_rio_config(x, addr, err, op) \
245 __asm__ __volatile__( \
246 "1: "op" %1,0(%2)\n" \
249 ".section .fixup,\"ax\"\n" \
253 ".section __ex_table,\"a\"\n" \
257 : "=r" (err), "=r" (x) \
258 : "b" (addr), "i" (-EFAULT), "0" (err))
260 static void __iomem *rio_regs_win;
263 static int (*saved_mcheck_exception)(struct pt_regs *regs);
265 static int fsl_rio_mcheck_exception(struct pt_regs *regs)
267 const struct exception_table_entry *entry = NULL;
268 unsigned long reason = mfspr(SPRN_MCSR);
270 if (reason & MCSR_BUS_RBERR) {
271 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
272 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
273 /* Check if we are prepared to handle this fault */
274 entry = search_exception_tables(regs->nip);
276 pr_debug("RIO: %s - MC Exception handled\n",
278 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
281 regs->nip = entry->fixup;
287 if (saved_mcheck_exception)
288 return saved_mcheck_exception(regs);
290 return cur_cpu_spec->machine_check(regs);
295 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
296 * @mport: RapidIO master port info
297 * @index: ID of RapidIO interface
298 * @destid: Destination ID of target device
299 * @data: 16-bit info field of RapidIO doorbell message
301 * Sends a MPC85xx doorbell message. Returns %0 on success or
302 * %-EINVAL on failure.
304 static int fsl_rio_doorbell_send(struct rio_mport *mport,
305 int index, u16 destid, u16 data)
307 struct rio_priv *priv = mport->priv;
308 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
309 index, destid, data);
310 switch (mport->phy_type) {
311 case RIO_PHY_PARALLEL:
312 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
313 out_be16(priv->dbell_win, data);
316 /* In the serial version silicons, such as MPC8548, MPC8641,
317 * below operations is must be.
319 out_be32(&priv->msg_regs->odmr, 0x00000000);
320 out_be32(&priv->msg_regs->odretcr, 0x00000004);
321 out_be32(&priv->msg_regs->oddpr, destid << 16);
322 out_be32(&priv->msg_regs->oddatr, data);
323 out_be32(&priv->msg_regs->odmr, 0x00000001);
331 * fsl_local_config_read - Generate a MPC85xx local config space read
332 * @mport: RapidIO master port info
333 * @index: ID of RapdiIO interface
334 * @offset: Offset into configuration space
335 * @len: Length (in bytes) of the maintenance transaction
336 * @data: Value to be read into
338 * Generates a MPC85xx local configuration space read. Returns %0 on
339 * success or %-EINVAL on failure.
341 static int fsl_local_config_read(struct rio_mport *mport,
342 int index, u32 offset, int len, u32 *data)
344 struct rio_priv *priv = mport->priv;
345 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
347 *data = in_be32(priv->regs_win + offset);
353 * fsl_local_config_write - Generate a MPC85xx local config space write
354 * @mport: RapidIO master port info
355 * @index: ID of RapdiIO interface
356 * @offset: Offset into configuration space
357 * @len: Length (in bytes) of the maintenance transaction
358 * @data: Value to be written
360 * Generates a MPC85xx local configuration space write. Returns %0 on
361 * success or %-EINVAL on failure.
363 static int fsl_local_config_write(struct rio_mport *mport,
364 int index, u32 offset, int len, u32 data)
366 struct rio_priv *priv = mport->priv;
368 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
369 index, offset, data);
370 out_be32(priv->regs_win + offset, data);
376 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
377 * @mport: RapidIO master port info
378 * @index: ID of RapdiIO interface
379 * @destid: Destination ID of transaction
380 * @hopcount: Number of hops to target device
381 * @offset: Offset into configuration space
382 * @len: Length (in bytes) of the maintenance transaction
383 * @val: Location to be read into
385 * Generates a MPC85xx read maintenance transaction. Returns %0 on
386 * success or %-EINVAL on failure.
389 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
390 u8 hopcount, u32 offset, int len, u32 *val)
392 struct rio_priv *priv = mport->priv;
397 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
398 index, destid, hopcount, offset, len);
400 /* 16MB maintenance window possible */
401 /* allow only aligned access to maintenance registers */
402 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
405 out_be32(&priv->maint_atmu_regs->rowtar,
406 (destid << 22) | (hopcount << 12) | (offset >> 12));
407 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
409 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
412 __fsl_read_rio_config(rval, data, err, "lbz");
415 __fsl_read_rio_config(rval, data, err, "lhz");
418 __fsl_read_rio_config(rval, data, err, "lwz");
425 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
426 err, destid, hopcount, offset);
435 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
436 * @mport: RapidIO master port info
437 * @index: ID of RapdiIO interface
438 * @destid: Destination ID of transaction
439 * @hopcount: Number of hops to target device
440 * @offset: Offset into configuration space
441 * @len: Length (in bytes) of the maintenance transaction
442 * @val: Value to be written
444 * Generates an MPC85xx write maintenance transaction. Returns %0 on
445 * success or %-EINVAL on failure.
448 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
449 u8 hopcount, u32 offset, int len, u32 val)
451 struct rio_priv *priv = mport->priv;
454 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
455 index, destid, hopcount, offset, len, val);
457 /* 16MB maintenance windows possible */
458 /* allow only aligned access to maintenance registers */
459 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
462 out_be32(&priv->maint_atmu_regs->rowtar,
463 (destid << 22) | (hopcount << 12) | (offset >> 12));
464 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
466 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
469 out_8((u8 *) data, val);
472 out_be16((u16 *) data, val);
475 out_be32((u32 *) data, val);
485 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
486 * @mport: Master port with outbound message queue
487 * @rdev: Target of outbound message
488 * @mbox: Outbound mailbox
489 * @buffer: Message to add to outbound queue
490 * @len: Length of message
492 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
493 * %0 on success or %-EINVAL on failure.
496 fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
497 void *buffer, size_t len)
499 struct rio_priv *priv = mport->priv;
501 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
502 + priv->msg_tx_ring.tx_slot;
505 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
506 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
508 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
513 /* Copy and clear rest of buffer */
514 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
516 if (len < (RIO_MAX_MSG_SIZE - 4))
517 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
518 + len, 0, RIO_MAX_MSG_SIZE - len);
520 switch (mport->phy_type) {
521 case RIO_PHY_PARALLEL:
522 /* Set mbox field for message */
523 desc->dport = mbox & 0x3;
525 /* Enable EOMI interrupt, set priority, and set destid */
526 desc->dattr = 0x28000000 | (rdev->destid << 2);
529 /* Set mbox field for message, and set destid */
530 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
532 /* Enable EOMI interrupt and priority */
533 desc->dattr = 0x28000000;
537 /* Set transfer size aligned to next power of 2 (in double words) */
538 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
540 /* Set snooping and source buffer address */
541 desc->saddr = 0x00000004
542 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
544 /* Increment enqueue pointer */
545 omr = in_be32(&priv->msg_regs->omr);
546 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
548 /* Go to next descriptor */
549 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
550 priv->msg_tx_ring.tx_slot = 0;
557 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
558 * @irq: Linux interrupt number
559 * @dev_instance: Pointer to interrupt-specific data
561 * Handles outbound message interrupts. Executes a register outbound
562 * mailbox event handler and acks the interrupt occurrence.
565 fsl_rio_tx_handler(int irq, void *dev_instance)
568 struct rio_mport *port = (struct rio_mport *)dev_instance;
569 struct rio_priv *priv = port->priv;
571 osr = in_be32(&priv->msg_regs->osr);
573 if (osr & RIO_MSG_OSR_TE) {
574 pr_info("RIO: outbound message transmission error\n");
575 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
579 if (osr & RIO_MSG_OSR_QOI) {
580 pr_info("RIO: outbound message queue overflow\n");
581 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
585 if (osr & RIO_MSG_OSR_EOMI) {
586 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
587 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
588 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
591 /* Ack the end-of-message interrupt */
592 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
600 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
601 * @mport: Master port implementing the outbound message unit
602 * @dev_id: Device specific pointer to pass on event
603 * @mbox: Mailbox to open
604 * @entries: Number of entries in the outbound mailbox ring
606 * Initializes buffer ring, request the outbound message interrupt,
607 * and enables the outbound message unit. Returns %0 on success and
608 * %-EINVAL or %-ENOMEM on failure.
611 fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
614 struct rio_priv *priv = mport->priv;
616 if ((entries < RIO_MIN_TX_RING_SIZE) ||
617 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
622 /* Initialize shadow copy ring */
623 priv->msg_tx_ring.dev_id = dev_id;
624 priv->msg_tx_ring.size = entries;
626 for (i = 0; i < priv->msg_tx_ring.size; i++) {
627 priv->msg_tx_ring.virt_buffer[i] =
628 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
629 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
630 if (!priv->msg_tx_ring.virt_buffer[i]) {
632 for (j = 0; j < priv->msg_tx_ring.size; j++)
633 if (priv->msg_tx_ring.virt_buffer[j])
634 dma_free_coherent(priv->dev,
644 /* Initialize outbound message descriptor ring */
645 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
646 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
647 &priv->msg_tx_ring.phys, GFP_KERNEL);
648 if (!priv->msg_tx_ring.virt) {
652 memset(priv->msg_tx_ring.virt, 0,
653 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
654 priv->msg_tx_ring.tx_slot = 0;
656 /* Point dequeue/enqueue pointers at first entry in ring */
657 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
658 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
660 /* Configure for snooping */
661 out_be32(&priv->msg_regs->osar, 0x00000004);
663 /* Clear interrupt status */
664 out_be32(&priv->msg_regs->osr, 0x000000b3);
666 /* Hook up outbound message handler */
667 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
668 "msg_tx", (void *)mport);
673 * Configure outbound message unit
675 * Interrupts (all enabled, except QEIE)
679 out_be32(&priv->msg_regs->omr, 0x00100220);
681 /* Set number of entries */
682 out_be32(&priv->msg_regs->omr,
683 in_be32(&priv->msg_regs->omr) |
684 ((get_bitmask_order(entries) - 2) << 12));
686 /* Now enable the unit */
687 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
693 dma_free_coherent(priv->dev,
694 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
695 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
698 for (i = 0; i < priv->msg_tx_ring.size; i++)
699 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
700 priv->msg_tx_ring.virt_buffer[i],
701 priv->msg_tx_ring.phys_buffer[i]);
707 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
708 * @mport: Master port implementing the outbound message unit
709 * @mbox: Mailbox to close
711 * Disables the outbound message unit, free all buffers, and
712 * frees the outbound message interrupt.
714 static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
716 struct rio_priv *priv = mport->priv;
717 /* Disable inbound message unit */
718 out_be32(&priv->msg_regs->omr, 0);
721 dma_free_coherent(priv->dev,
722 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
723 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
726 free_irq(IRQ_RIO_TX(mport), (void *)mport);
730 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
731 * @irq: Linux interrupt number
732 * @dev_instance: Pointer to interrupt-specific data
734 * Handles inbound message interrupts. Executes a registered inbound
735 * mailbox event handler and acks the interrupt occurrence.
738 fsl_rio_rx_handler(int irq, void *dev_instance)
741 struct rio_mport *port = (struct rio_mport *)dev_instance;
742 struct rio_priv *priv = port->priv;
744 isr = in_be32(&priv->msg_regs->isr);
746 if (isr & RIO_MSG_ISR_TE) {
747 pr_info("RIO: inbound message reception error\n");
748 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
752 /* XXX Need to check/dispatch until queue empty */
753 if (isr & RIO_MSG_ISR_DIQI) {
755 * We implement *only* mailbox 0, but can receive messages
756 * for any mailbox/letter to that mailbox destination. So,
757 * make the callback with an unknown/invalid mailbox number
760 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
762 /* Ack the queueing interrupt */
763 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
771 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
772 * @mport: Master port implementing the inbound message unit
773 * @dev_id: Device specific pointer to pass on event
774 * @mbox: Mailbox to open
775 * @entries: Number of entries in the inbound mailbox ring
777 * Initializes buffer ring, request the inbound message interrupt,
778 * and enables the inbound message unit. Returns %0 on success
779 * and %-EINVAL or %-ENOMEM on failure.
782 fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
785 struct rio_priv *priv = mport->priv;
787 if ((entries < RIO_MIN_RX_RING_SIZE) ||
788 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
793 /* Initialize client buffer ring */
794 priv->msg_rx_ring.dev_id = dev_id;
795 priv->msg_rx_ring.size = entries;
796 priv->msg_rx_ring.rx_slot = 0;
797 for (i = 0; i < priv->msg_rx_ring.size; i++)
798 priv->msg_rx_ring.virt_buffer[i] = NULL;
800 /* Initialize inbound message ring */
801 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
802 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
803 &priv->msg_rx_ring.phys, GFP_KERNEL);
804 if (!priv->msg_rx_ring.virt) {
809 /* Point dequeue/enqueue pointers at first entry in ring */
810 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
811 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
813 /* Clear interrupt status */
814 out_be32(&priv->msg_regs->isr, 0x00000091);
816 /* Hook up inbound message handler */
817 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
818 "msg_rx", (void *)mport);
820 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
821 priv->msg_tx_ring.virt_buffer[i],
822 priv->msg_tx_ring.phys_buffer[i]);
827 * Configure inbound message unit:
829 * 4KB max message size
830 * Unmask all interrupt sources
833 out_be32(&priv->msg_regs->imr, 0x001b0060);
835 /* Set number of queue entries */
836 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
838 /* Now enable the unit */
839 setbits32(&priv->msg_regs->imr, 0x1);
846 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
847 * @mport: Master port implementing the inbound message unit
848 * @mbox: Mailbox to close
850 * Disables the inbound message unit, free all buffers, and
851 * frees the inbound message interrupt.
853 static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
855 struct rio_priv *priv = mport->priv;
856 /* Disable inbound message unit */
857 out_be32(&priv->msg_regs->imr, 0);
860 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
861 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
864 free_irq(IRQ_RIO_RX(mport), (void *)mport);
868 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
869 * @mport: Master port implementing the inbound message unit
870 * @mbox: Inbound mailbox number
871 * @buf: Buffer to add to inbound queue
873 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
874 * %0 on success or %-EINVAL on failure.
876 static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
879 struct rio_priv *priv = mport->priv;
881 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
882 priv->msg_rx_ring.rx_slot);
884 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
886 "RIO: error adding inbound buffer %d, buffer exists\n",
887 priv->msg_rx_ring.rx_slot);
892 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
893 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
894 priv->msg_rx_ring.rx_slot = 0;
901 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
902 * @mport: Master port implementing the inbound message unit
903 * @mbox: Inbound mailbox number
905 * Gets the next available inbound message from the inbound message queue.
906 * A pointer to the message is returned on success or NULL on failure.
908 static void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
910 struct rio_priv *priv = mport->priv;
911 u32 phys_buf, virt_buf;
915 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
917 /* If no more messages, then bail out */
918 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
921 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
922 - priv->msg_rx_ring.phys);
923 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
924 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
928 "RIO: inbound message copy failed, no buffers\n");
932 /* Copy max message size, caller is expected to allocate that big */
933 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
935 /* Clear the available buffer */
936 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
939 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
946 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
947 * @irq: Linux interrupt number
948 * @dev_instance: Pointer to interrupt-specific data
950 * Handles doorbell interrupts. Parses a list of registered
951 * doorbell event handlers and executes a matching event handler.
954 fsl_rio_dbell_handler(int irq, void *dev_instance)
957 struct rio_mport *port = (struct rio_mport *)dev_instance;
958 struct rio_priv *priv = port->priv;
960 dsr = in_be32(&priv->msg_regs->dsr);
962 if (dsr & DOORBELL_DSR_TE) {
963 pr_info("RIO: doorbell reception error\n");
964 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
968 if (dsr & DOORBELL_DSR_QFI) {
969 pr_info("RIO: doorbell queue full\n");
970 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
973 /* XXX Need to check/dispatch until queue empty */
974 if (dsr & DOORBELL_DSR_DIQI) {
976 (u32) priv->dbell_ring.virt +
977 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
978 struct rio_dbell *dbell;
982 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
983 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
985 list_for_each_entry(dbell, &port->dbells, node) {
986 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
987 (dbell->res->end >= DBELL_INF(dmsg))) {
993 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
997 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
998 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1000 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
1001 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
1009 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1010 * @mport: Master port implementing the inbound doorbell unit
1012 * Initializes doorbell unit hardware and inbound DMA buffer
1013 * ring. Called from fsl_rio_setup(). Returns %0 on success
1014 * or %-ENOMEM on failure.
1016 static int fsl_rio_doorbell_init(struct rio_mport *mport)
1018 struct rio_priv *priv = mport->priv;
1021 /* Map outbound doorbell window immediately after maintenance window */
1022 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1023 RIO_DBELL_WIN_SIZE);
1024 if (!priv->dbell_win) {
1026 "RIO: unable to map outbound doorbell window\n");
1031 /* Initialize inbound doorbells */
1032 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1033 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
1034 if (!priv->dbell_ring.virt) {
1035 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1037 iounmap(priv->dbell_win);
1041 /* Point dequeue/enqueue pointers at first entry in ring */
1042 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
1043 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
1045 /* Clear interrupt status */
1046 out_be32(&priv->msg_regs->dsr, 0x00000091);
1048 /* Hook up doorbell handler */
1049 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1050 "dbell_rx", (void *)mport);
1052 iounmap(priv->dbell_win);
1053 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1054 priv->dbell_ring.virt, priv->dbell_ring.phys);
1056 "MPC85xx RIO: unable to request inbound doorbell irq");
1060 /* Configure doorbells for snooping, 512 entries, and enable */
1061 out_be32(&priv->msg_regs->dmr, 0x00108161);
1068 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1069 * @irq: Linux interrupt number
1070 * @dev_instance: Pointer to interrupt-specific data
1072 * Handles port write interrupts. Parses a list of registered
1073 * port write event handlers and executes a matching event handler.
1076 fsl_rio_port_write_handler(int irq, void *dev_instance)
1079 struct rio_mport *port = (struct rio_mport *)dev_instance;
1080 struct rio_priv *priv = port->priv;
1083 epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1084 if (!(epwisr & RIO_EPWISR_PW))
1087 ipwmr = in_be32(&priv->msg_regs->pwmr);
1088 ipwsr = in_be32(&priv->msg_regs->pwsr);
1091 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1092 if (ipwsr & RIO_IPWSR_QF)
1094 if (ipwsr & RIO_IPWSR_TE)
1096 if (ipwsr & RIO_IPWSR_QFI)
1098 if (ipwsr & RIO_IPWSR_PWD)
1100 if (ipwsr & RIO_IPWSR_PWB)
1104 /* Schedule deferred processing if PW was received */
1105 if (ipwsr & RIO_IPWSR_QFI) {
1106 /* Save PW message (if there is room in FIFO),
1107 * otherwise discard it.
1109 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1110 priv->port_write_msg.msg_count++;
1111 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1114 priv->port_write_msg.discard_count++;
1115 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1116 priv->port_write_msg.discard_count);
1118 /* Clear interrupt and issue Clear Queue command. This allows
1119 * another port-write to be received.
1121 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI);
1122 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1124 schedule_work(&priv->pw_work);
1127 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1128 priv->port_write_msg.err_count++;
1129 pr_debug("RIO: Port-Write Transaction Err (%d)\n",
1130 priv->port_write_msg.err_count);
1131 /* Clear Transaction Error: port-write controller should be
1132 * disabled when clearing this error
1134 out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
1135 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE);
1136 out_be32(&priv->msg_regs->pwmr, ipwmr);
1139 if (ipwsr & RIO_IPWSR_PWD) {
1140 priv->port_write_msg.discard_count++;
1141 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1142 priv->port_write_msg.discard_count);
1143 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD);
1147 if (epwisr & RIO_EPWISR_PINT) {
1148 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1149 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1150 out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
1156 static void fsl_pw_dpc(struct work_struct *work)
1158 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1159 unsigned long flags;
1160 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1163 * Process port-write messages
1165 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1166 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1168 /* Process one message */
1169 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1173 pr_debug("%s : Port-Write Message:", __func__);
1174 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1176 pr_debug("\n0x%02x: 0x%08x", i*4,
1179 pr_debug(" 0x%08x", msg_buffer[i]);
1184 /* Pass the port-write message to RIO core for processing */
1185 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1186 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1188 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1192 * fsl_rio_pw_enable - enable/disable port-write interface init
1193 * @mport: Master port implementing the port write unit
1194 * @enable: 1=enable; 0=disable port-write message handling
1196 static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1198 struct rio_priv *priv = mport->priv;
1201 rval = in_be32(&priv->msg_regs->pwmr);
1204 rval |= RIO_IPWMR_PWE;
1206 rval &= ~RIO_IPWMR_PWE;
1208 out_be32(&priv->msg_regs->pwmr, rval);
1214 * fsl_rio_port_write_init - MPC85xx port write interface init
1215 * @mport: Master port implementing the port write unit
1217 * Initializes port write unit hardware and DMA buffer
1218 * ring. Called from fsl_rio_setup(). Returns %0 on success
1219 * or %-ENOMEM on failure.
1221 static int fsl_rio_port_write_init(struct rio_mport *mport)
1223 struct rio_priv *priv = mport->priv;
1226 /* Following configurations require a disabled port write controller */
1227 out_be32(&priv->msg_regs->pwmr,
1228 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1230 /* Initialize port write */
1231 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1233 &priv->port_write_msg.phys, GFP_KERNEL);
1234 if (!priv->port_write_msg.virt) {
1235 pr_err("RIO: unable allocate port write queue\n");
1239 priv->port_write_msg.err_count = 0;
1240 priv->port_write_msg.discard_count = 0;
1242 /* Point dequeue/enqueue pointers at first entry */
1243 out_be32(&priv->msg_regs->epwqbar, 0);
1244 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1246 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1247 in_be32(&priv->msg_regs->epwqbar),
1248 in_be32(&priv->msg_regs->pwqbar));
1250 /* Clear interrupt status IPWSR */
1251 out_be32(&priv->msg_regs->pwsr,
1252 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1254 /* Configure port write contoller for snooping enable all reporting,
1256 out_be32(&priv->msg_regs->pwmr,
1257 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1260 /* Hook up port-write handler */
1261 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
1262 "port-write", (void *)mport);
1264 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1268 INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1269 spin_lock_init(&priv->pw_fifo_lock);
1270 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1271 pr_err("FIFO allocation failed\n");
1276 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1277 in_be32(&priv->msg_regs->pwmr),
1278 in_be32(&priv->msg_regs->pwsr));
1283 free_irq(IRQ_RIO_PW(mport), (void *)mport);
1285 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1286 priv->port_write_msg.virt,
1287 priv->port_write_msg.phys);
1291 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1296 switch (ccsr >> 30) {
1307 dev_info(dev, "Hardware port width: %s\n", str);
1309 switch ((ccsr >> 27) & 7) {
1311 str = "Single-lane 0";
1314 str = "Single-lane 2";
1323 dev_info(dev, "Training connection status: %s\n", str);
1326 if (!(ccsr & 0x80000000))
1327 dev_info(dev, "Output port operating in 8-bit mode\n");
1328 if (!(ccsr & 0x08000000))
1329 dev_info(dev, "Input port operating in 8-bit mode\n");
1334 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
1335 * @dev: platform_device pointer
1337 * Initializes MPC85xx RapidIO hardware interface, configures
1338 * master port with system-specific info, and registers the
1339 * master port with the RapidIO subsystem.
1341 int fsl_rio_setup(struct platform_device *dev)
1343 struct rio_ops *ops;
1344 struct rio_mport *port;
1345 struct rio_priv *priv;
1347 const u32 *dt_range, *cell;
1348 struct resource regs;
1351 u64 law_start, law_size;
1354 if (!dev->dev.of_node) {
1355 dev_err(&dev->dev, "Device OF-Node is NULL");
1359 rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
1361 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1362 dev->dev.of_node->full_name);
1365 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name);
1366 dev_info(&dev->dev, "Regs: %pR\n", ®s);
1368 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
1370 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1371 dev->dev.of_node->full_name);
1375 /* Get node address wide */
1376 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1380 aw = of_n_addr_cells(dev->dev.of_node);
1381 /* Get node size wide */
1382 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1386 sw = of_n_size_cells(dev->dev.of_node);
1387 /* Get parent address wide wide */
1388 paw = of_n_addr_cells(dev->dev.of_node);
1390 law_start = of_read_number(dt_range + aw, paw);
1391 law_size = of_read_number(dt_range + aw + paw, sw);
1393 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1394 law_start, law_size);
1396 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
1401 ops->lcread = fsl_local_config_read;
1402 ops->lcwrite = fsl_local_config_write;
1403 ops->cread = fsl_rio_config_read;
1404 ops->cwrite = fsl_rio_config_write;
1405 ops->dsend = fsl_rio_doorbell_send;
1406 ops->pwenable = fsl_rio_pw_enable;
1407 ops->open_outb_mbox = fsl_open_outb_mbox;
1408 ops->open_inb_mbox = fsl_open_inb_mbox;
1409 ops->close_outb_mbox = fsl_close_outb_mbox;
1410 ops->close_inb_mbox = fsl_close_inb_mbox;
1411 ops->add_outb_message = fsl_add_outb_message;
1412 ops->add_inb_buffer = fsl_add_inb_buffer;
1413 ops->get_inb_message = fsl_get_inb_message;
1415 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1422 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
1424 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
1429 INIT_LIST_HEAD(&port->dbells);
1430 port->iores.start = law_start;
1431 port->iores.end = law_start + law_size - 1;
1432 port->iores.flags = IORESOURCE_MEM;
1433 port->iores.name = "rio_io_win";
1435 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
1436 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
1437 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
1438 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
1439 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
1440 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
1442 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1443 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1444 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1445 strcpy(port->name, "RIO0 mport");
1447 priv->dev = &dev->dev;
1451 port->phys_efptr = 0x100;
1452 rio_register_mport(port);
1454 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1455 rio_regs_win = priv->regs_win;
1457 /* Probe the master port phy type */
1458 ccsr = in_be32(priv->regs_win + RIO_CCSR);
1459 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
1460 dev_info(&dev->dev, "RapidIO PHY type: %s\n",
1461 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
1462 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
1464 /* Checking the port training status */
1465 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1466 dev_err(&dev->dev, "Port is not ready. "
1467 "Try to restart connection...\n");
1468 switch (port->phy_type) {
1469 case RIO_PHY_SERIAL:
1471 out_be32(priv->regs_win + RIO_CCSR, 0);
1473 setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
1475 setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
1477 case RIO_PHY_PARALLEL:
1479 out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
1481 out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
1485 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1486 dev_err(&dev->dev, "Port restart failed.\n");
1490 dev_info(&dev->dev, "Port restart success!\n");
1492 fsl_rio_info(&dev->dev, ccsr);
1494 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1495 & RIO_PEF_CTLS) >> 4;
1496 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1497 port->sys_size ? 65536 : 256);
1499 if (port->host_deviceid >= 0)
1500 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
1501 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
1503 out_be32(priv->regs_win + RIO_GCCSR, 0x00000000);
1505 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1506 + RIO_ATMU_REGS_OFFSET);
1507 priv->maint_atmu_regs = priv->atmu_regs + 1;
1508 priv->dbell_atmu_regs = priv->atmu_regs + 2;
1509 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1510 ((port->phy_type == RIO_PHY_SERIAL) ?
1511 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1513 /* Set to receive any dist ID for serial RapidIO controller. */
1514 if (port->phy_type == RIO_PHY_SERIAL)
1515 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1517 /* Configure maintenance transaction window */
1518 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1519 out_be32(&priv->maint_atmu_regs->rowar,
1520 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
1522 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1524 /* Configure outbound doorbell window */
1525 out_be32(&priv->dbell_atmu_regs->rowbar,
1526 (law_start + RIO_MAINT_WIN_SIZE) >> 12);
1527 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */
1528 fsl_rio_doorbell_init(port);
1529 fsl_rio_port_write_init(port);
1532 saved_mcheck_exception = ppc_md.machine_check_exception;
1533 ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
1538 iounmap(priv->regs_win);
1548 /* The probe function for RapidIO peer-to-peer network.
1550 static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev)
1552 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1553 dev->dev.of_node->full_name);
1555 return fsl_rio_setup(dev);
1558 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1560 .compatible = "fsl,rapidio-delta",
1565 static struct platform_driver fsl_of_rio_rpn_driver = {
1567 .name = "fsl-of-rio",
1568 .owner = THIS_MODULE,
1569 .of_match_table = fsl_of_rio_rpn_ids,
1571 .probe = fsl_of_rio_rpn_probe,
1574 static __init int fsl_of_rio_rpn_init(void)
1576 return platform_driver_register(&fsl_of_rio_rpn_driver);
1579 subsys_initcall(fsl_of_rio_rpn_init);