3 * Copyright IBM Corp. 1999
4 * Author(s): Hartmut Penner (hp@de.ibm.com),
5 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 * Derived from "include/asm-i386/processor.h"
8 * Copyright (C) 1994, Linus Torvalds
11 #ifndef __ASM_S390_PROCESSOR_H
12 #define __ASM_S390_PROCESSOR_H
16 #include <linux/linkage.h>
17 #include <linux/irqflags.h>
20 #include <asm/ptrace.h>
21 #include <asm/setup.h>
22 #include <asm/runtime_instr.h>
25 * Default implementation of macro that returns current
26 * instruction pointer ("program counter").
28 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
30 static inline void get_cpu_id(struct cpuid *ptr)
32 asm volatile("stidp %0" : "=Q" (*ptr));
35 extern void s390_adjust_jiffies(void);
36 extern const struct seq_operations cpuinfo_op;
37 extern int sysctl_ieee_emulation_warnings;
38 extern void execve_tail(void);
41 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
45 #define TASK_SIZE (1UL << 31)
46 #define TASK_MAX_SIZE (1UL << 31)
47 #define TASK_UNMAPPED_BASE (1UL << 30)
49 #else /* CONFIG_64BIT */
51 #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
52 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
53 (1UL << 30) : (1UL << 41))
54 #define TASK_SIZE TASK_SIZE_OF(current)
55 #define TASK_MAX_SIZE (1UL << 53)
57 #endif /* CONFIG_64BIT */
60 #define STACK_TOP (1UL << 31)
61 #define STACK_TOP_MAX (1UL << 31)
62 #else /* CONFIG_64BIT */
63 #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
64 #define STACK_TOP_MAX (1UL << 42)
65 #endif /* CONFIG_64BIT */
67 #define HAVE_ARCH_PICK_MMAP_LAYOUT
76 struct thread_struct {
78 unsigned int acrs[NUM_ACRS];
79 unsigned long ksp; /* kernel stack pointer */
80 mm_segment_t mm_segment;
81 unsigned long gmap_addr; /* address of last gmap fault. */
82 unsigned int gmap_pfault; /* signal of a pending guest pfault */
83 struct per_regs per_user; /* User specified PER registers */
84 struct per_event per_event; /* Cause of the last PER trap */
85 unsigned long per_flags; /* Flags to control debug behavior */
86 /* pfault_wait is used to block the process on a pfault event */
87 unsigned long pfault_wait;
88 struct list_head list;
89 /* cpu runtime instrumentation */
90 struct runtime_instr_cb *ri_cb;
93 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
97 /* Flag to disable transactions. */
98 #define PER_FLAG_NO_TE 1UL
99 /* Flag to enable random transaction aborts. */
100 #define PER_FLAG_TE_ABORT_RAND 2UL
101 /* Flag to specify random transaction abort mode:
102 * - abort each transaction at a random instruction before TEND if set.
103 * - abort random transactions at a random instruction if cleared.
105 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
107 typedef struct thread_struct thread_struct;
110 * Stack layout of a C stack frame.
114 unsigned long back_chain;
115 unsigned long empty1[5];
116 unsigned long gprs[10];
117 unsigned int empty2[8];
121 unsigned long empty1[5];
122 unsigned int empty2[8];
123 unsigned long gprs[10];
124 unsigned long back_chain;
128 #define ARCH_MIN_TASKALIGN 8
130 #define INIT_THREAD { \
131 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
135 * Do necessary setup to start up a new thread.
137 #define start_thread(regs, new_psw, new_stackp) do { \
138 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
139 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
140 regs->gprs[15] = new_stackp; \
144 #define start_thread31(regs, new_psw, new_stackp) do { \
145 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
146 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
147 regs->gprs[15] = new_stackp; \
148 crst_table_downgrade(current->mm, 1UL << 31); \
152 /* Forward declaration, a strange C thing */
158 extern void show_cacheinfo(struct seq_file *m);
160 static inline void show_cacheinfo(struct seq_file *m) { }
163 /* Free all resources held by a thread. */
164 extern void release_thread(struct task_struct *);
167 * Return saved PC of a blocked thread.
169 extern unsigned long thread_saved_pc(struct task_struct *t);
171 unsigned long get_wchan(struct task_struct *p);
172 #define task_pt_regs(tsk) ((struct pt_regs *) \
173 (task_stack_page(tsk) + THREAD_SIZE) - 1)
174 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
175 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
177 /* Has task runtime instrumentation enabled ? */
178 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
180 static inline unsigned short stap(void)
182 unsigned short cpu_address;
184 asm volatile("stap %0" : "=m" (cpu_address));
189 * Give up the time slice of the virtual PU.
191 static inline void cpu_relax(void)
193 if (MACHINE_HAS_DIAG44)
194 asm volatile("diag 0,0,68");
198 #define arch_mutex_cpu_relax() barrier()
200 static inline void psw_set_key(unsigned int key)
202 asm volatile("spka 0(%0)" : : "d" (key));
206 * Set PSW to specified value.
208 static inline void __load_psw(psw_t psw)
211 asm volatile("lpsw %0" : : "Q" (psw) : "cc");
213 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
218 * Set PSW mask to specified value, while leaving the
219 * PSW addr pointing to the next instruction.
221 static inline void __load_psw_mask (unsigned long mask)
232 " st %0,%O1+4(%R1)\n"
235 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
236 #else /* CONFIG_64BIT */
239 " stg %0,%O1+8(%R1)\n"
242 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
243 #endif /* CONFIG_64BIT */
247 * Rewind PSW instruction address by specified number of bytes.
249 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
252 if (psw.addr & PSW_ADDR_AMODE)
254 return (psw.addr - ilc) | PSW_ADDR_AMODE;
256 return (psw.addr - ilc) & ((1UL << 24) - 1);
260 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
261 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
263 return (psw.addr - ilc) & mask;
268 * Function to drop a processor into disabled wait state
270 static inline void __noreturn disabled_wait(unsigned long code)
272 unsigned long ctl_buf;
275 dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
278 * Store status and then load disabled wait psw,
279 * the processor is dead afterwards
284 " ni 0(%2),0xef\n" /* switch off protection */
286 " stpt 0xd8\n" /* store timer */
287 " stckc 0xe0\n" /* store clock comparator */
288 " stpx 0x108\n" /* store prefix register */
289 " stam 0,15,0x120\n" /* store access registers */
290 " std 0,0x160\n" /* store f0 */
291 " std 2,0x168\n" /* store f2 */
292 " std 4,0x170\n" /* store f4 */
293 " std 6,0x178\n" /* store f6 */
294 " stm 0,15,0x180\n" /* store general registers */
295 " stctl 0,15,0x1c0\n" /* store control registers */
296 " oi 0x1c0,0x10\n" /* fake protection bit */
299 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
300 #else /* CONFIG_64BIT */
303 " ni 4(%2),0xef\n" /* switch off protection */
306 " stpt 0x328(1)\n" /* store timer */
307 " stckc 0x330(1)\n" /* store clock comparator */
308 " stpx 0x318(1)\n" /* store prefix register */
309 " stam 0,15,0x340(1)\n"/* store access registers */
310 " stfpc 0x31c(1)\n" /* store fpu control */
311 " std 0,0x200(1)\n" /* store f0 */
312 " std 1,0x208(1)\n" /* store f1 */
313 " std 2,0x210(1)\n" /* store f2 */
314 " std 3,0x218(1)\n" /* store f3 */
315 " std 4,0x220(1)\n" /* store f4 */
316 " std 5,0x228(1)\n" /* store f5 */
317 " std 6,0x230(1)\n" /* store f6 */
318 " std 7,0x238(1)\n" /* store f7 */
319 " std 8,0x240(1)\n" /* store f8 */
320 " std 9,0x248(1)\n" /* store f9 */
321 " std 10,0x250(1)\n" /* store f10 */
322 " std 11,0x258(1)\n" /* store f11 */
323 " std 12,0x260(1)\n" /* store f12 */
324 " std 13,0x268(1)\n" /* store f13 */
325 " std 14,0x270(1)\n" /* store f14 */
326 " std 15,0x278(1)\n" /* store f15 */
327 " stmg 0,15,0x280(1)\n"/* store general registers */
328 " stctg 0,15,0x380(1)\n"/* store control registers */
329 " oi 0x384(1),0x10\n"/* fake protection bit */
332 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
333 #endif /* CONFIG_64BIT */
338 * Use to set psw mask except for the first byte which
339 * won't be changed by this function.
342 __set_psw_mask(unsigned long mask)
344 __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
347 #define local_mcck_enable() \
348 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
349 #define local_mcck_disable() \
350 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)
353 * Basic Machine Check/Program Check Handler.
356 extern void s390_base_mcck_handler(void);
357 extern void s390_base_pgm_handler(void);
358 extern void s390_base_ext_handler(void);
360 extern void (*s390_base_mcck_handler_fn)(void);
361 extern void (*s390_base_pgm_handler_fn)(void);
362 extern void (*s390_base_ext_handler_fn)(void);
364 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
366 extern int memcpy_real(void *, void *, size_t);
367 extern void memcpy_absolute(void *, void *, size_t);
369 #define mem_assign_absolute(dest, val) { \
370 __typeof__(dest) __tmp = (val); \
372 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
373 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
377 * Helper macro for exception table entries
379 #define EX_TABLE(_fault, _target) \
380 ".section __ex_table,\"a\"\n" \
382 ".long (" #_fault ") - .\n" \
383 ".long (" #_target ") - .\n" \
386 #else /* __ASSEMBLY__ */
388 #define EX_TABLE(_fault, _target) \
389 .section __ex_table,"a" ; \
391 .long (_fault) - . ; \
392 .long (_target) - . ; \
395 #endif /* __ASSEMBLY__ */
397 #endif /* __ASM_S390_PROCESSOR_H */